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-rw-r--r--firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c16
1 files changed, 13 insertions, 3 deletions
diff --git a/firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c b/firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c
index 73673cdd67..d4839893d3 100644
--- a/firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c
+++ b/firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c
@@ -21,6 +21,7 @@
21 21
22 22
23#include "config.h" 23#include "config.h"
24#include "panic.h"
24#include "system.h" 25#include "system.h"
25#include "kernel.h" 26#include "kernel.h"
26#include "cpu.h" 27#include "cpu.h"
@@ -188,6 +189,7 @@ uint32_t nand_reset(uint32_t bank)
188 if (nand_send_cmd(NAND_CMD_RESET)) return 1; 189 if (nand_send_cmd(NAND_CMD_RESET)) return 1;
189 if (nand_wait_chip_ready(bank)) return 1; 190 if (nand_wait_chip_ready(bank)) return 1;
190 FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO; 191 FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
192 sleep(0);
191 return 0; 193 return 0;
192} 194}
193 195
@@ -197,7 +199,7 @@ uint32_t nand_wait_status_ready(uint32_t bank)
197 nand_set_fmctrl0(bank, 0); 199 nand_set_fmctrl0(bank, 0);
198 if ((FMCSTAT & (FMCSTAT_BANK0READY << bank))) 200 if ((FMCSTAT & (FMCSTAT_BANK0READY << bank)))
199 FMCSTAT = (FMCSTAT_BANK0READY << bank); 201 FMCSTAT = (FMCSTAT_BANK0READY << bank);
200 FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO; 202 FMCTRL1 = FMCTRL1_CLEARRFIFO;
201 if (nand_send_cmd(NAND_CMD_GET_STATUS)) return 1; 203 if (nand_send_cmd(NAND_CMD_GET_STATUS)) return 1;
202 while (1) 204 while (1)
203 { 205 {
@@ -234,6 +236,7 @@ uint32_t nand_transfer_data(uint32_t bank, uint32_t direction,
234 if (!direction) invalidate_dcache(); 236 if (!direction) invalidate_dcache();
235 if (nand_wait_addrdone()) return 1; 237 if (nand_wait_addrdone()) return 1;
236 if (!direction) FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO; 238 if (!direction) FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
239 else FMCTRL1 = FMCTRL1_CLEARRFIFO;
237 return 0; 240 return 0;
238} 241}
239 242
@@ -298,7 +301,7 @@ uint32_t nand_get_chip_type(uint32_t bank)
298 FMCTRL1 = FMCTRL1_DOREADDATA; 301 FMCTRL1 = FMCTRL1_DOREADDATA;
299 if (nand_wait_addrdone()) return nand_unlock(0xFFFFFFFF); 302 if (nand_wait_addrdone()) return nand_unlock(0xFFFFFFFF);
300 result = FMFIFO; 303 result = FMFIFO;
301 FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO; 304 FMCTRL1 = FMCTRL1_CLEARRFIFO;
302 return nand_unlock(result); 305 return nand_unlock(result);
303} 306}
304 307
@@ -331,7 +334,14 @@ void nand_power_up(void)
331 pmu_ldo_power_on(4); 334 pmu_ldo_power_on(4);
332 sleep(HZ / 20); 335 sleep(HZ / 20);
333 nand_last_activity_value = current_tick; 336 nand_last_activity_value = current_tick;
334 for (i = 0; i < 4; i++) nand_reset(i); 337 for (i = 0; i < 4; i++)
338 {
339 if(nand_type[i] != 0xFFFFFFFF)
340 {
341 if(nand_reset(i))
342 if(nand_reset(i)) panicf("nand_power_up: nand_reset(bank=%d) failed.",(unsigned int)i);
343 }
344 }
335 nand_powered = 1; 345 nand_powered = 1;
336 nand_last_activity_value = current_tick; 346 nand_last_activity_value = current_tick;
337 mutex_unlock(&nand_mtx); 347 mutex_unlock(&nand_mtx);