diff options
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/system.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/firmware/system.c b/firmware/system.c index af2b74a17a..846a4434f7 100644 --- a/firmware/system.c +++ b/firmware/system.c | |||
@@ -624,7 +624,7 @@ void set_cpu_frequency(long frequency) | |||
624 | timers_adjust_prescale(CPUFREQ_MAX_MULT, true); | 624 | timers_adjust_prescale(CPUFREQ_MAX_MULT, true); |
625 | DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */ | 625 | DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */ |
626 | cpu_frequency = CPUFREQ_MAX; | 626 | cpu_frequency = CPUFREQ_MAX; |
627 | IDECONFIG1 = 0x10100000 | (3 << 13) | (5 << 10); | 627 | IDECONFIG1 = 0x10100000 | (1 << 13) | (2 << 10); |
628 | /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ | 628 | /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ |
629 | IDECONFIG2 = 0x40000 | (2 << 8); /* TA enable + CS2wait */ | 629 | IDECONFIG2 = 0x40000 | (2 << 8); /* TA enable + CS2wait */ |
630 | break; | 630 | break; |
@@ -646,7 +646,7 @@ void set_cpu_frequency(long frequency) | |||
646 | timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true); | 646 | timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true); |
647 | DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */ | 647 | DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */ |
648 | cpu_frequency = CPUFREQ_NORMAL; | 648 | cpu_frequency = CPUFREQ_NORMAL; |
649 | IDECONFIG1 = 0x10100000 | (3 << 13) | (5 << 10); | 649 | IDECONFIG1 = 0x10100000 | (0 << 13) | (1 << 10); |
650 | /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ | 650 | /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ |
651 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ | 651 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ |
652 | break; | 652 | break; |
@@ -664,7 +664,7 @@ void set_cpu_frequency(long frequency) | |||
664 | #endif | 664 | #endif |
665 | DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ | 665 | DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ |
666 | cpu_frequency = CPUFREQ_DEFAULT; | 666 | cpu_frequency = CPUFREQ_DEFAULT; |
667 | IDECONFIG1 = 0x10100000 | (3 << 13) | (1 << 10); | 667 | IDECONFIG1 = 0x10100000 | (0 << 13) | (1 << 10); |
668 | /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ | 668 | /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ |
669 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ | 669 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ |
670 | break; | 670 | break; |