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-rw-r--r--firmware/export/imx233.h14
-rw-r--r--firmware/target/arm/imx233/boot.lds6
-rw-r--r--firmware/target/arm/imx233/system-imx233.c27
-rw-r--r--firmware/target/arm/mmu-arm.S4
4 files changed, 35 insertions, 16 deletions
diff --git a/firmware/export/imx233.h b/firmware/export/imx233.h
index 182442c2ab..682240ac40 100644
--- a/firmware/export/imx233.h
+++ b/firmware/export/imx233.h
@@ -24,12 +24,14 @@
24#define IRAM_ORIG 0 24#define IRAM_ORIG 0
25#define IRAM_SIZE 0x8000 25#define IRAM_SIZE 0x8000
26#define DRAM_ORIG 0x40000000 26#define DRAM_ORIG 0x40000000
27#define DRAM_SIZE 0x20000000 27#define DRAM_SIZE (MEMORYSIZE * 0x100000)
28 28
29#define TTB_BASE_ADDR (DRAM_ORIG + (MEMORYSIZE*0x100000) - TTB_SIZE) 29#define TTB_BASE_ADDR (IRAM_ORIG + IRAM_SIZE - TTB_SIZE)
30#define TTB_SIZE (0x4000) 30#define TTB_SIZE 0x4000
31#define TTB_BASE ((unsigned long *)TTB_BASE_ADDR) 31#define TTB_BASE ((unsigned long *)TTB_BASE_ADDR)
32#define FRAME_SIZE (240*320*2) 32#define FRAME_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_DEPTH / 8)
33#define LCD_FRAME_ADDR (DRAM_ORIG + DRAM_SIZE - FRAME_SIZE)
34#define FRAME ((unsigned short *)LCD_FRAME_ADDR)
33 35
34/* USBOTG */ 36/* USBOTG */
35#define USB_QHARRAY_ATTR __attribute__((section(".qharray"),nocommon,aligned(2048))) 37#define USB_QHARRAY_ATTR __attribute__((section(".qharray"),nocommon,aligned(2048)))
@@ -48,5 +50,7 @@
48#define __BLOCK_SFTRST (1 << 31) 50#define __BLOCK_SFTRST (1 << 31)
49#define __BLOCK_CLKGATE (1 << 30) 51#define __BLOCK_CLKGATE (1 << 30)
50 52
53#define CACHEALIGN_BITS 4
54
51 55
52#endif /* __IMX233_H__ */ 56#endif /* __IMX233_H__ */
diff --git a/firmware/target/arm/imx233/boot.lds b/firmware/target/arm/imx233/boot.lds
index cb925b055e..0a8f0ed8f8 100644
--- a/firmware/target/arm/imx233/boot.lds
+++ b/firmware/target/arm/imx233/boot.lds
@@ -8,8 +8,8 @@ STARTUP(target/arm/imx233/crt0.o)
8 8
9MEMORY 9MEMORY
10{ 10{
11 IRAM : ORIGIN = IRAM_ORIG, LENGTH = IRAM_SIZE 11 IRAM : ORIGIN = IRAM_ORIG, LENGTH = IRAM_SIZE - TTB_SIZE
12 DRAM : ORIGIN = DRAM_ORIG, LENGTH = DRAM_SIZE - TTB_SIZE 12 DRAM : ORIGIN = DRAM_ORIG, LENGTH = DRAM_SIZE - FRAME_SIZE
13} 13}
14 14
15SECTIONS 15SECTIONS
@@ -30,7 +30,7 @@ SECTIONS
30 { 30 {
31 _iramstart = .; // always 0 31 _iramstart = .; // always 0
32 *(.vectors) 32 *(.vectors)
33 KEEP(*(.vectors));// otherwise there are no reference to it and the linker strip it 33 KEEP(*(.vectors));// otherwise there are no references to it and the linker strip it
34 *(.icode) 34 *(.icode)
35 *(.irodata) 35 *(.irodata)
36 *(.idata) 36 *(.idata)
diff --git a/firmware/target/arm/imx233/system-imx233.c b/firmware/target/arm/imx233/system-imx233.c
index 58f12506df..c4a32dd46e 100644
--- a/firmware/target/arm/imx233/system-imx233.c
+++ b/firmware/target/arm/imx233/system-imx233.c
@@ -141,6 +141,25 @@ void imx233_softirq(int src, bool enable)
141 __REG_CLR(HW_ICOLL_INTERRUPT(src)) = HW_ICOLL_INTERRUPT__SOFTIRQ; 141 __REG_CLR(HW_ICOLL_INTERRUPT(src)) = HW_ICOLL_INTERRUPT__SOFTIRQ;
142} 142}
143 143
144static void set_page_tables(void)
145{
146 /* map every memory region to itself */
147 map_section(0, 0, 0x1000, CACHE_NONE);
148
149 /* map RAM and enable caching for it */
150 map_section(DRAM_ORIG, DRAM_ORIG, MEMORYSIZE, CACHE_ALL);
151
152 /* enable buffered writing for the framebuffer */
153 map_section((int)FRAME, (int)FRAME, 1, BUFFERED);
154}
155
156void memory_init(void)
157{
158 ttb_init();
159 set_page_tables();
160 enable_mmu();
161}
162
144void system_init(void) 163void system_init(void)
145{ 164{
146 /* disable all interrupts */ 165 /* disable all interrupts */
@@ -158,14 +177,6 @@ void system_init(void)
158 imx233_timrot_init(); 177 imx233_timrot_init();
159 imx233_dma_init(); 178 imx233_dma_init();
160 imx233_ssp_init(); 179 imx233_ssp_init();
161 imx233_i2c_init();
162}
163
164void power_off(void)
165{
166 /* power down */
167 HW_POWER_RESET = HW_POWER_RESET__UNLOCK | HW_POWER_RESET__PWD;
168 while(1);
169} 180}
170 181
171bool imx233_us_elapsed(uint32_t ref, unsigned us_delay) 182bool imx233_us_elapsed(uint32_t ref, unsigned us_delay)
diff --git a/firmware/target/arm/mmu-arm.S b/firmware/target/arm/mmu-arm.S
index 24abfec1a7..39f0edbfce 100644
--- a/firmware/target/arm/mmu-arm.S
+++ b/firmware/target/arm/mmu-arm.S
@@ -44,6 +44,10 @@
44/* MMU not present */ 44/* MMU not present */
45#define CACHE_SIZE 4 45#define CACHE_SIZE 4
46 46
47#elif CONFIG_CPU == IMX233
48#define USE_MMU
49#define CACHE_SIZE 16
50
47#else 51#else
48#error Cache settings unknown for this CPU ! 52#error Cache settings unknown for this CPU !
49 53