diff options
Diffstat (limited to 'firmware/timer.c')
-rw-r--r-- | firmware/timer.c | 48 |
1 files changed, 45 insertions, 3 deletions
diff --git a/firmware/timer.c b/firmware/timer.c index 849e4ba598..ca23cb890c 100644 --- a/firmware/timer.c +++ b/firmware/timer.c | |||
@@ -28,7 +28,7 @@ static void (*pfn_timer)(void) = NULL; /* timer callback */ | |||
28 | static void (*pfn_unregister)(void) = NULL; /* unregister callback */ | 28 | static void (*pfn_unregister)(void) = NULL; /* unregister callback */ |
29 | #ifdef CPU_COLDFIRE | 29 | #ifdef CPU_COLDFIRE |
30 | static int base_prescale; | 30 | static int base_prescale; |
31 | #elif defined CPU_PP | 31 | #elif defined CPU_PP || CONFIG_CPU == PNX0101 |
32 | static long cycles_new = 0; | 32 | static long cycles_new = 0; |
33 | #endif | 33 | #endif |
34 | 34 | ||
@@ -67,6 +67,24 @@ void TIMER2(void) | |||
67 | cycles_new = 0; | 67 | cycles_new = 0; |
68 | } | 68 | } |
69 | } | 69 | } |
70 | #elif CONFIG_CPU == PNX0101 | ||
71 | void TIMER1_ISR(void) | ||
72 | { | ||
73 | if (cycles_new > 0) | ||
74 | { | ||
75 | TIMER1.load = cycles_new - 1; | ||
76 | cycles_new = 0; | ||
77 | } | ||
78 | if (pfn_timer != NULL) | ||
79 | { | ||
80 | cycles_new = -1; | ||
81 | /* "lock" the variable, in case timer_set_period() | ||
82 | * is called within pfn_timer() */ | ||
83 | pfn_timer(); | ||
84 | cycles_new = 0; | ||
85 | } | ||
86 | TIMER1.clr = 1; /* clear the interrupt */ | ||
87 | } | ||
70 | #endif /* CONFIG_CPU */ | 88 | #endif /* CONFIG_CPU */ |
71 | 89 | ||
72 | static bool timer_set(long cycles, bool start) | 90 | static bool timer_set(long cycles, bool start) |
@@ -85,8 +103,26 @@ static bool timer_set(long cycles, bool start) | |||
85 | } | 103 | } |
86 | #endif | 104 | #endif |
87 | 105 | ||
88 | #if CONFIG_CPU == PNX0101 /* TODO: Implement for iFP */ | 106 | #if CONFIG_CPU == PNX0101 |
89 | (void)start; | 107 | if (start) |
108 | { | ||
109 | if (pfn_unregister != NULL) | ||
110 | { | ||
111 | pfn_unregister(); | ||
112 | pfn_unregister = NULL; | ||
113 | } | ||
114 | TIMER1.ctrl &= ~0x80; /* disable the counter */ | ||
115 | TIMER1.ctrl |= 0x40; /* reload after counting down to zero */ | ||
116 | TIMER1.ctrl &= ~0xc; /* no prescaler */ | ||
117 | TIMER1.clr = 1; /* clear an interrupt event */ | ||
118 | } | ||
119 | if (start || (cycles_new == -1)) /* within isr, cycles_new is "locked" */ | ||
120 | { /* enable timer */ | ||
121 | TIMER1.load = cycles - 1; | ||
122 | TIMER1.ctrl |= 0x80; /* enable the counter */ | ||
123 | } | ||
124 | else | ||
125 | cycles_new = cycles; | ||
90 | #endif | 126 | #endif |
91 | 127 | ||
92 | #if CONFIG_CPU == SH7034 | 128 | #if CONFIG_CPU == SH7034 |
@@ -229,6 +265,9 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void), | |||
229 | #elif defined(CPU_PP) | 265 | #elif defined(CPU_PP) |
230 | /* unmask interrupt source */ | 266 | /* unmask interrupt source */ |
231 | CPU_INT_EN = TIMER2_MASK; | 267 | CPU_INT_EN = TIMER2_MASK; |
268 | #elif CONFIG_CPU == PNX0101 | ||
269 | irq_set_int_handler(IRQ_TIMER1, TIMER1_ISR); | ||
270 | irq_enable_int(IRQ_TIMER1); | ||
232 | #endif | 271 | #endif |
233 | return true; | 272 | return true; |
234 | } | 273 | } |
@@ -249,6 +288,9 @@ void timer_unregister(void) | |||
249 | #elif defined(CPU_PP) | 288 | #elif defined(CPU_PP) |
250 | TIMER2_CFG = 0; /* stop timer 2 */ | 289 | TIMER2_CFG = 0; /* stop timer 2 */ |
251 | CPU_INT_CLR = TIMER2_MASK; | 290 | CPU_INT_CLR = TIMER2_MASK; |
291 | #elif CONFIG_CPU == PNX0101 | ||
292 | TIMER1.ctrl &= ~0x80; /* disable timer 1 */ | ||
293 | irq_disable_int(5); | ||
252 | #endif | 294 | #endif |
253 | pfn_timer = NULL; | 295 | pfn_timer = NULL; |
254 | pfn_unregister = NULL; | 296 | pfn_unregister = NULL; |