diff options
Diffstat (limited to 'firmware/test/i2c/main.c')
-rw-r--r-- | firmware/test/i2c/main.c | 257 |
1 files changed, 123 insertions, 134 deletions
diff --git a/firmware/test/i2c/main.c b/firmware/test/i2c/main.c index b5aecec733..9010af2d59 100644 --- a/firmware/test/i2c/main.c +++ b/firmware/test/i2c/main.c | |||
@@ -16,10 +16,12 @@ | |||
16 | * KIND, either express or implied. | 16 | * KIND, either express or implied. |
17 | * | 17 | * |
18 | ****************************************************************************/ | 18 | ****************************************************************************/ |
19 | #include "types.h" | ||
19 | #include "i2c.h" | 20 | #include "i2c.h" |
20 | #include "mas.h" | 21 | #include "mas.h" |
21 | #include "sh7034.h" | 22 | #include "sh7034.h" |
22 | #include "debug.h" | 23 | #include "debug.h" |
24 | #include "kernel.h" | ||
23 | 25 | ||
24 | unsigned char fliptable[] = | 26 | unsigned char fliptable[] = |
25 | { | 27 | { |
@@ -59,10 +61,14 @@ unsigned char fliptable[] = | |||
59 | 61 | ||
60 | extern unsigned char mp3data[]; | 62 | extern unsigned char mp3data[]; |
61 | extern int mp3datalen; | 63 | extern int mp3datalen; |
64 | unsigned char *mp3dataptr; | ||
65 | int mp3_transmitted; | ||
66 | |||
67 | bool dma_on; | ||
62 | 68 | ||
63 | void setup_sci0(void) | 69 | void setup_sci0(void) |
64 | { | 70 | { |
65 | PBCR1 = (PBCR1 & 0xccff) | 0x0200; | 71 | PBCR1 = (PBCR1 & 0xccff) | 0x1200; |
66 | 72 | ||
67 | /* set PB12 to output */ | 73 | /* set PB12 to output */ |
68 | PBIOR |= 0x1000; | 74 | PBIOR |= 0x1000; |
@@ -86,19 +92,20 @@ void setup_sci0(void) | |||
86 | IPRD &= 0x0ff0; | 92 | IPRD &= 0x0ff0; |
87 | 93 | ||
88 | /* set IRQ6 and IRQ7 to edge detect */ | 94 | /* set IRQ6 and IRQ7 to edge detect */ |
89 | // ICR |= 0x03; | 95 | ICR |= 0x03; |
90 | 96 | ||
91 | /* set PB15 and PB14 to inputs */ | 97 | /* set PB15 and PB14 to inputs */ |
92 | PBIOR &= 0x7fff; | 98 | PBIOR &= 0x7fff; |
93 | PBIOR &= 0xbfff; | 99 | PBIOR &= 0xbfff; |
94 | 100 | ||
95 | /* set IRQ6 prio 8 and IRQ7 prio 0 */ | 101 | /* set IRQ6 prio 8 and IRQ7 prio 0 */ |
96 | // IPRB = ( IPRB & 0xff00 ) | 0x80; | 102 | IPRB = ( IPRB & 0xff00 ) | 0x0080; |
97 | 103 | ||
98 | IPRB = 0; | 104 | /* Enable End of DMA interrupt at prio 8 */ |
105 | IPRC = (IPRC & 0xf0ff) | 0x0800; | ||
99 | 106 | ||
100 | /* Enable Tx (only!) */ | 107 | /* Enable Tx (only!) */ |
101 | SCR0 |= 0xa0; | 108 | // SCR0 |= 0xa0; |
102 | } | 109 | } |
103 | 110 | ||
104 | int mas_tx_ready(void) | 111 | int mas_tx_ready(void) |
@@ -109,160 +116,142 @@ int mas_tx_ready(void) | |||
109 | void init_dma(void) | 116 | void init_dma(void) |
110 | { | 117 | { |
111 | SAR3 = (unsigned int) mp3data; | 118 | SAR3 = (unsigned int) mp3data; |
112 | DAR3 = 0xFFFFEC3; | 119 | DAR3 = 0x5FFFEC3; |
113 | CHCR3 = 0x1500; /* Single address destination, TXI0 */ | 120 | CHCR3 &= ~0x0002; /* Clear interrupt */ |
121 | CHCR3 = 0x1504; /* Single address destination, TXI0, IE=1 */ | ||
114 | DTCR3 = 64000; | 122 | DTCR3 = 64000; |
115 | DMAOR = 0x0001; /* Enable DMA */ | 123 | DMAOR = 0x0001; /* Enable DMA */ |
116 | } | 124 | } |
117 | 125 | ||
118 | void start_dma(void) | 126 | void start_dma(void) |
119 | { | 127 | { |
120 | CHCR3 |= 1; | 128 | SCR0 |= 0x80; |
129 | dma_on = TRUE; | ||
121 | } | 130 | } |
122 | 131 | ||
123 | void stop_dma(void) | 132 | void stop_dma(void) |
124 | { | 133 | { |
125 | CHCR3 &= ~1; | 134 | SCR0 &= 0x7f; |
135 | dma_on = FALSE; | ||
126 | } | 136 | } |
127 | 137 | ||
138 | void dma_tick(void) | ||
139 | { | ||
140 | if(!dma_on) | ||
141 | { | ||
142 | if(PBDR & 0x4000) | ||
143 | { | ||
144 | if(!(SCR0 & 0x80)) | ||
145 | start_dma(); | ||
146 | } | ||
147 | } | ||
148 | } | ||
128 | 149 | ||
129 | int main(void) | 150 | int main(void) |
130 | { | 151 | { |
131 | char buf[40]; | 152 | char buf[40]; |
132 | char str[32]; | 153 | char str[32]; |
133 | int i=0; | 154 | int i=0; |
134 | int dma_on = 0; | ||
135 | 155 | ||
136 | /* Clear it all! */ | 156 | /* Clear it all! */ |
137 | SSR1 &= ~(SCI_RDRF | SCI_ORER | SCI_PER | SCI_FER); | 157 | SSR1 &= ~(SCI_RDRF | SCI_ORER | SCI_PER | SCI_FER); |
138 | 158 | ||
139 | /* This enables the serial Rx interrupt, to be able to exit into the | 159 | /* This enables the serial Rx interrupt, to be able to exit into the |
140 | debugger when you hit CTRL-C */ | 160 | debugger when you hit CTRL-C */ |
141 | SCR1 |= 0x40; | 161 | SCR1 |= 0x40; |
142 | SCR1 &= ~0x80; | 162 | SCR1 &= ~0x80; |
143 | asm ("ldc\t%0,sr" : : "r"(0<<4)); | ||
144 | 163 | ||
145 | debugf("Olle: %d\n", 7); | 164 | i2c_init(); |
165 | |||
166 | dma_on = TRUE; | ||
146 | 167 | ||
147 | i2c_init(); | 168 | kernel_init(); |
148 | debugf("I2C Init done\n"); | 169 | tick_add_task(dma_tick); |
149 | i=mas_readmem(MAS_BANK_D1,0xff6,(unsigned long*)buf,2); | 170 | |
150 | if (i) { | 171 | set_irq_level(0); |
151 | debugf("Error - mas_readmem() returned %d\n", i); | 172 | |
152 | while(1); | 173 | setup_sci0(); |
153 | } | 174 | |
154 | 175 | i=mas_readmem(MAS_BANK_D1,0xff6,(unsigned long*)buf,2); | |
155 | i = buf[0] | buf[1] << 8; | 176 | if (i) { |
156 | debugf("MAS version: %x\n", i); | 177 | debugf("Error - mas_readmem() returned %d\n", i); |
157 | i = buf[4] | buf[5] << 8; | 178 | while(1); |
158 | debugf("MAS revision: %x\n", i); | 179 | } |
159 | 180 | ||
160 | i=mas_readmem(MAS_BANK_D1,0xff9,(unsigned long*)buf,7); | 181 | i = buf[0] | buf[1] << 8; |
161 | if (i) { | 182 | debugf("MAS version: %x\n", i); |
162 | debugf("Error - mas_readmem() returned %d\n", i); | 183 | i = buf[4] | buf[5] << 8; |
163 | while(1); | 184 | debugf("MAS revision: %x\n", i); |
164 | } | 185 | |
165 | 186 | i=mas_readmem(MAS_BANK_D1,0xff9,(unsigned long*)buf,7); | |
166 | for(i = 0;i < 7;i++) | 187 | if (i) { |
167 | { | 188 | debugf("Error - mas_readmem() returned %d\n", i); |
168 | str[i*2+1] = buf[i*4]; | 189 | while(1); |
169 | str[i*2] = buf[i*4+1]; | 190 | } |
170 | } | 191 | |
171 | str[i*2] = 0; | 192 | for(i = 0;i < 7;i++) |
172 | debugf("Description: %s\n", str); | 193 | { |
173 | 194 | str[i*2+1] = buf[i*4]; | |
174 | i=mas_readreg(0xe6); | 195 | str[i*2] = buf[i*4+1]; |
175 | if (i < 0) { | 196 | } |
176 | debugf("Error - mas_readreg() returned %d\n", i); | 197 | str[i*2] = 0; |
177 | while(1); | 198 | debugf("Description: %s\n", str); |
178 | } | 199 | |
179 | 200 | i=mas_writereg(0x3b, 0x20); | |
180 | debugf("Register 0xe6: %x\n", i); | 201 | if (i < 0) { |
181 | 202 | debugf("Error - mas_writereg() returned %d\n", i); | |
203 | while(1); | ||
204 | } | ||
205 | |||
206 | i = mas_run(1); | ||
207 | if (i < 0) { | ||
208 | debugf("Error - mas_run() returned %d\n", i); | ||
209 | while(1); | ||
210 | } | ||
182 | 211 | ||
183 | debugf("Writing register 0xaa\n"); | ||
184 | |||
185 | i=mas_writereg(0xaa, 0x1); | ||
186 | if (i < 0) { | ||
187 | debugf("Error - mas_writereg() returned %d\n", i); | ||
188 | while(1); | ||
189 | } | ||
190 | |||
191 | i=mas_readreg(0xaa); | ||
192 | if (i < 0) { | ||
193 | debugf("Error - mas_readreg() returned %d\n", i); | ||
194 | while(1); | ||
195 | } | ||
196 | |||
197 | debugf("Register 0xaa: %x\n", i); | ||
198 | 212 | ||
199 | debugf("Writing register 0xaa again\n"); | 213 | for(i = 0;i < mp3datalen;i++) |
200 | 214 | { | |
201 | i=mas_writereg(0xaa, 0); | 215 | mp3data[i] = fliptable[mp3data[i]]; |
202 | if (i < 0) { | 216 | } |
203 | debugf("Error - mas_writereg() returned %d\n", i); | 217 | |
204 | while(1); | 218 | while(1) |
205 | } | 219 | { |
206 | 220 | debugf("let's play...\n"); | |
207 | i=mas_readreg(0xaa); | 221 | init_dma(); |
208 | if (i < 0) { | 222 | |
209 | debugf("Error - mas_readreg() returned %d\n", i); | 223 | mp3dataptr = mp3data; |
210 | while(1); | 224 | mp3_transmitted = 0; |
211 | } | 225 | |
212 | 226 | dma_on = TRUE; | |
213 | debugf("Register 0xaa: %x\n", i); | 227 | |
214 | 228 | /* Enable Tx (only!) */ | |
215 | i=mas_readreg(0xed); | 229 | SCR0 |= 0xa0; |
216 | if (i < 0) { | 230 | |
217 | debugf("Error - mas_readreg(ed) returned %d\n", i); | 231 | CHCR3 |= 1; |
218 | while(1); | 232 | |
219 | } | 233 | debugf("sleeping...\n"); |
220 | 234 | sleep(10000); | |
221 | debugf("Register 0xed: %x\n", i); | 235 | } |
222 | 236 | } | |
223 | i=mas_writereg(0x3b, 0x20); | ||
224 | if (i < 0) { | ||
225 | debugf("Error - mas_writereg() returned %d\n", i); | ||
226 | while(1); | ||
227 | } | ||
228 | |||
229 | i = mas_run(1); | ||
230 | if (i < 0) { | ||
231 | debugf("Error - mas_run() returned %d\n", i); | ||
232 | while(1); | ||
233 | } | ||
234 | 237 | ||
235 | 238 | #pragma interrupt | |
236 | setup_sci0(); | 239 | void IRQ6(void) |
237 | 240 | { | |
238 | i = 0; | 241 | stop_dma(); |
239 | 242 | } | |
240 | init_dma(); | 243 | |
241 | 244 | #pragma interrupt | |
242 | while(1) | 245 | void DEI3(void) |
243 | { | 246 | { |
244 | /* Demand pin high? */ | 247 | mp3_transmitted += 64000; |
245 | if(PBDR & 0x4000) | 248 | if(mp3_transmitted < mp3datalen) |
246 | { | 249 | { |
247 | start_dma(); | 250 | DTCR3 = 64000; |
248 | #if 0 | 251 | CHCR3 &= ~0x0002; |
249 | /* More data to write? */ | 252 | } |
250 | if(i < mp3datalen) | 253 | else |
251 | { | 254 | { |
252 | /* Transmitter ready? */ | 255 | CHCR3 = 0; |
253 | while(!mas_tx_ready()){}; | 256 | } |
254 | |||
255 | /* Write data into TDR and clear TDRE */ | ||
256 | TDR0 = fliptable[mp3data[i++]]; | ||
257 | SSR0 &= ~SCI_TDRE; | ||
258 | } | ||
259 | #endif | ||
260 | } | ||
261 | else | ||
262 | { | ||
263 | stop_dma(); | ||
264 | } | ||
265 | } | ||
266 | |||
267 | while(1); | ||
268 | } | 257 | } |