diff options
Diffstat (limited to 'firmware/target')
21 files changed, 174 insertions, 166 deletions
diff --git a/firmware/target/arm/imx31/debug-imx31.c b/firmware/target/arm/imx31/debug-imx31.c index ad436ea231..abf180cfd2 100644 --- a/firmware/target/arm/imx31/debug-imx31.c +++ b/firmware/target/arm/imx31/debug-imx31.c | |||
@@ -50,15 +50,15 @@ bool __dbg_hw_info(void) | |||
50 | iim_system_rev()); | 50 | iim_system_rev()); |
51 | lcd_puts(0, line++, buf); line++; | 51 | lcd_puts(0, line++, buf); line++; |
52 | 52 | ||
53 | mpctl = CLKCTL_MPCTL; | 53 | mpctl = CCM_MPCTL; |
54 | spctl = CLKCTL_SPCTL; | 54 | spctl = CCM_SPCTL; |
55 | upctl = CLKCTL_UPCTL; | 55 | upctl = CCM_UPCTL; |
56 | 56 | ||
57 | pllref = imx31_clkctl_get_pll_ref_clk(); | 57 | pllref = ccm_get_pll_ref_clk(); |
58 | 58 | ||
59 | mcu_pllfreq = imx31_clkctl_get_pll(PLL_MCU); | 59 | mcu_pllfreq = ccm_get_pll(PLL_MCU); |
60 | ser_pllfreq = imx31_clkctl_get_pll(PLL_SERIAL); | 60 | ser_pllfreq = ccm_get_pll(PLL_SERIAL); |
61 | usb_pllfreq = imx31_clkctl_get_pll(PLL_USB); | 61 | usb_pllfreq = ccm_get_pll(PLL_USB); |
62 | 62 | ||
63 | snprintf(buf, sizeof (buf), "pll_ref_clk: %u", pllref); | 63 | snprintf(buf, sizeof (buf), "pll_ref_clk: %u", pllref); |
64 | lcd_puts(0, line++, buf); line++; | 64 | lcd_puts(0, line++, buf); line++; |
@@ -70,7 +70,7 @@ bool __dbg_hw_info(void) | |||
70 | snprintf(buf, sizeof (buf), " mpl_dpdgck_clk: %u", mcu_pllfreq); | 70 | snprintf(buf, sizeof (buf), " mpl_dpdgck_clk: %u", mcu_pllfreq); |
71 | lcd_puts(0, line++, buf); line++; | 71 | lcd_puts(0, line++, buf); line++; |
72 | 72 | ||
73 | regval = CLKCTL_PDR0; | 73 | regval = CCM_PDR0; |
74 | snprintf(buf, sizeof (buf), " PDR0: %08lX", regval); | 74 | snprintf(buf, sizeof (buf), " PDR0: %08lX", regval); |
75 | lcd_puts(0, line++, buf); | 75 | lcd_puts(0, line++, buf); |
76 | 76 | ||
@@ -111,7 +111,7 @@ bool __dbg_hw_info(void) | |||
111 | snprintf(buf, sizeof (buf), " upl_dpdgck_clk: %u", usb_pllfreq); | 111 | snprintf(buf, sizeof (buf), " upl_dpdgck_clk: %u", usb_pllfreq); |
112 | lcd_puts(0, line++, buf); line++; | 112 | lcd_puts(0, line++, buf); line++; |
113 | 113 | ||
114 | regval = CLKCTL_PDR1; | 114 | regval = CCM_PDR1; |
115 | snprintf(buf, sizeof (buf), " PDR1: %08lX", regval); | 115 | snprintf(buf, sizeof (buf), " PDR1: %08lX", regval); |
116 | lcd_puts(0, line++, buf); | 116 | lcd_puts(0, line++, buf); |
117 | 117 | ||
@@ -120,7 +120,7 @@ bool __dbg_hw_info(void) | |||
120 | snprintf(buf, sizeof (buf), " usb_clk: %u", freq); | 120 | snprintf(buf, sizeof (buf), " usb_clk: %u", freq); |
121 | lcd_puts(0, line++, buf); | 121 | lcd_puts(0, line++, buf); |
122 | 122 | ||
123 | freq = usb_pllfreq / (((CLKCTL_PDR0 >> 16) & 0x1f) + 1); | 123 | freq = usb_pllfreq / (((CCM_PDR0 >> 16) & 0x1f) + 1); |
124 | snprintf(buf, sizeof (buf), " ipg_per_baud: %u", freq); | 124 | snprintf(buf, sizeof (buf), " ipg_per_baud: %u", freq); |
125 | lcd_puts(0, line++, buf); | 125 | lcd_puts(0, line++, buf); |
126 | 126 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c b/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c index 3c66c42adc..52293228f8 100644 --- a/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c | |||
@@ -57,8 +57,8 @@ unsigned short adc_read(int channel) | |||
57 | { | 57 | { |
58 | /* Keep enable, start conversion, increment from channel 0, | 58 | /* Keep enable, start conversion, increment from channel 0, |
59 | * increment from channel 4 */ | 59 | * increment from channel 4 */ |
60 | uint32_t adc1 = MC13783_ADEN | MC13783_ASC | MC13783_ADA1w(0) | | 60 | uint32_t adc1 = MC13783_ADEN | MC13783_ASC | |
61 | MC13783_ADA2w(4); | 61 | (0 << MC13783_ADA1_POS) | (4 << MC13783_ADA2_POS); |
62 | 62 | ||
63 | if (input_select == 1) | 63 | if (input_select == 1) |
64 | adc1 |= MC13783_ADSEL; /* 2nd set of inputs */ | 64 | adc1 |= MC13783_ADSEL; /* 2nd set of inputs */ |
@@ -81,7 +81,9 @@ unsigned short adc_read(int channel) | |||
81 | mutex_unlock(&adc_mtx); | 81 | mutex_unlock(&adc_mtx); |
82 | 82 | ||
83 | /* Channels 0-3/8-11 in ADD1, 4-7/12-15 in ADD2 */ | 83 | /* Channels 0-3/8-11 in ADD1, 4-7/12-15 in ADD2 */ |
84 | return (channel & 4) ? MC13783_ADD2r(data) : MC13783_ADD1r(data); | 84 | return (channel & 4) ? |
85 | ((data & MC13783_ADD2) >> MC13783_ADD2_POS) : | ||
86 | ((data & MC13783_ADD1) >> MC13783_ADD1_POS); | ||
85 | } | 87 | } |
86 | 88 | ||
87 | bool adc_enable_channel(int channel, bool enable) | 89 | bool adc_enable_channel(int channel, bool enable) |
diff --git a/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c b/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c index c32dead30a..c941037317 100644 --- a/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c | |||
@@ -275,7 +275,7 @@ static unsigned long ata_dma_selected = ATA_DMA_PIO; | |||
275 | static unsigned int get_T(void) | 275 | static unsigned int get_T(void) |
276 | { | 276 | { |
277 | /* T = ATA clock period in nanoseconds */ | 277 | /* T = ATA clock period in nanoseconds */ |
278 | return 1000 * 1000 * 1000 / imx31_clkctl_get_ata_clk(); | 278 | return 1000 * 1000 * 1000 / ccm_get_ata_clk(); |
279 | } | 279 | } |
280 | 280 | ||
281 | static void ata_wait_for_idle(void) | 281 | static void ata_wait_for_idle(void) |
@@ -325,7 +325,7 @@ void ata_reset(void) | |||
325 | void ata_enable(bool on) | 325 | void ata_enable(bool on) |
326 | { | 326 | { |
327 | /* Unconditionally clock module before writing regs */ | 327 | /* Unconditionally clock module before writing regs */ |
328 | imx31_clkctl_module_clock_gating(CG_ATA, CGM_ON_ALL); | 328 | ccm_module_clock_gating(CG_ATA, CGM_ON_RUN_WAIT); |
329 | ata_wait_for_idle(); | 329 | ata_wait_for_idle(); |
330 | 330 | ||
331 | if (on) | 331 | if (on) |
@@ -339,7 +339,7 @@ void ata_enable(bool on) | |||
339 | sleep(HZ/100); | 339 | sleep(HZ/100); |
340 | 340 | ||
341 | /* Disable off - unclock ATA module */ | 341 | /* Disable off - unclock ATA module */ |
342 | imx31_clkctl_module_clock_gating(CG_ATA, CGM_OFF); | 342 | ccm_module_clock_gating(CG_ATA, CGM_OFF); |
343 | } | 343 | } |
344 | } | 344 | } |
345 | 345 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c index a135889e6e..4ba7da4be0 100644 --- a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c | |||
@@ -59,7 +59,7 @@ void UIE_VECTOR(void) | |||
59 | ); | 59 | ); |
60 | 60 | ||
61 | offset = mode == 0x11 ? | 61 | offset = mode == 0x11 ? |
62 | (int32_t)FIVECSR : ((int32_t)NIVECSR >> 16); | 62 | (int32_t)AVIC_FIVECSR : ((int32_t)AVIC_NIVECSR >> 16); |
63 | 63 | ||
64 | panicf("Unhandled %s %d: %s", | 64 | panicf("Unhandled %s %d: %s", |
65 | mode == 0x11 ? "FIQ" : "IRQ", offset, | 65 | mode == 0x11 ? "FIQ" : "IRQ", offset, |
@@ -69,7 +69,7 @@ void UIE_VECTOR(void) | |||
69 | /* We use the AVIC */ | 69 | /* We use the AVIC */ |
70 | void __attribute__((interrupt("IRQ"))) irq_handler(void) | 70 | void __attribute__((interrupt("IRQ"))) irq_handler(void) |
71 | { | 71 | { |
72 | const int offset = (int32_t)NIVECSR >> 16; | 72 | const int offset = (int32_t)AVIC_NIVECSR >> 16; |
73 | 73 | ||
74 | if (offset == -1) | 74 | if (offset == -1) |
75 | { | 75 | { |
@@ -105,20 +105,20 @@ void avic_init(void) | |||
105 | int i; | 105 | int i; |
106 | 106 | ||
107 | /* Disable all interrupts and set to unhandled */ | 107 | /* Disable all interrupts and set to unhandled */ |
108 | avic_disable_int(ALL); | 108 | avic_disable_int(INT_ALL); |
109 | 109 | ||
110 | /* Reset AVIC control */ | 110 | /* Reset AVIC control */ |
111 | avic->intcntl = 0; | 111 | avic->intcntl = 0; |
112 | 112 | ||
113 | /* Init all interrupts to type IRQ */ | 113 | /* Init all interrupts to type IRQ */ |
114 | avic_set_int_type(ALL, IRQ); | 114 | avic_set_int_type(INT_ALL, INT_TYPE_IRQ); |
115 | 115 | ||
116 | /* Set all normal to lowest priority */ | 116 | /* Set all normal to lowest priority */ |
117 | for (i = 0; i < 8; i++) | 117 | for (i = 0; i < 8; i++) |
118 | avic->nipriority[i] = 0; | 118 | avic->nipriority[i] = 0; |
119 | 119 | ||
120 | /* Set NM bit to enable VIC */ | 120 | /* Set NM bit to enable VIC */ |
121 | avic->intcntl |= INTCNTL_NM; | 121 | avic->intcntl |= AVIC_INTCNTL_NM; |
122 | 122 | ||
123 | /* Enable VE bit in CP15 Control reg to enable VIC */ | 123 | /* Enable VE bit in CP15 Control reg to enable VIC */ |
124 | asm volatile ( | 124 | asm volatile ( |
@@ -147,7 +147,7 @@ void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype, | |||
147 | struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR; | 147 | struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR; |
148 | int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); | 148 | int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); |
149 | 149 | ||
150 | if (ints != ALL) /* No mass-enable allowed */ | 150 | if (ints != INT_ALL) /* No mass-enable allowed */ |
151 | { | 151 | { |
152 | avic_set_int_type(ints, intstype); | 152 | avic_set_int_type(ints, intstype); |
153 | avic->vector[ints] = (long)handler; | 153 | avic->vector[ints] = (long)handler; |
@@ -163,7 +163,7 @@ void avic_disable_int(enum IMX31_INT_LIST ints) | |||
163 | struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR; | 163 | struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR; |
164 | uint32_t i; | 164 | uint32_t i; |
165 | 165 | ||
166 | if (ints == ALL) | 166 | if (ints == INT_ALL) |
167 | { | 167 | { |
168 | for (i = 0; i < 64; i++) | 168 | for (i = 0; i < 64; i++) |
169 | { | 169 | { |
@@ -185,7 +185,7 @@ static void set_int_type(int i, enum INT_TYPE intstype) | |||
185 | volatile uint32_t *reg = &avic->inttype[1 - (i >> 5)]; | 185 | volatile uint32_t *reg = &avic->inttype[1 - (i >> 5)]; |
186 | uint32_t val = 1L << (i & 0x1f); | 186 | uint32_t val = 1L << (i & 0x1f); |
187 | 187 | ||
188 | if (intstype == IRQ) | 188 | if (intstype == INT_TYPE_IRQ) |
189 | val = *reg & ~val; | 189 | val = *reg & ~val; |
190 | else | 190 | else |
191 | val = *reg | val; | 191 | val = *reg | val; |
@@ -197,7 +197,7 @@ void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype) | |||
197 | { | 197 | { |
198 | int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); | 198 | int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); |
199 | 199 | ||
200 | if (ints == ALL) | 200 | if (ints == INT_ALL) |
201 | { | 201 | { |
202 | int i; | 202 | int i; |
203 | for (i = 0; i < 64; i++) | 203 | for (i = 0; i < 64; i++) |
diff --git a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h index 3580c8c083..a049713600 100644 --- a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h +++ b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h | |||
@@ -172,32 +172,34 @@ struct avic_map | |||
172 | }; | 172 | }; |
173 | }; | 173 | }; |
174 | 174 | ||
175 | #define INT_PRIO_DEFAULT 7 | ||
176 | |||
175 | enum INT_TYPE | 177 | enum INT_TYPE |
176 | { | 178 | { |
177 | IRQ = 0, | 179 | INT_TYPE_IRQ = 0, |
178 | FIQ | 180 | INT_TYPE_FIQ |
179 | }; | 181 | }; |
180 | 182 | ||
181 | enum IMX31_INT_LIST | 183 | enum IMX31_INT_LIST |
182 | { | 184 | { |
183 | __IMX31_INT_FIRST = -1, | 185 | __IMX31_INT_FIRST = -1, |
184 | RESERVED0, RESERVED1, RESERVED2, I2C3, | 186 | INT_RESERVED0, INT_RESERVED1, INT_RESERVED2, INT_I2C3, |
185 | I2C2, MPEG4_ENCODER, RTIC, FIR, | 187 | INT_I2C2, INT_MPEG4_ENCODER, INT_RTIC, INT_FIR, |
186 | MMC_SDHC2, MMC_SDHC1, I2C1, SSI2, | 188 | INT_MMC_SDHC2, INT_MMC_SDHC1, INT_I2C1, INT_SSI2, |
187 | SSI1, CSPI2, CSPI1, ATA, | 189 | INT_SSI1, INT_CSPI2, INT_CSPI1, INT_ATA, |
188 | MBX, CSPI3, UART3, IIM, | 190 | INT_MBX, INT_CSPI3, INT_UART3, INT_IIM, |
189 | SIM1, SIM2, RNGA, EVTMON, | 191 | INT_SIM1, INT_SIM2, INT_RNGA, INT_EVTMON, |
190 | KPP, RTC, PWN, EPIT2, | 192 | INT_KPP, INT_RTC, INT_PWN, INT_EPIT2, |
191 | EPIT1, GPT, PWR_FAIL, CCM_DVFS, | 193 | INT_EPIT1, INT_GPT, INT_PWR_FAIL, INT_CCM_DVFS, |
192 | UART2, NANDFC, SDMA, USB_HOST1, | 194 | INT_UART2, INT_NANDFC, INT_SDMA, INT_USB_HOST1, |
193 | USB_HOST2, USB_OTG, RESERVED3, MSHC1, | 195 | INT_USB_HOST2, INT_USB_OTG, INT_RESERVED3, INT_MSHC1, |
194 | MSHC2, IPU_ERR, IPU, RESERVED4, | 196 | INT_MSHC2, INT_IPU_ERR, INT_IPU, INT_RESERVED4, |
195 | RESERVED5, UART1, UART4, UART5, | 197 | INT_RESERVED5, INT_UART1, INT_UART4, INT_UART5, |
196 | ETC_IRQ, SCC_SCM, SCC_SMN, GPIO2, | 198 | INT_ETC_IRQ, INT_SCC_SCM, INT_SCC_SMN, INT_GPIO2, |
197 | GPIO1, CCM_CLK, PCMCIA, WDOG, | 199 | INT_GPIO1, INT_CCM_CLK, INT_PCMCIA, INT_WDOG, |
198 | GPIO3, RESERVED6, EXT_PWMG, EXT_TEMP, | 200 | INT_GPIO3, INT_RESERVED6, INT_EXT_PWMG, INT_EXT_TEMP, |
199 | EXT_SENS1, EXT_SENS2, EXT_WDOG, EXT_TV, | 201 | INT_EXT_SENS1, INT_EXT_SENS2, INT_EXT_WDOG, INT_EXT_TV, |
200 | ALL | 202 | INT_ALL |
201 | }; | 203 | }; |
202 | 204 | ||
203 | void avic_init(void); | 205 | void avic_init(void); |
diff --git a/firmware/target/arm/imx31/gigabeat-s/backlight-imx31.c b/firmware/target/arm/imx31/gigabeat-s/backlight-imx31.c index 8f75b72f58..8457d06a77 100644 --- a/firmware/target/arm/imx31/gigabeat-s/backlight-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/backlight-imx31.c | |||
@@ -176,7 +176,8 @@ void _backlight_off(void) | |||
176 | sleep(HZ/100); | 176 | sleep(HZ/100); |
177 | 177 | ||
178 | /* Write final PWM setting */ | 178 | /* Write final PWM setting */ |
179 | mc13783_write_masked(MC13783_LED_CONTROL2, MC13783_LEDMDDCw(0), | 179 | mc13783_write_masked(MC13783_LED_CONTROL2, |
180 | 0 << MC13783_LEDMDDC_POS, | ||
180 | MC13783_LEDMDDC); | 181 | MC13783_LEDMDDC); |
181 | 182 | ||
182 | #ifdef HAVE_LCD_SLEEP | 183 | #ifdef HAVE_LCD_SLEEP |
@@ -198,10 +199,10 @@ void _backlight_set_brightness(int brightness) | |||
198 | 199 | ||
199 | md = led_md_pwm_table[brightness].md; | 200 | md = led_md_pwm_table[brightness].md; |
200 | backlight_pwm_bits = backlight_on_status ? | 201 | backlight_pwm_bits = backlight_on_status ? |
201 | MC13783_LEDMDDCw(led_md_pwm_table[brightness].pwm) : 0; | 202 | (led_md_pwm_table[brightness].pwm << MC13783_LEDMDDC_POS) : 0; |
202 | 203 | ||
203 | mc13783_write_masked(MC13783_LED_CONTROL2, | 204 | mc13783_write_masked(MC13783_LED_CONTROL2, |
204 | MC13783_LEDMDw(md) | backlight_pwm_bits, | 205 | (md << MC13783_LEDMD_POS) | backlight_pwm_bits, |
205 | MC13783_LEDMD | MC13783_LEDMDDC); | 206 | MC13783_LEDMD | MC13783_LEDMDDC); |
206 | 207 | ||
207 | mutex_unlock(&backlight_mutex); | 208 | mutex_unlock(&backlight_mutex); |
diff --git a/firmware/target/arm/imx31/gigabeat-s/button-imx31.c b/firmware/target/arm/imx31/gigabeat-s/button-imx31.c index d2a46f2c9f..505ba397d9 100644 --- a/firmware/target/arm/imx31/gigabeat-s/button-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/button-imx31.c | |||
@@ -197,7 +197,7 @@ void button_init_device(void) | |||
197 | #endif | 197 | #endif |
198 | 198 | ||
199 | /* Enable keypad clock */ | 199 | /* Enable keypad clock */ |
200 | imx31_clkctl_module_clock_gating(CG_KPP, CGM_ON_ALL); | 200 | ccm_module_clock_gating(CG_KPP, CGM_ON_RUN_WAIT); |
201 | 201 | ||
202 | /* 1. Enable number of rows in keypad (KPCR[4:0]) | 202 | /* 1. Enable number of rows in keypad (KPCR[4:0]) |
203 | * | 203 | * |
@@ -219,8 +219,7 @@ void button_init_device(void) | |||
219 | * 6. Set the KDIE control bit bit. */ | 219 | * 6. Set the KDIE control bit bit. */ |
220 | KPP_KPSR = KPP_KPSR_KDIE | KPP_KPSR_KRSS | KPP_KPSR_KDSC | KPP_KPSR_KPKD; | 220 | KPP_KPSR = KPP_KPSR_KDIE | KPP_KPSR_KRSS | KPP_KPSR_KDSC | KPP_KPSR_KPKD; |
221 | 221 | ||
222 | /* KPP IRQ at priority 3 */ | 222 | avic_enable_int(INT_KPP, INT_TYPE_IRQ, INT_PRIO_DEFAULT, KPP_HANDLER); |
223 | avic_enable_int(KPP, IRQ, 3, KPP_HANDLER); | ||
224 | 223 | ||
225 | button_power_event(); | 224 | button_power_event(); |
226 | mc13783_enable_event(MC13783_ONOFD1_EVENT); | 225 | mc13783_enable_event(MC13783_ONOFD1_EVENT); |
@@ -235,7 +234,7 @@ void button_close_device(void) | |||
235 | { | 234 | { |
236 | int oldlevel = disable_irq_save(); | 235 | int oldlevel = disable_irq_save(); |
237 | 236 | ||
238 | avic_disable_int(KPP); | 237 | avic_disable_int(INT_KPP); |
239 | KPP_KPSR &= ~(KPP_KPSR_KRIE | KPP_KPSR_KDIE); | 238 | KPP_KPSR &= ~(KPP_KPSR_KRIE | KPP_KPSR_KDIE); |
240 | int_btn = BUTTON_NONE; | 239 | int_btn = BUTTON_NONE; |
241 | 240 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c index df592deecb..761cf8f701 100644 --- a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c | |||
@@ -24,47 +24,41 @@ | |||
24 | #include "cpu.h" | 24 | #include "cpu.h" |
25 | #include "clkctl-imx31.h" | 25 | #include "clkctl-imx31.h" |
26 | 26 | ||
27 | unsigned int imx31_get_src_pll(void) | 27 | unsigned int ccm_get_src_pll(void) |
28 | { | 28 | { |
29 | return (CLKCTL_PMCR0 & 0xC0000000) == 0 ? PLL_SERIAL : PLL_MCU; | 29 | return (CCM_PMCR0 & 0xC0000000) == 0 ? PLL_SERIAL : PLL_MCU; |
30 | } | 30 | } |
31 | 31 | ||
32 | void imx31_clkctl_module_clock_gating(enum IMX31_CG_LIST cg, | 32 | void ccm_module_clock_gating(enum IMX31_CG_LIST cg, enum IMX31_CG_MODES mode) |
33 | enum IMX31_CG_MODES mode) | ||
34 | { | 33 | { |
35 | volatile unsigned long *reg; | 34 | volatile unsigned long *reg; |
36 | unsigned long mask; | 35 | unsigned long mask; |
37 | int shift; | 36 | int shift; |
38 | int oldlevel; | ||
39 | 37 | ||
40 | if (cg >= CG_NUM_CLOCKS) | 38 | if (cg >= CG_NUM_CLOCKS) |
41 | return; | 39 | return; |
42 | 40 | ||
43 | reg = &CLKCTL_CGR0 + cg / 16; /* Select CGR0, CGR1, CGR2 */ | 41 | reg = &CCM_CGR0 + cg / 16; /* Select CGR0, CGR1, CGR2 */ |
44 | shift = 2*(cg % 16); /* Get field shift */ | 42 | shift = 2*(cg % 16); /* Get field shift */ |
45 | mask = CG_MASK << shift; /* Select field */ | 43 | mask = CG_MASK << shift; /* Select field */ |
46 | 44 | ||
47 | oldlevel = disable_interrupt_save(IRQ_FIQ_STATUS); | 45 | imx31_regmod32(reg, mode << shift, mask); |
48 | |||
49 | *reg = (*reg & ~mask) | ((mode << shift) & mask); | ||
50 | |||
51 | restore_interrupt(oldlevel); | ||
52 | } | 46 | } |
53 | 47 | ||
54 | /* Get the PLL reference clock frequency in HZ */ | 48 | /* Get the PLL reference clock frequency in HZ */ |
55 | unsigned int imx31_clkctl_get_pll_ref_clk(void) | 49 | unsigned int ccm_get_pll_ref_clk(void) |
56 | { | 50 | { |
57 | if ((CLKCTL_CCMR & (3 << 1)) == (1 << 1)) | 51 | if ((CCM_CCMR & (3 << 1)) == (1 << 1)) |
58 | return CONFIG_CLK32_FREQ * 1024; | 52 | return CONFIG_CLK32_FREQ * 1024; |
59 | else | 53 | else |
60 | return CONFIG_HCLK_FREQ; | 54 | return CONFIG_HCLK_FREQ; |
61 | } | 55 | } |
62 | 56 | ||
63 | /* Return PLL frequency in HZ */ | 57 | /* Return PLL frequency in HZ */ |
64 | unsigned int imx31_clkctl_get_pll(enum IMX31_PLLS pll) | 58 | unsigned int ccm_get_pll(enum IMX31_PLLS pll) |
65 | { | 59 | { |
66 | uint32_t infreq = imx31_clkctl_get_pll_ref_clk(); | 60 | uint32_t infreq = ccm_get_pll_ref_clk(); |
67 | uint32_t reg = (&CLKCTL_MPCTL)[pll]; | 61 | uint32_t reg = (&CCM_MPCTL)[pll]; |
68 | uint32_t mfn = reg & 0x3ff; | 62 | uint32_t mfn = reg & 0x3ff; |
69 | uint32_t pd = ((reg >> 26) & 0xf) + 1; | 63 | uint32_t pd = ((reg >> 26) & 0xf) + 1; |
70 | uint64_t mfd = ((reg >> 16) & 0x3ff) + 1; | 64 | uint64_t mfd = ((reg >> 16) & 0x3ff) + 1; |
@@ -75,27 +69,27 @@ unsigned int imx31_clkctl_get_pll(enum IMX31_PLLS pll) | |||
75 | return 2*infreq*(mfi * mfd + mfn) / (mfd * pd); | 69 | return 2*infreq*(mfi * mfd + mfn) / (mfd * pd); |
76 | } | 70 | } |
77 | 71 | ||
78 | unsigned int imx31_clkctl_get_ipg_clk(void) | 72 | unsigned int ccm_get_ipg_clk(void) |
79 | { | 73 | { |
80 | unsigned int pllnum = imx31_get_src_pll(); | 74 | unsigned int pllnum = ccm_get_src_pll(); |
81 | unsigned int pll = imx31_clkctl_get_pll(pllnum); | 75 | unsigned int pll = ccm_get_pll(pllnum); |
82 | uint32_t reg = CLKCTL_PDR0; | 76 | uint32_t reg = CCM_PDR0; |
83 | unsigned int max_pdf = ((reg >> 3) & 0x7) + 1; | 77 | unsigned int max_pdf = ((reg >> 3) & 0x7) + 1; |
84 | unsigned int ipg_pdf = ((reg >> 6) & 0x3) + 1; | 78 | unsigned int ipg_pdf = ((reg >> 6) & 0x3) + 1; |
85 | 79 | ||
86 | return pll / (max_pdf * ipg_pdf); | 80 | return pll / (max_pdf * ipg_pdf); |
87 | } | 81 | } |
88 | 82 | ||
89 | unsigned int imx31_clkctl_get_ahb_clk(void) | 83 | unsigned int ccm_get_ahb_clk(void) |
90 | { | 84 | { |
91 | unsigned int pllnum = imx31_get_src_pll(); | 85 | unsigned int pllnum = ccm_get_src_pll(); |
92 | unsigned int pll = imx31_clkctl_get_pll(pllnum); | 86 | unsigned int pll = ccm_get_pll(pllnum); |
93 | unsigned int max_pdf = ((CLKCTL_PDR0 >> 3) & 0x7) + 1; | 87 | unsigned int max_pdf = ((CCM_PDR0 >> 3) & 0x7) + 1; |
94 | 88 | ||
95 | return pll / max_pdf; | 89 | return pll / max_pdf; |
96 | } | 90 | } |
97 | 91 | ||
98 | unsigned int imx31_clkctl_get_ata_clk(void) | 92 | unsigned int ccm_get_ata_clk(void) |
99 | { | 93 | { |
100 | return imx31_clkctl_get_ipg_clk(); | 94 | return ccm_get_ipg_clk(); |
101 | } | 95 | } |
diff --git a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h index bd8f89a15b..e1057a9618 100644 --- a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h +++ b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h | |||
@@ -20,8 +20,8 @@ | |||
20 | * KIND, either express or implied. | 20 | * KIND, either express or implied. |
21 | * | 21 | * |
22 | ****************************************************************************/ | 22 | ****************************************************************************/ |
23 | #ifndef _CLKCTL_IMX31_H_ | 23 | #ifndef _CCM_IMX31_H_ |
24 | #define _CLKCTL_IMX31_H_ | 24 | #define _CCM_IMX31_H_ |
25 | 25 | ||
26 | enum IMX31_CG_LIST | 26 | enum IMX31_CG_LIST |
27 | { | 27 | { |
@@ -82,8 +82,8 @@ enum IMX31_CG_MODES | |||
82 | 82 | ||
83 | /* Enable or disable module clocks independently - module must _not_ be | 83 | /* Enable or disable module clocks independently - module must _not_ be |
84 | * active! */ | 84 | * active! */ |
85 | void imx31_clkctl_module_clock_gating(enum IMX31_CG_LIST cg, | 85 | void ccm_module_clock_gating(enum IMX31_CG_LIST cg, |
86 | enum IMX31_CG_MODES mode); | 86 | enum IMX31_CG_MODES mode); |
87 | 87 | ||
88 | enum IMX31_PLLS | 88 | enum IMX31_PLLS |
89 | { | 89 | { |
@@ -97,18 +97,18 @@ enum IMX31_PLLS | |||
97 | #define CONFIG_HCLK_FREQ 27000000 | 97 | #define CONFIG_HCLK_FREQ 27000000 |
98 | 98 | ||
99 | /* Get the PLL reference clock frequency in HZ */ | 99 | /* Get the PLL reference clock frequency in HZ */ |
100 | unsigned int imx31_clkctl_get_pll_ref_clk(void); | 100 | unsigned int ccm_get_pll_ref_clk(void); |
101 | 101 | ||
102 | /* Return PLL frequency in HZ */ | 102 | /* Return PLL frequency in HZ */ |
103 | unsigned int imx31_clkctl_get_pll(enum IMX31_PLLS pll); | 103 | unsigned int ccm_get_pll(enum IMX31_PLLS pll); |
104 | 104 | ||
105 | /* Return ipg_clk in HZ */ | 105 | /* Return ipg_clk in HZ */ |
106 | unsigned int imx31_clkctl_get_ipg_clk(void); | 106 | unsigned int ccm_get_ipg_clk(void); |
107 | 107 | ||
108 | /* Return ahb_clk in HZ */ | 108 | /* Return ahb_clk in HZ */ |
109 | unsigned int imx31_clkctl_get_ahb_clk(void); | 109 | unsigned int ccm_get_ahb_clk(void); |
110 | 110 | ||
111 | /* Return the ATA frequency in HZ */ | 111 | /* Return the ATA frequency in HZ */ |
112 | unsigned int imx31_clkctl_get_ata_clk(void); | 112 | unsigned int ccm_get_ata_clk(void); |
113 | 113 | ||
114 | #endif /* _CLKCTL_IMX31_H_ */ | 114 | #endif /* _CCM_IMX31_H_ */ |
diff --git a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c index 7646402435..d846f4d1d0 100644 --- a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c | |||
@@ -50,22 +50,18 @@ void fmradio_i2c_init(void) | |||
50 | * disabled */ | 50 | * disabled */ |
51 | imx31_regmod32(&SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1, | 51 | imx31_regmod32(&SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1, |
52 | /* RI_DTE1 (I2C2_SCLK) */ | 52 | /* RI_DTE1 (I2C2_SCLK) */ |
53 | SW_PAD_CTL_IO2w(SW_PAD_CTL_PUE_PKE_DISABLE | | 53 | ((SW_PAD_CTL_PUE_PKE_DISABLE | SW_PAD_CTL_PUS_UP_100K | |
54 | SW_PAD_CTL_PUS_UP_100K | | 54 | SW_PAD_CTL_HYS | SW_PAD_CTL_ODE) << SW_PAD_CTL_IO2_POS) | |
55 | SW_PAD_CTL_HYS | | ||
56 | SW_PAD_CTL_ODE) | | ||
57 | /* DCD_DTE1 (I2C2_SDA) */ | 55 | /* DCD_DTE1 (I2C2_SDA) */ |
58 | SW_PAD_CTL_IO1w(SW_PAD_CTL_PUE_PKE_DISABLE | | 56 | ((SW_PAD_CTL_PUE_PKE_DISABLE | SW_PAD_CTL_PUS_UP_100K | |
59 | SW_PAD_CTL_PUS_UP_100K | | 57 | SW_PAD_CTL_HYS | SW_PAD_CTL_ODE) << SW_PAD_CTL_IO1_POS), |
60 | SW_PAD_CTL_HYS | | ||
61 | SW_PAD_CTL_ODE), | ||
62 | SW_PAD_CTL_IO2 | SW_PAD_CTL_IO1); | 58 | SW_PAD_CTL_IO2 | SW_PAD_CTL_IO1); |
63 | /* set outputs to I2C2 */ | 59 | /* set outputs to I2C2 */ |
64 | imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, | 60 | imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, |
65 | /* RI_DTE1 => I2C2_SCLK */ | 61 | /* RI_DTE1 => I2C2_SCLK */ |
66 | SW_MUX_CTL_SIG4w(SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2) | | 62 | ((SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2) << SW_MUX_CTL_SIG4_POS) | |
67 | /* DCD_DTE1 => I2C2_SDA */ | 63 | /* DCD_DTE1 => I2C2_SDA */ |
68 | SW_MUX_CTL_SIG3w(SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2), | 64 | ((SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2) << SW_MUX_CTL_SIG3_POS), |
69 | SW_MUX_CTL_SIG4 | SW_MUX_CTL_SIG3); | 65 | SW_MUX_CTL_SIG4 | SW_MUX_CTL_SIG3); |
70 | } | 66 | } |
71 | 67 | ||
@@ -79,7 +75,8 @@ void fmradio_i2c_enable(bool enable) | |||
79 | imx31_regset32(&GPIO2_GDIR, (1 << 15)); /* SDIO OUT */ | 75 | imx31_regset32(&GPIO2_GDIR, (1 << 15)); /* SDIO OUT */ |
80 | /* I2C2_SDA => MCU2_15 */ | 76 | /* I2C2_SDA => MCU2_15 */ |
81 | imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, | 77 | imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, |
82 | SW_MUX_CTL_SIG3w(SW_MUX_OUT_GPIO_DR | SW_MUX_IN_GPIO_PSR_ISR), | 78 | (SW_MUX_OUT_GPIO_DR | |
79 | SW_MUX_IN_GPIO_PSR_ISR) << SW_MUX_CTL_SIG3_POS, | ||
83 | SW_MUX_CTL_SIG3); | 80 | SW_MUX_CTL_SIG3); |
84 | /* enable CLK32KMCU clock */ | 81 | /* enable CLK32KMCU clock */ |
85 | mc13783_set(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN); | 82 | mc13783_set(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN); |
diff --git a/firmware/target/arm/imx31/gigabeat-s/gpio-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/gpio-gigabeat-s.c index 446932b308..3d0ff977da 100644 --- a/firmware/target/arm/imx31/gigabeat-s/gpio-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/gpio-gigabeat-s.c | |||
@@ -22,6 +22,7 @@ | |||
22 | ****************************************************************************/ | 22 | ****************************************************************************/ |
23 | #include "config.h" | 23 | #include "config.h" |
24 | #include "system.h" | 24 | #include "system.h" |
25 | #include "avic-imx31.h" | ||
25 | #include "gpio-imx31.h" | 26 | #include "gpio-imx31.h" |
26 | 27 | ||
27 | /* Gigabeat S definitions for static GPIO event registration */ | 28 | /* Gigabeat S definitions for static GPIO event registration */ |
@@ -44,7 +45,7 @@ static const struct gpio_event gpio1_events[] = | |||
44 | /* Describes the events attached to GPIO1 port */ | 45 | /* Describes the events attached to GPIO1 port */ |
45 | const struct gpio_event_list gpio1_event_list = | 46 | const struct gpio_event_list gpio1_event_list = |
46 | { | 47 | { |
47 | .ints_priority = 7, | 48 | .ints_priority = INT_PRIO_DEFAULT, |
48 | .count = ARRAYLEN(gpio1_events), | 49 | .count = ARRAYLEN(gpio1_events), |
49 | .events = gpio1_events, | 50 | .events = gpio1_events, |
50 | }; | 51 | }; |
diff --git a/firmware/target/arm/imx31/gigabeat-s/gpio-imx31.c b/firmware/target/arm/imx31/gigabeat-s/gpio-imx31.c index 090182bed4..944f70eae3 100644 --- a/firmware/target/arm/imx31/gigabeat-s/gpio-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/gpio-imx31.c | |||
@@ -55,21 +55,21 @@ static struct gpio_module_descriptor | |||
55 | #if (GPIO_EVENT_MASK & USE_GPIO1_EVENTS) | 55 | #if (GPIO_EVENT_MASK & USE_GPIO1_EVENTS) |
56 | { | 56 | { |
57 | .base = (struct gpio_map *)GPIO1_BASE_ADDR, | 57 | .base = (struct gpio_map *)GPIO1_BASE_ADDR, |
58 | .ints = GPIO1, | 58 | .ints = INT_GPIO1, |
59 | .handler = GPIO1_HANDLER, | 59 | .handler = GPIO1_HANDLER, |
60 | }, | 60 | }, |
61 | #endif | 61 | #endif |
62 | #if (GPIO_EVENT_MASK & USE_GPIO2_EVENTS) | 62 | #if (GPIO_EVENT_MASK & USE_GPIO2_EVENTS) |
63 | { | 63 | { |
64 | .base = (struct gpio_map *)GPIO2_BASE_ADDR, | 64 | .base = (struct gpio_map *)GPIO2_BASE_ADDR, |
65 | .ints = GPIO2, | 65 | .ints = INT_GPIO2, |
66 | .handler = GPIO2_HANDLER, | 66 | .handler = GPIO2_HANDLER, |
67 | }, | 67 | }, |
68 | #endif | 68 | #endif |
69 | #if (GPIO_EVENT_MASK & USE_GPIO3_EVENTS) | 69 | #if (GPIO_EVENT_MASK & USE_GPIO3_EVENTS) |
70 | { | 70 | { |
71 | .base = (struct gpio_map *)GPIO3_BASE_ADDR, | 71 | .base = (struct gpio_map *)GPIO3_BASE_ADDR, |
72 | .ints = GPIO3, | 72 | .ints = INT_GPIO3, |
73 | .handler = GPIO3_HANDLER, | 73 | .handler = GPIO3_HANDLER, |
74 | }, | 74 | }, |
75 | #endif | 75 | #endif |
@@ -168,7 +168,7 @@ bool gpio_enable_event(enum gpio_event_ids id) | |||
168 | if (imr == 0) | 168 | if (imr == 0) |
169 | { | 169 | { |
170 | /* First enabled interrupt for this GPIO */ | 170 | /* First enabled interrupt for this GPIO */ |
171 | avic_enable_int(desc->ints, IRQ, desc->list->ints_priority, | 171 | avic_enable_int(desc->ints, INT_TYPE_IRQ, desc->list->ints_priority, |
172 | desc->handler); | 172 | desc->handler); |
173 | } | 173 | } |
174 | 174 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.c b/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.c index bf69afedb7..05d761c9ce 100644 --- a/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.c | |||
@@ -57,7 +57,7 @@ static struct i2c_module_descriptor | |||
57 | { | 57 | { |
58 | .base = (struct i2c_map *)I2C1_BASE_ADDR, | 58 | .base = (struct i2c_map *)I2C1_BASE_ADDR, |
59 | .cg = CG_I2C1, | 59 | .cg = CG_I2C1, |
60 | .ints = I2C1, | 60 | .ints = INT_I2C1, |
61 | .handler = I2C1_HANDLER, | 61 | .handler = I2C1_HANDLER, |
62 | }, | 62 | }, |
63 | #endif | 63 | #endif |
@@ -65,7 +65,7 @@ static struct i2c_module_descriptor | |||
65 | { | 65 | { |
66 | .base = (struct i2c_map *)I2C2_BASE_ADDR, | 66 | .base = (struct i2c_map *)I2C2_BASE_ADDR, |
67 | .cg = CG_I2C2, | 67 | .cg = CG_I2C2, |
68 | .ints = I2C2, | 68 | .ints = INT_I2C2, |
69 | .handler = I2C2_HANDLER, | 69 | .handler = I2C2_HANDLER, |
70 | }, | 70 | }, |
71 | #endif | 71 | #endif |
@@ -73,7 +73,7 @@ static struct i2c_module_descriptor | |||
73 | { | 73 | { |
74 | .base = (struct i2c_map *)I2C3_BASE_ADDR, | 74 | .base = (struct i2c_map *)I2C3_BASE_ADDR, |
75 | .cg = CG_I2C3, | 75 | .cg = CG_I2C3, |
76 | .ints = I2C3, | 76 | .ints = INT_I2C3, |
77 | .handler = I2C3_HANDLER, | 77 | .handler = I2C3_HANDLER, |
78 | }, | 78 | }, |
79 | #endif | 79 | #endif |
@@ -286,11 +286,11 @@ void i2c_init(void) | |||
286 | for (i = 0; i < I2C_NUM_I2C; i++) | 286 | for (i = 0; i < I2C_NUM_I2C; i++) |
287 | { | 287 | { |
288 | struct i2c_module_descriptor *const desc = &i2c_descs[i]; | 288 | struct i2c_module_descriptor *const desc = &i2c_descs[i]; |
289 | imx31_clkctl_module_clock_gating(desc->cg, CGM_ON_ALL); | 289 | ccm_module_clock_gating(desc->cg, CGM_ON_RUN_WAIT); |
290 | mutex_init(&desc->m); | 290 | mutex_init(&desc->m); |
291 | wakeup_init(&desc->w); | 291 | wakeup_init(&desc->w); |
292 | desc->base->i2cr = 0; | 292 | desc->base->i2cr = 0; |
293 | imx31_clkctl_module_clock_gating(desc->cg, CGM_OFF); | 293 | ccm_module_clock_gating(desc->cg, CGM_OFF); |
294 | } | 294 | } |
295 | } | 295 | } |
296 | 296 | ||
@@ -305,8 +305,9 @@ void i2c_enable_node(struct i2c_node *node, bool enable) | |||
305 | if (++desc->enable == 1) | 305 | if (++desc->enable == 1) |
306 | { | 306 | { |
307 | /* First enable */ | 307 | /* First enable */ |
308 | imx31_clkctl_module_clock_gating(desc->cg, CGM_ON_ALL); | 308 | ccm_module_clock_gating(desc->cg, CGM_ON_RUN_WAIT); |
309 | avic_enable_int(desc->ints, IRQ, 7, desc->handler); | 309 | avic_enable_int(desc->ints, INT_TYPE_IRQ, INT_PRIO_DEFAULT, |
310 | desc->handler); | ||
310 | } | 311 | } |
311 | } | 312 | } |
312 | else | 313 | else |
@@ -317,7 +318,7 @@ void i2c_enable_node(struct i2c_node *node, bool enable) | |||
317 | while (desc->base->i2sr & I2C_I2SR_IBB); /* Wait for STOP */ | 318 | while (desc->base->i2sr & I2C_I2SR_IBB); /* Wait for STOP */ |
318 | desc->base->i2cr &= ~I2C_I2CR_IEN; | 319 | desc->base->i2cr &= ~I2C_I2CR_IEN; |
319 | avic_disable_int(desc->ints); | 320 | avic_disable_int(desc->ints); |
320 | imx31_clkctl_module_clock_gating(desc->cg, CGM_OFF); | 321 | ccm_module_clock_gating(desc->cg, CGM_OFF); |
321 | } | 322 | } |
322 | } | 323 | } |
323 | 324 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c index a2f3d779eb..01e9b8b721 100644 --- a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c | |||
@@ -38,11 +38,11 @@ static __attribute__((interrupt("IRQ"))) void EPIT1_HANDLER(void) | |||
38 | 38 | ||
39 | void tick_start(unsigned int interval_in_ms) | 39 | void tick_start(unsigned int interval_in_ms) |
40 | { | 40 | { |
41 | imx31_clkctl_module_clock_gating(CG_EPIT1, CGM_ON_ALL); /* EPIT1 module | 41 | ccm_module_clock_gating(CG_EPIT1, CGM_ON_RUN_WAIT); /* EPIT1 module |
42 | clock ON - before writing | 42 | clock ON - before writing |
43 | regs! */ | 43 | regs! */ |
44 | EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable the counter */ | 44 | EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable the counter */ |
45 | CLKCTL_WIMR0 &= ~WIM_IPI_INT_EPIT1; /* Clear wakeup mask */ | 45 | CCM_WIMR0 &= ~CCM_WIMR0_IPI_INT_EPIT1; /* Clear wakeup mask */ |
46 | 46 | ||
47 | /* mcu_main_clk = 528MHz = 27MHz * 2 * ((9 + 7/9) / 1) | 47 | /* mcu_main_clk = 528MHz = 27MHz * 2 * ((9 + 7/9) / 1) |
48 | * CLKSRC = ipg_clk = 528MHz / 4 / 2 = 66MHz, | 48 | * CLKSRC = ipg_clk = 528MHz / 4 / 2 = 66MHz, |
@@ -53,13 +53,14 @@ void tick_start(unsigned int interval_in_ms) | |||
53 | * Compare interrupt enabled, | 53 | * Compare interrupt enabled, |
54 | * Count from load value */ | 54 | * Count from load value */ |
55 | EPITCR1 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW | | 55 | EPITCR1 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW | |
56 | EPITCR_PRESCALER(2640-1) | EPITCR_RLD | EPITCR_OCIEN | | 56 | (2640-1) << EPITCR_PRESCALER_POS | EPITCR_RLD | EPITCR_OCIEN | |
57 | EPITCR_ENMOD; | 57 | EPITCR_ENMOD; |
58 | 58 | ||
59 | EPITLR1 = interval_in_ms*25; /* Count down from interval */ | 59 | EPITLR1 = interval_in_ms*25; /* Count down from interval */ |
60 | EPITCMPR1 = 0; /* Event when counter reaches 0 */ | 60 | EPITCMPR1 = 0; /* Event when counter reaches 0 */ |
61 | EPITSR1 = EPITSR_OCIF; /* Clear any pending interrupt */ | 61 | EPITSR1 = EPITSR_OCIF; /* Clear any pending interrupt */ |
62 | avic_enable_int(EPIT1, IRQ, 7, EPIT1_HANDLER); | 62 | avic_enable_int(INT_EPIT1, INT_TYPE_IRQ, INT_PRIO_DEFAULT, |
63 | EPIT1_HANDLER); | ||
63 | EPITCR1 |= EPITCR_EN; /* Enable the counter */ | 64 | EPITCR1 |= EPITCR_EN; /* Enable the counter */ |
64 | } | 65 | } |
65 | 66 | ||
@@ -73,9 +74,9 @@ void kernel_device_init(void) | |||
73 | #ifdef BOOTLOADER | 74 | #ifdef BOOTLOADER |
74 | void tick_stop(void) | 75 | void tick_stop(void) |
75 | { | 76 | { |
76 | avic_disable_int(EPIT1); /* Disable insterrupt */ | 77 | avic_disable_int(INT_EPIT1); /* Disable insterrupt */ |
77 | EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable counter */ | 78 | EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable counter */ |
78 | EPITSR1 = EPITSR_OCIF; /* Clear pending */ | 79 | EPITSR1 = EPITSR_OCIF; /* Clear pending */ |
79 | imx31_clkctl_module_clock_gating(CG_EPIT1, CGM_OFF); /* Turn off module clock */ | 80 | ccm_module_clock_gating(CG_EPIT1, CGM_OFF); /* Turn off module clock */ |
80 | } | 81 | } |
81 | #endif | 82 | #endif |
diff --git a/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c b/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c index deaa2a0dcd..00f196a512 100644 --- a/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c | |||
@@ -130,8 +130,8 @@ void pcm_play_dma_init(void) | |||
130 | sdma_channel_init(DMA_PLAY_CH_NUM, &dma_play_cd, &dma_play_bd); | 130 | sdma_channel_init(DMA_PLAY_CH_NUM, &dma_play_cd, &dma_play_bd); |
131 | sdma_channel_set_priority(DMA_PLAY_CH_NUM, DMA_PLAY_CH_PRIORITY); | 131 | sdma_channel_set_priority(DMA_PLAY_CH_NUM, DMA_PLAY_CH_PRIORITY); |
132 | 132 | ||
133 | imx31_clkctl_module_clock_gating(CG_SSI1, CGM_ON_ALL); | 133 | ccm_module_clock_gating(CG_SSI1, CGM_ON_RUN_WAIT); |
134 | imx31_clkctl_module_clock_gating(CG_SSI2, CGM_ON_ALL); | 134 | ccm_module_clock_gating(CG_SSI2, CGM_ON_RUN_WAIT); |
135 | 135 | ||
136 | /* Reset & disable SSIs */ | 136 | /* Reset & disable SSIs */ |
137 | SSI_SCR1 &= ~SSI_SCR_SSIEN; | 137 | SSI_SCR1 &= ~SSI_SCR_SSIEN; |
@@ -178,12 +178,12 @@ void pcm_play_dma_init(void) | |||
178 | SSI_STCR_TEFS | SSI_STCR_TFEN0; | 178 | SSI_STCR_TEFS | SSI_STCR_TFEN0; |
179 | 179 | ||
180 | /* 16 bits per word, 2 words per frame */ | 180 | /* 16 bits per word, 2 words per frame */ |
181 | SSI_STCCR2 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) | | 181 | SSI_STCCR2 = SSI_STRCCR_WL16 | ((2-1) << SSI_STRCCR_DC_POS) | |
182 | SSI_STRCCR_PMw(4-1); | 182 | ((4-1) << SSI_STRCCR_PM_POS); |
183 | 183 | ||
184 | /* Transmit low watermark */ | 184 | /* Transmit low watermark */ |
185 | SSI_SFCSR2 = (SSI_SFCSR2 & ~SSI_SFCSR_TFWM0) | | 185 | SSI_SFCSR2 = (SSI_SFCSR2 & ~SSI_SFCSR_TFWM0) | |
186 | SSI_SFCSR_TFWM0w(8-SDMA_SSI_TXFIFO_WML); | 186 | ((8-SDMA_SSI_TXFIFO_WML) << SSI_SFCSR_TFWM0_POS); |
187 | SSI_STMSK2 = 0; | 187 | SSI_STMSK2 = 0; |
188 | 188 | ||
189 | /* SSI1 - provides MCLK to codec. Receives data from codec. */ | 189 | /* SSI1 - provides MCLK to codec. Receives data from codec. */ |
@@ -201,7 +201,7 @@ void pcm_play_dma_init(void) | |||
201 | * The hardware seems to force a divide by 4 even if all bits are | 201 | * The hardware seems to force a divide by 4 even if all bits are |
202 | * zero but comply by setting DIV2 and the others to zero. | 202 | * zero but comply by setting DIV2 and the others to zero. |
203 | */ | 203 | */ |
204 | SSI_STCCR1 = SSI_STRCCR_DIV2 | SSI_STRCCR_PMw(1-1); | 204 | SSI_STCCR1 = SSI_STRCCR_DIV2 | ((1-1) << SSI_STRCCR_PM_POS); |
205 | 205 | ||
206 | /* SSI1 - receive - asynchronous clocks */ | 206 | /* SSI1 - receive - asynchronous clocks */ |
207 | SSI_SCR1 = SSI_SCR_I2S_MODE_SLAVE; | 207 | SSI_SCR1 = SSI_SCR_I2S_MODE_SLAVE; |
@@ -210,12 +210,12 @@ void pcm_play_dma_init(void) | |||
210 | SSI_SRCR_REFS; | 210 | SSI_SRCR_REFS; |
211 | 211 | ||
212 | /* 16 bits per word, 2 words per frame */ | 212 | /* 16 bits per word, 2 words per frame */ |
213 | SSI_SRCCR1 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) | | 213 | SSI_SRCCR1 = SSI_STRCCR_WL16 | ((2-1) << SSI_STRCCR_DC_POS) | |
214 | SSI_STRCCR_PMw(4-1); | 214 | ((4-1) << SSI_STRCCR_PM_POS); |
215 | 215 | ||
216 | /* Receive high watermark */ | 216 | /* Receive high watermark */ |
217 | SSI_SFCSR1 = (SSI_SFCSR1 & ~SSI_SFCSR_RFWM0) | | 217 | SSI_SFCSR1 = (SSI_SFCSR1 & ~SSI_SFCSR_RFWM0) | |
218 | SSI_SFCSR_RFWM0w(SDMA_SSI_RXFIFO_WML); | 218 | (SDMA_SSI_RXFIFO_WML << SSI_SFCSR_RFWM0_POS); |
219 | SSI_SRMSK1 = 0; | 219 | SSI_SRMSK1 = 0; |
220 | 220 | ||
221 | /* Enable SSI1 (codec clock) */ | 221 | /* Enable SSI1 (codec clock) */ |
@@ -252,7 +252,7 @@ static void play_start_pcm(void) | |||
252 | static void play_stop_pcm(void) | 252 | static void play_stop_pcm(void) |
253 | { | 253 | { |
254 | /* Wait for FIFO to empty */ | 254 | /* Wait for FIFO to empty */ |
255 | while (SSI_SFCSR_TFCNT0r(SSI_SFCSR2) > 0); | 255 | while (SSI_SFCSR_TFCNT0 & SSI_SFCSR2); |
256 | 256 | ||
257 | /* Disable transmission */ | 257 | /* Disable transmission */ |
258 | SSI_STCR2 &= ~SSI_STCR_TFEN0; | 258 | SSI_STCR2 &= ~SSI_STCR_TFEN0; |
diff --git a/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c b/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c index 98604d1eef..f905057372 100644 --- a/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c | |||
@@ -58,7 +58,7 @@ static struct spi_module_descriptor | |||
58 | { | 58 | { |
59 | .base = (struct cspi_map *)CSPI1_BASE_ADDR, | 59 | .base = (struct cspi_map *)CSPI1_BASE_ADDR, |
60 | .cg = CG_CSPI1, | 60 | .cg = CG_CSPI1, |
61 | .ints = CSPI1, | 61 | .ints = INT_CSPI1, |
62 | .handler = CSPI1_HANDLER, | 62 | .handler = CSPI1_HANDLER, |
63 | }, | 63 | }, |
64 | #endif | 64 | #endif |
@@ -66,7 +66,7 @@ static struct spi_module_descriptor | |||
66 | { | 66 | { |
67 | .base = (struct cspi_map *)CSPI2_BASE_ADDR, | 67 | .base = (struct cspi_map *)CSPI2_BASE_ADDR, |
68 | .cg = CG_CSPI2, | 68 | .cg = CG_CSPI2, |
69 | .ints = CSPI2, | 69 | .ints = INT_CSPI2, |
70 | .handler = CSPI2_HANDLER, | 70 | .handler = CSPI2_HANDLER, |
71 | }, | 71 | }, |
72 | #endif | 72 | #endif |
@@ -74,7 +74,7 @@ static struct spi_module_descriptor | |||
74 | { | 74 | { |
75 | .base = (struct cspi_map *)CSPI3_BASE_ADDR, | 75 | .base = (struct cspi_map *)CSPI3_BASE_ADDR, |
76 | .cg = CG_CSPI3, | 76 | .cg = CG_CSPI3, |
77 | .ints = CSPI3, | 77 | .ints = INT_CSPI3, |
78 | .handler = CSPI3_HANDLER, | 78 | .handler = CSPI3_HANDLER, |
79 | }, | 79 | }, |
80 | #endif | 80 | #endif |
@@ -267,12 +267,13 @@ void spi_enable_module(struct spi_node *node) | |||
267 | struct cspi_map * const base = desc->base; | 267 | struct cspi_map * const base = desc->base; |
268 | 268 | ||
269 | /* Enable clock-gating register */ | 269 | /* Enable clock-gating register */ |
270 | imx31_clkctl_module_clock_gating(desc->cg, CGM_ON_ALL); | 270 | ccm_module_clock_gating(desc->cg, CGM_ON_RUN_WAIT); |
271 | /* Reset */ | 271 | /* Reset */ |
272 | spi_reset(base); | 272 | spi_reset(base); |
273 | desc->last = NULL; | 273 | desc->last = NULL; |
274 | /* Enable interrupt at controller level */ | 274 | /* Enable interrupt at controller level */ |
275 | avic_enable_int(desc->ints, IRQ, 6, desc->handler); | 275 | avic_enable_int(desc->ints, INT_TYPE_IRQ, INT_PRIO_DEFAULT, |
276 | desc->handler); | ||
276 | } | 277 | } |
277 | 278 | ||
278 | mutex_unlock(&desc->m); | 279 | mutex_unlock(&desc->m); |
@@ -297,7 +298,7 @@ void spi_disable_module(struct spi_node *node) | |||
297 | base->conreg &= ~CSPI_CONREG_EN; | 298 | base->conreg &= ~CSPI_CONREG_EN; |
298 | 299 | ||
299 | /* Disable interface clock */ | 300 | /* Disable interface clock */ |
300 | imx31_clkctl_module_clock_gating(desc->cg, CGM_OFF); | 301 | ccm_module_clock_gating(desc->cg, CGM_OFF); |
301 | } | 302 | } |
302 | 303 | ||
303 | mutex_unlock(&desc->m); | 304 | mutex_unlock(&desc->m); |
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-imx31.c b/firmware/target/arm/imx31/gigabeat-s/system-imx31.c index b3f0fd66c9..c710c5b93c 100644 --- a/firmware/target/arm/imx31/gigabeat-s/system-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/system-imx31.c | |||
@@ -49,7 +49,7 @@ unsigned int iim_prod_rev(void) | |||
49 | static void iim_init(void) | 49 | static void iim_init(void) |
50 | { | 50 | { |
51 | /* Initialize the IC revision info (required by SDMA) */ | 51 | /* Initialize the IC revision info (required by SDMA) */ |
52 | imx31_clkctl_module_clock_gating(CG_IIM, CGM_ON_ALL); | 52 | ccm_module_clock_gating(CG_IIM, CGM_ON_RUN_WAIT); |
53 | product_rev = IIM_PREV; | 53 | product_rev = IIM_PREV; |
54 | system_rev = IIM_SREV; | 54 | system_rev = IIM_SREV; |
55 | } | 55 | } |
@@ -59,13 +59,13 @@ static void iim_init(void) | |||
59 | /* Initialize the watchdog timer */ | 59 | /* Initialize the watchdog timer */ |
60 | void watchdog_init(unsigned int half_seconds) | 60 | void watchdog_init(unsigned int half_seconds) |
61 | { | 61 | { |
62 | uint16_t wcr = WDOG_WCR_WTw(half_seconds) | /* Timeout */ | 62 | uint16_t wcr = ((half_seconds << WDOG_WCR_WT_POS) & WDOG_WCR_WT) | |
63 | WDOG_WCR_WOE | /* WDOG output enabled */ | 63 | WDOG_WCR_WOE | /* WDOG output enabled */ |
64 | WDOG_WCR_WDA | /* WDOG assertion - no effect */ | 64 | WDOG_WCR_WDA | /* WDOG assertion - no effect */ |
65 | WDOG_WCR_SRS | /* System reset - no effect */ | 65 | WDOG_WCR_SRS | /* System reset - no effect */ |
66 | WDOG_WCR_WRE; /* Generate a WDOG signal */ | 66 | WDOG_WCR_WRE; /* Generate a WDOG signal */ |
67 | 67 | ||
68 | imx31_clkctl_module_clock_gating(CG_WDOG, CGM_ON_RUN_WAIT); | 68 | ccm_module_clock_gating(CG_WDOG, CGM_ON_RUN_WAIT); |
69 | 69 | ||
70 | WDOG_WCR = wcr; | 70 | WDOG_WCR = wcr; |
71 | WDOG_WSR = 0x5555; | 71 | WDOG_WSR = 0x5555; |
@@ -86,8 +86,8 @@ void watchdog_service(void) | |||
86 | /* Start the general-purpose timer (1MHz) */ | 86 | /* Start the general-purpose timer (1MHz) */ |
87 | void gpt_start(void) | 87 | void gpt_start(void) |
88 | { | 88 | { |
89 | imx31_clkctl_module_clock_gating(CG_GPT, CGM_ON_RUN_WAIT); | 89 | ccm_module_clock_gating(CG_GPT, CGM_ON_RUN_WAIT); |
90 | unsigned int ipg_mhz = imx31_clkctl_get_ipg_clk() / 1000000; | 90 | unsigned int ipg_mhz = ccm_get_ipg_clk() / 1000000; |
91 | 91 | ||
92 | GPTCR &= ~GPTCR_EN; /* Disable counter */ | 92 | GPTCR &= ~GPTCR_EN; /* Disable counter */ |
93 | GPTCR |= GPTCR_SWR; /* Reset module */ | 93 | GPTCR |= GPTCR_SWR; /* Reset module */ |
@@ -123,7 +123,7 @@ void system_reboot(void) | |||
123 | void system_exception_wait(void) | 123 | void system_exception_wait(void) |
124 | { | 124 | { |
125 | /* Called in many contexts so button reading may be a chore */ | 125 | /* Called in many contexts so button reading may be a chore */ |
126 | avic_disable_int(ALL); | 126 | avic_disable_int(INT_ALL); |
127 | core_idle(); | 127 | core_idle(); |
128 | while (1); | 128 | while (1); |
129 | } | 129 | } |
@@ -174,8 +174,8 @@ void system_init(void) | |||
174 | 174 | ||
175 | unsigned int i; | 175 | unsigned int i; |
176 | 176 | ||
177 | /* MCR WFI enables wait mode */ | 177 | /* MCR WFI enables wait mode (CCM_CCMR_LPM_WAIT_MODE = 0) */ |
178 | CLKCTL_CCMR &= ~(3 << 14); | 178 | imx31_regclr32(&CCM_CCMR, CCM_CCMR_LPM); |
179 | 179 | ||
180 | iim_init(); | 180 | iim_init(); |
181 | 181 | ||
@@ -189,7 +189,7 @@ void system_init(void) | |||
189 | imx31_regclr32(&UCR1_5, EUARTUCR1_UARTEN); | 189 | imx31_regclr32(&UCR1_5, EUARTUCR1_UARTEN); |
190 | 190 | ||
191 | for (i = 0; i < ARRAYLEN(disable_clocks); i++) | 191 | for (i = 0; i < ARRAYLEN(disable_clocks); i++) |
192 | imx31_clkctl_module_clock_gating(disable_clocks[i], CGM_OFF); | 192 | ccm_module_clock_gating(disable_clocks[i], CGM_OFF); |
193 | 193 | ||
194 | avic_init(); | 194 | avic_init(); |
195 | gpt_start(); | 195 | gpt_start(); |
@@ -242,7 +242,7 @@ void __attribute__((naked)) imx31_regclr32(volatile uint32_t *reg_p, | |||
242 | void system_prepare_fw_start(void) | 242 | void system_prepare_fw_start(void) |
243 | { | 243 | { |
244 | disable_interrupt(IRQ_FIQ_STATUS); | 244 | disable_interrupt(IRQ_FIQ_STATUS); |
245 | avic_disable_int(ALL); | 245 | avic_disable_int(INT_ALL); |
246 | mc13783_close(); | 246 | mc13783_close(); |
247 | tick_stop(); | 247 | tick_stop(); |
248 | } | 248 | } |
diff --git a/firmware/target/arm/imx31/gigabeat-s/timer-imx31.c b/firmware/target/arm/imx31/gigabeat-s/timer-imx31.c index 531baf3cc5..c4734a543b 100644 --- a/firmware/target/arm/imx31/gigabeat-s/timer-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/timer-imx31.c | |||
@@ -35,11 +35,11 @@ static void __attribute__((interrupt("IRQ"))) EPIT2_HANDLER(void) | |||
35 | static void stop_timer(bool clock_off) | 35 | static void stop_timer(bool clock_off) |
36 | { | 36 | { |
37 | /* Ensure clock gating on (before touching any module registers) */ | 37 | /* Ensure clock gating on (before touching any module registers) */ |
38 | imx31_clkctl_module_clock_gating(CG_EPIT2, CGM_ON_ALL); | 38 | ccm_module_clock_gating(CG_EPIT2, CGM_ON_RUN_WAIT); |
39 | /* Disable insterrupt */ | 39 | /* Disable insterrupt */ |
40 | avic_disable_int(EPIT2); | 40 | avic_disable_int(INT_EPIT2); |
41 | /* Clear wakeup mask */ | 41 | /* Clear wakeup mask */ |
42 | CLKCTL_WIMR0 &= ~WIM_IPI_INT_EPIT2; | 42 | CCM_WIMR0 &= ~CCM_WIMR0_IPI_INT_EPIT2; |
43 | /* Disable counter */ | 43 | /* Disable counter */ |
44 | EPITCR2 &= ~(EPITCR_OCIEN | EPITCR_EN); | 44 | EPITCR2 &= ~(EPITCR_OCIEN | EPITCR_EN); |
45 | /* Clear pending */ | 45 | /* Clear pending */ |
@@ -48,7 +48,7 @@ static void stop_timer(bool clock_off) | |||
48 | if (clock_off) | 48 | if (clock_off) |
49 | { | 49 | { |
50 | /* Final stop, not reset; don't clock module any longer */ | 50 | /* Final stop, not reset; don't clock module any longer */ |
51 | imx31_clkctl_module_clock_gating(CG_EPIT2, CGM_OFF); | 51 | ccm_module_clock_gating(CG_EPIT2, CGM_OFF); |
52 | } | 52 | } |
53 | } | 53 | } |
54 | 54 | ||
@@ -77,7 +77,7 @@ bool _timer_set(long cycles, bool start) | |||
77 | * Reload from modulus register, | 77 | * Reload from modulus register, |
78 | * Count from load value */ | 78 | * Count from load value */ |
79 | EPITCR2 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW | | 79 | EPITCR2 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW | |
80 | EPITCR_PRESCALER(1-1) | EPITCR_RLD | EPITCR_ENMOD; | 80 | (1-1) << EPITCR_PRESCALER_POS | EPITCR_RLD | EPITCR_ENMOD; |
81 | EPITLR2 = cycles; | 81 | EPITLR2 = cycles; |
82 | /* Event when counter reaches 0 */ | 82 | /* Event when counter reaches 0 */ |
83 | EPITCMPR2 = 0; | 83 | EPITCMPR2 = 0; |
@@ -95,7 +95,8 @@ bool _timer_register(void) | |||
95 | 95 | ||
96 | /* Enable interrupt */ | 96 | /* Enable interrupt */ |
97 | EPITCR2 |= EPITCR_OCIEN; | 97 | EPITCR2 |= EPITCR_OCIEN; |
98 | avic_enable_int(EPIT2, IRQ, 8, EPIT2_HANDLER); | 98 | avic_enable_int(INT_EPIT2, INT_TYPE_IRQ, INT_PRIO_DEFAULT, |
99 | EPIT2_HANDLER); | ||
99 | /* Start timer */ | 100 | /* Start timer */ |
100 | EPITCR2 |= EPITCR_EN; | 101 | EPITCR2 |= EPITCR_EN; |
101 | 102 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c b/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c index 8682cff7c7..2011d0c633 100644 --- a/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c | |||
@@ -89,7 +89,7 @@ void usb_enable(bool on) | |||
89 | { | 89 | { |
90 | /* Module clock should be on since since this could be called with | 90 | /* Module clock should be on since since this could be called with |
91 | * OFF initially and writing module registers would hardlock otherwise. */ | 91 | * OFF initially and writing module registers would hardlock otherwise. */ |
92 | imx31_clkctl_module_clock_gating(CG_USBOTG, CGM_ON_ALL); | 92 | ccm_module_clock_gating(CG_USBOTG, CGM_ON_RUN_WAIT); |
93 | enable_transceiver(true); | 93 | enable_transceiver(true); |
94 | 94 | ||
95 | if (on) | 95 | if (on) |
@@ -100,7 +100,7 @@ void usb_enable(bool on) | |||
100 | { | 100 | { |
101 | usb_core_exit(); | 101 | usb_core_exit(); |
102 | enable_transceiver(false); | 102 | enable_transceiver(false); |
103 | imx31_clkctl_module_clock_gating(CG_USBOTG, CGM_OFF); | 103 | ccm_module_clock_gating(CG_USBOTG, CGM_OFF); |
104 | } | 104 | } |
105 | } | 105 | } |
106 | 106 | ||
@@ -117,9 +117,14 @@ static void __attribute__((interrupt("IRQ"))) USB_OTG_HANDLER(void) | |||
117 | void usb_drv_int_enable(bool enable) | 117 | void usb_drv_int_enable(bool enable) |
118 | { | 118 | { |
119 | if (enable) | 119 | if (enable) |
120 | avic_enable_int(USB_OTG, IRQ, 7, USB_OTG_HANDLER); | 120 | { |
121 | else | 121 | avic_enable_int(INT_USB_OTG, INT_TYPE_IRQ, INT_PRIO_DEFAULT, |
122 | avic_disable_int(USB_OTG); | 122 | USB_OTG_HANDLER); |
123 | } | ||
124 | else | ||
125 | { | ||
126 | avic_disable_int(INT_USB_OTG); | ||
127 | } | ||
123 | } | 128 | } |
124 | 129 | ||
125 | /* Called during the bus reset interrupt when in detect mode */ | 130 | /* Called during the bus reset interrupt when in detect mode */ |
diff --git a/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c b/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c index 542f6eb633..cf9331144a 100644 --- a/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c | |||
@@ -52,11 +52,13 @@ void audiohw_init(void) | |||
52 | * WM Codec post divider (MCLKDIV=1.5): | 52 | * WM Codec post divider (MCLKDIV=1.5): |
53 | * INT_BIT_CLK (MCLK) / 1.5 = 11289600Hz = 256*fs = SYSCLK | 53 | * INT_BIT_CLK (MCLK) / 1.5 = 11289600Hz = 256*fs = SYSCLK |
54 | */ | 54 | */ |
55 | imx31_regmod32(&CLKCTL_PDR1, | 55 | imx31_regmod32(&CCM_PDR1, |
56 | PDR1_SSI1_PODFw(5-1) | PDR1_SSI2_PODFw(64-1) | | 56 | (1-1) << CCM_PDR1_SSI1_PRE_PODF_POS | |
57 | PDR1_SSI1_PRE_PODFw(1-1) | PDR1_SSI2_PRE_PODFw(8-1), | 57 | (5-1) << CCM_PDR1_SSI1_PODF_POS | |
58 | PDR1_SSI1_PODF | PDR1_SSI2_PODF | | 58 | (8-1) << CCM_PDR1_SSI2_PRE_PODF_POS, |
59 | PDR1_SSI1_PRE_PODF | PDR1_SSI2_PRE_PODF); | 59 | (64-1) << CCM_PDR1_SSI2_PODF_POS | |
60 | CCM_PDR1_SSI1_PODF | CCM_PDR1_SSI2_PODF | | ||
61 | CCM_PDR1_SSI1_PRE_PODF | CCM_PDR1_SSI2_PRE_PODF); | ||
60 | 62 | ||
61 | i2c_enable_node(&wm8978_i2c_node, true); | 63 | i2c_enable_node(&wm8978_i2c_node, true); |
62 | 64 | ||
diff --git a/firmware/target/arm/imx31/sdma-imx31.c b/firmware/target/arm/imx31/sdma-imx31.c index 4c5674afb9..97af419077 100644 --- a/firmware/target/arm/imx31/sdma-imx31.c +++ b/firmware/target/arm/imx31/sdma-imx31.c | |||
@@ -502,10 +502,11 @@ static bool setup_channel(struct channel_control_block *ccb_p) | |||
502 | /** Public routines **/ | 502 | /** Public routines **/ |
503 | void sdma_init(void) | 503 | void sdma_init(void) |
504 | { | 504 | { |
505 | imx31_clkctl_module_clock_gating(CG_SDMA, CGM_ON_RUN_WAIT); | ||
506 | int i; | 505 | int i; |
507 | unsigned long acr; | 506 | unsigned long acr; |
508 | 507 | ||
508 | ccm_module_clock_gating(CG_SDMA, CGM_ON_RUN_WAIT); | ||
509 | |||
509 | /* Reset the controller */ | 510 | /* Reset the controller */ |
510 | SDMA_RESET |= SDMA_RESET_RESET; | 511 | SDMA_RESET |= SDMA_RESET_RESET; |
511 | while (SDMA_RESET & SDMA_RESET_RESET); | 512 | while (SDMA_RESET & SDMA_RESET_RESET); |
@@ -532,11 +533,11 @@ void sdma_init(void) | |||
532 | /* 32-word channel contexts, use default bootscript address */ | 533 | /* 32-word channel contexts, use default bootscript address */ |
533 | SDMA_CHN0ADDR = SDMA_CHN0ADDR_SMSZ | 0x0050; | 534 | SDMA_CHN0ADDR = SDMA_CHN0ADDR_SMSZ | 0x0050; |
534 | 535 | ||
535 | avic_enable_int(SDMA, IRQ, 8, SDMA_HANDLER); | 536 | avic_enable_int(INT_SDMA, INT_TYPE_IRQ, INT_PRIO_DEFAULT+1, SDMA_HANDLER); |
536 | 537 | ||
537 | /* SDMA core must run at the proper frequency based upon the AHB/IPG ratio */ | 538 | /* SDMA core must run at the proper frequency based upon the AHB/IPG |
538 | acr = (imx31_clkctl_get_ahb_clk() / imx31_clkctl_get_ipg_clk()) < 2 ? | 539 | * ratio */ |
539 | SDMA_CONFIG_ACR : 0; | 540 | acr = (ccm_get_ahb_clk() / ccm_get_ipg_clk()) < 2 ? SDMA_CONFIG_ACR : 0; |
540 | 541 | ||
541 | /* No dsp, no debug | 542 | /* No dsp, no debug |
542 | * Static context switching - TLSbo86520L SW Workaround for SDMA Chnl0 | 543 | * Static context switching - TLSbo86520L SW Workaround for SDMA Chnl0 |