diff options
Diffstat (limited to 'firmware/target')
-rw-r--r-- | firmware/target/arm/tms320dm320/app.lds | 8 | ||||
-rwxr-xr-x | firmware/target/arm/tms320dm320/crt0.S | 4 |
2 files changed, 12 insertions, 0 deletions
diff --git a/firmware/target/arm/tms320dm320/app.lds b/firmware/target/arm/tms320dm320/app.lds index 64610a3577..0a9aa85bc4 100644 --- a/firmware/target/arm/tms320dm320/app.lds +++ b/firmware/target/arm/tms320dm320/app.lds | |||
@@ -81,9 +81,13 @@ SECTIONS | |||
81 | _vectorsstart = .; | 81 | _vectorsstart = .; |
82 | *(.vectors); | 82 | *(.vectors); |
83 | _vectorsend = .; | 83 | _vectorsend = .; |
84 | #ifndef CREATIVE_ZVx | ||
84 | } > IRAM AT> DRAM | 85 | } > IRAM AT> DRAM |
85 | 86 | ||
86 | _vectorscopy = LOADADDR(.vectors); | 87 | _vectorscopy = LOADADDR(.vectors); |
88 | #else | ||
89 | } > IRAM | ||
90 | #endif | ||
87 | 91 | ||
88 | .iram : | 92 | .iram : |
89 | { | 93 | { |
@@ -93,9 +97,13 @@ SECTIONS | |||
93 | *(.idata) | 97 | *(.idata) |
94 | . = ALIGN(0x4); | 98 | . = ALIGN(0x4); |
95 | _iramend = .; | 99 | _iramend = .; |
100 | #ifndef CREATIVE_ZVx | ||
96 | } > IRAM AT> DRAM | 101 | } > IRAM AT> DRAM |
97 | 102 | ||
98 | _iramcopy = LOADADDR(.iram); | 103 | _iramcopy = LOADADDR(.iram); |
104 | #else | ||
105 | } > IRAM | ||
106 | #endif | ||
99 | 107 | ||
100 | .ibss (NOLOAD) : | 108 | .ibss (NOLOAD) : |
101 | { | 109 | { |
diff --git a/firmware/target/arm/tms320dm320/crt0.S b/firmware/target/arm/tms320dm320/crt0.S index a0b5a5abfb..ba5daa9117 100755 --- a/firmware/target/arm/tms320dm320/crt0.S +++ b/firmware/target/arm/tms320dm320/crt0.S | |||
@@ -44,6 +44,7 @@ start: | |||
44 | 44 | ||
45 | msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */ | 45 | msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */ |
46 | 46 | ||
47 | #ifndef CREATIVE_ZVx | ||
47 | /* Copy exception handler code to address 0 */ | 48 | /* Copy exception handler code to address 0 */ |
48 | ldr r2, =_vectorsstart | 49 | ldr r2, =_vectorsstart |
49 | ldr r3, =_vectorsend | 50 | ldr r3, =_vectorsend |
@@ -53,6 +54,7 @@ start: | |||
53 | ldrhi r5, [r4], #4 | 54 | ldrhi r5, [r4], #4 |
54 | strhi r5, [r2], #4 | 55 | strhi r5, [r2], #4 |
55 | bhi 1b | 56 | bhi 1b |
57 | #endif | ||
56 | 58 | ||
57 | /* Disable data and instruction cache, high vectors (at 0xffff0000 instead of 0x00000000) */ | 59 | /* Disable data and instruction cache, high vectors (at 0xffff0000 instead of 0x00000000) */ |
58 | mrc p15, 0, r0, c1, c0, 0 | 60 | mrc p15, 0, r0, c1, c0, 0 |
@@ -105,6 +107,7 @@ start: | |||
105 | strhi r4, [r2], #4 | 107 | strhi r4, [r2], #4 |
106 | bhi 1b | 108 | bhi 1b |
107 | 109 | ||
110 | #ifndef CREATIVE_ZVx | ||
108 | /* Copy the IRAM */ | 111 | /* Copy the IRAM */ |
109 | ldr r2, =_iramcopy | 112 | ldr r2, =_iramcopy |
110 | ldr r3, =_iramstart | 113 | ldr r3, =_iramstart |
@@ -114,6 +117,7 @@ start: | |||
114 | ldrhi r5, [r2], #4 | 117 | ldrhi r5, [r2], #4 |
115 | strhi r5, [r3], #4 | 118 | strhi r5, [r3], #4 |
116 | bhi 1b | 119 | bhi 1b |
120 | #endif | ||
117 | #endif /* !BOOTLOADER,!STUB */ | 121 | #endif /* !BOOTLOADER,!STUB */ |
118 | 122 | ||
119 | /* Initialise bss section to zero */ | 123 | /* Initialise bss section to zero */ |