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-rw-r--r--firmware/target/arm/as3525/clock-target.h35
-rw-r--r--firmware/target/arm/as3525/sansa-c200v2/lcd-c200v2.c2
-rw-r--r--firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c2
-rw-r--r--firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c2
-rw-r--r--firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c2
5 files changed, 22 insertions, 21 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h
index a227f464ff..21fd4c65d2 100644
--- a/firmware/target/arm/as3525/clock-target.h
+++ b/firmware/target/arm/as3525/clock-target.h
@@ -21,6 +21,9 @@
21#ifndef CLOCK_TARGET_H 21#ifndef CLOCK_TARGET_H
22#define CLOCK_TARGET_H 22#define CLOCK_TARGET_H
23 23
24/* returns clock divider, given maximal target frequency and clock reference */
25#define CLK_DIV(ref, target) ((ref + target - 1) / target)
26
24/* PLL */ 27/* PLL */
25 28
26#define AS3525_PLLA_FREQ 248000000 29#define AS3525_PLLA_FREQ 248000000
@@ -39,28 +42,26 @@
39 42
40/* peripherals */ 43/* peripherals */
41 44
42#define AS3525_PCLK_FREQ 65000000 45#define AS3525_PCLK_FREQ 62000000
43 46#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */
44#define AS3525_IDE_FREQ 90000000 47#error PCLK frequency is too low : clock divider will not fit !
48#endif
45 49
46#define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ 50#define AS3525_IDE_FREQ 66000000
51#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) >= (1<<4) /* 4 bits */
52#error IDE frequency is too low : clock divider will not fit !
53#endif
47 54
48#define AS3525_I2C_FREQ 400000 55#define AS3525_I2C_FREQ 400000
56#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_I2C_FREQ)) >= (1<<16) /* 2*8 bits */
57#error I2C frequency is too low : clock divider will not fit !
58#endif
49 59
50/* LCD controller : varies on the models */ 60#define AS3525_DBOP_FREQ 32000000
51#if defined(SANSA_CLIP) 61#if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */
52#define AS3525_DBOP_FREQ 6000000 62#error DBOP frequency is too low : clock divider will not fit !
53#elif defined(SANSA_M200V4)
54#define AS3525_DBOP_FREQ 8000000
55#elif defined(SANSA_FUZE)
56#define AS3525_DBOP_FREQ 8000000
57#elif defined(SANSA_E200V2)
58#define AS3525_DBOP_FREQ 8000000
59#elif defined(SANSA_C200V2)
60#define AS3525_DBOP_FREQ 8000000
61#endif 63#endif
62 64
63/* macro for not giving a target clock > at the one provided */ 65#define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */
64#define CLK_DIV(ref, target) ((ref + target - 1) / target)
65 66
66#endif /* CLOCK_TARGET_H */ 67#endif /* CLOCK_TARGET_H */
diff --git a/firmware/target/arm/as3525/sansa-c200v2/lcd-c200v2.c b/firmware/target/arm/as3525/sansa-c200v2/lcd-c200v2.c
index 88adcd9d96..0ffe0bdc8d 100644
--- a/firmware/target/arm/as3525/sansa-c200v2/lcd-c200v2.c
+++ b/firmware/target/arm/as3525/sansa-c200v2/lcd-c200v2.c
@@ -98,7 +98,7 @@ static void lcd_delay(int x)
98/* DBOP initialisation, do what OF does */ 98/* DBOP initialisation, do what OF does */
99static void ams3525_dbop_init(void) 99static void ams3525_dbop_init(void)
100{ 100{
101 CGU_DBOP = (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ); 101 CGU_DBOP = (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1);
102 102
103 DBOP_TIMPOL_01 = 0xe167e167; 103 DBOP_TIMPOL_01 = 0xe167e167;
104 DBOP_TIMPOL_23 = 0xe167006e; 104 DBOP_TIMPOL_23 = 0xe167006e;
diff --git a/firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c b/firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c
index 4669abdf7d..a88e5faa0a 100644
--- a/firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c
+++ b/firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c
@@ -70,7 +70,7 @@
70/* DBOP initialisation, do what OF does */ 70/* DBOP initialisation, do what OF does */
71static void ams3525_dbop_init(void) 71static void ams3525_dbop_init(void)
72{ 72{
73 CGU_DBOP |= (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ); 73 CGU_DBOP |= (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1);
74 74
75 GPIOB_AFSEL = 0x08; /* DBOP on pin 3 */ 75 GPIOB_AFSEL = 0x08; /* DBOP on pin 3 */
76 GPIOC_AFSEL = 0x0f; /* DBOP on pins 3:0 */ 76 GPIOC_AFSEL = 0x0f; /* DBOP on pins 3:0 */
diff --git a/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c b/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c
index ef21893494..9e23dac340 100644
--- a/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c
+++ b/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c
@@ -108,7 +108,7 @@ static void lcd_delay(int x)
108/* DBOP initialisation, do what OF does */ 108/* DBOP initialisation, do what OF does */
109static void ams3525_dbop_init(void) 109static void ams3525_dbop_init(void)
110{ 110{
111 CGU_DBOP = (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ); 111 CGU_DBOP = (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1);
112 112
113 DBOP_TIMPOL_01 = 0xe167e167; 113 DBOP_TIMPOL_01 = 0xe167e167;
114 DBOP_TIMPOL_23 = 0xe167006e; 114 DBOP_TIMPOL_23 = 0xe167006e;
diff --git a/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c b/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c
index 141b890861..f0c85f53b4 100644
--- a/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c
+++ b/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c
@@ -50,7 +50,7 @@ static bool lcd_busy = false;
50 50
51static void as3525_dbop_init(void) 51static void as3525_dbop_init(void)
52{ 52{
53 CGU_DBOP = (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ); 53 CGU_DBOP = (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1);
54 54
55 DBOP_TIMPOL_01 = 0xe167e167; 55 DBOP_TIMPOL_01 = 0xe167e167;
56 DBOP_TIMPOL_23 = 0xe167006e; 56 DBOP_TIMPOL_23 = 0xe167006e;