diff options
Diffstat (limited to 'firmware/target')
-rw-r--r-- | firmware/target/arm/i2s-pp.c | 8 | ||||
-rw-r--r-- | firmware/target/arm/pcm-pp.c | 41 |
2 files changed, 1 insertions, 48 deletions
diff --git a/firmware/target/arm/i2s-pp.c b/firmware/target/arm/i2s-pp.c index 6397c1c0ac..750a2b8155 100644 --- a/firmware/target/arm/i2s-pp.c +++ b/firmware/target/arm/i2s-pp.c | |||
@@ -71,15 +71,7 @@ void i2s_reset(void) | |||
71 | IISDIV = 7; | 71 | IISDIV = 7; |
72 | #endif /* HAVE_AS3514 */ | 72 | #endif /* HAVE_AS3514 */ |
73 | 73 | ||
74 | #if defined (IRIVER_H10) || defined (IRIVER_H10_5GB) || defined(IPOD_NANO) \ | ||
75 | || defined(IPOD_VIDEO) || defined(IPOD_MINI2G) \ | ||
76 | || defined(IPOD_COLOR) || defined(IPOD_4G) \ | ||
77 | || defined (SANSA_C200) || defined (SANSA_E200) | ||
78 | /* Nano works fine with IIS_FIFO_FORMAT_LE16 as well */ | ||
79 | IISCONFIG = ((IISCONFIG & ~IIS_FIFO_FORMAT_MASK) | IIS_FIFO_FORMAT_LE16_2); | 74 | IISCONFIG = ((IISCONFIG & ~IIS_FIFO_FORMAT_MASK) | IIS_FIFO_FORMAT_LE16_2); |
80 | #else | ||
81 | IISCONFIG = ((IISCONFIG & ~IIS_FIFO_FORMAT_MASK) | IIS_FIFO_FORMAT_LE32); | ||
82 | #endif | ||
83 | 75 | ||
84 | /* RX_ATN_LVL = when 12 slots full */ | 76 | /* RX_ATN_LVL = when 12 slots full */ |
85 | /* TX_ATN_LVL = when 12 slots empty */ | 77 | /* TX_ATN_LVL = when 12 slots empty */ |
diff --git a/firmware/target/arm/pcm-pp.c b/firmware/target/arm/pcm-pp.c index dcf2ee9c53..d2a503c0da 100644 --- a/firmware/target/arm/pcm-pp.c +++ b/firmware/target/arm/pcm-pp.c | |||
@@ -25,25 +25,12 @@ | |||
25 | 25 | ||
26 | /** DMA **/ | 26 | /** DMA **/ |
27 | 27 | ||
28 | /* List of transfer settings. Defined by player in order to have an inventory | 28 | #ifdef CPU_PP502x |
29 | of working settings. DMA-compatible settings should be found for here, i2s, | ||
30 | and codec setup using "arithmetic" the hardware supports like halfword | ||
31 | swapping. Try to use 32-bit packed in IIS modes if possible. */ | ||
32 | #if defined(SANSA_C200) || defined(SANSA_E200) \ | ||
33 | || defined(IRIVER_H10) || defined(IRIVER_H10_5GB) || defined(IPOD_NANO) \ | ||
34 | || defined(IPOD_VIDEO) || defined(IPOD_MINI2G) \ | ||
35 | || defined(IPOD_COLOR) || defined(IPOD_4G) | ||
36 | /* 16-bit, L-R packed into 32 bits with left in the least significant halfword */ | 29 | /* 16-bit, L-R packed into 32 bits with left in the least significant halfword */ |
37 | #define SAMPLE_SIZE 16 | 30 | #define SAMPLE_SIZE 16 |
38 | #define TRANSFER_SIZE 32 | ||
39 | #elif 0 | ||
40 | /* 16-bit, one left 16-bit sample followed by one right 16-bit sample */ | ||
41 | #define SAMPLE_SIZE 16 | ||
42 | #define TRANSFER_SIZE 16 | ||
43 | #else | 31 | #else |
44 | /* 32-bit, one left 32-bit sample followed by one right 32-bit sample */ | 32 | /* 32-bit, one left 32-bit sample followed by one right 32-bit sample */ |
45 | #define SAMPLE_SIZE 32 | 33 | #define SAMPLE_SIZE 32 |
46 | #define TRANSFER_SIZE 32 | ||
47 | #endif | 34 | #endif |
48 | 35 | ||
49 | struct dma_data | 36 | struct dma_data |
@@ -51,11 +38,7 @@ struct dma_data | |||
51 | /* NOTE: The order of size and p is important if you use assembler | 38 | /* NOTE: The order of size and p is important if you use assembler |
52 | optimised fiq handler, so don't change it. */ | 39 | optimised fiq handler, so don't change it. */ |
53 | #if SAMPLE_SIZE == 16 | 40 | #if SAMPLE_SIZE == 16 |
54 | #if TRANSFER_SIZE == 16 | ||
55 | uint16_t *p; | ||
56 | #elif TRANSFER_SIZE == 32 | ||
57 | uint32_t *p; | 41 | uint32_t *p; |
58 | #endif | ||
59 | #elif SAMPLE_SIZE == 32 | 42 | #elif SAMPLE_SIZE == 32 |
60 | uint16_t *p; | 43 | uint16_t *p; |
61 | #endif | 44 | #endif |
@@ -140,15 +123,8 @@ void fiq_playback(void) | |||
140 | "ands r12, r12, %[mask] \n" | 123 | "ands r12, r12, %[mask] \n" |
141 | "beq .exit \n" /* FIFO full, exit */ | 124 | "beq .exit \n" /* FIFO full, exit */ |
142 | #if SAMPLE_SIZE == 16 | 125 | #if SAMPLE_SIZE == 16 |
143 | #if TRANSFER_SIZE == 16 | ||
144 | "ldrh r12, [r8], #2 \n" /* Load left channel */ | ||
145 | "strh r12, [r10, %[wr]] \n" /* Store it */ | ||
146 | "ldrh r12, [r8], #2 \n" /* Load right channel */ | ||
147 | "strh r12, [r10, %[wr]] \n" /* Store it */ | ||
148 | #elif TRANSFER_SIZE == 32 | ||
149 | "ldr r12, [r8], #4 \n" /* load two samples */ | 126 | "ldr r12, [r8], #4 \n" /* load two samples */ |
150 | "str r12, [r10, %[wr]] \n" /* write them */ | 127 | "str r12, [r10, %[wr]] \n" /* write them */ |
151 | #endif | ||
152 | #elif SAMPLE_SIZE == 32 | 128 | #elif SAMPLE_SIZE == 32 |
153 | "ldr r12, [r8], #4 \n" /* load two samples */ | 129 | "ldr r12, [r8], #4 \n" /* load two samples */ |
154 | "mov r12, r12, ror #16 \n" /* put left sample at the top bits */ | 130 | "mov r12, r12, ror #16 \n" /* put left sample at the top bits */ |
@@ -206,12 +182,7 @@ void fiq_playback(void) | |||
206 | return; | 182 | return; |
207 | } | 183 | } |
208 | #if SAMPLE_SIZE == 16 | 184 | #if SAMPLE_SIZE == 16 |
209 | #if TRANSFER_SIZE == 16 | ||
210 | IISFIFO_WRH = *dma_play_data.p++; | ||
211 | IISFIFO_WRH = *dma_play_data.p++; | ||
212 | #elif TRANSFER_SIZE == 32 | ||
213 | IISFIFO_WR = *dma_play_data.p++; | 185 | IISFIFO_WR = *dma_play_data.p++; |
214 | #endif | ||
215 | #elif SAMPLE_SIZE == 32 | 186 | #elif SAMPLE_SIZE == 32 |
216 | IISFIFO_WR = *dma_play_data.p++ << 16; | 187 | IISFIFO_WR = *dma_play_data.p++ << 16; |
217 | IISFIFO_WR = *dma_play_data.p++ << 16; | 188 | IISFIFO_WR = *dma_play_data.p++ << 16; |
@@ -274,12 +245,7 @@ static void play_start_pcm(void) | |||
274 | } | 245 | } |
275 | 246 | ||
276 | #if SAMPLE_SIZE == 16 | 247 | #if SAMPLE_SIZE == 16 |
277 | #if TRANSFER_SIZE == 16 | ||
278 | IISFIFO_WRH = *dma_play_data.p++; | ||
279 | IISFIFO_WRH = *dma_play_data.p++; | ||
280 | #elif TRANSFER_SIZE == 32 | ||
281 | IISFIFO_WR = *dma_play_data.p++; | 248 | IISFIFO_WR = *dma_play_data.p++; |
282 | #endif | ||
283 | #elif SAMPLE_SIZE == 32 | 249 | #elif SAMPLE_SIZE == 32 |
284 | IISFIFO_WR = *dma_play_data.p++ << 16; | 250 | IISFIFO_WR = *dma_play_data.p++ << 16; |
285 | IISFIFO_WR = *dma_play_data.p++ << 16; | 251 | IISFIFO_WR = *dma_play_data.p++ << 16; |
@@ -496,12 +462,7 @@ void fiq_record(void) | |||
496 | } | 462 | } |
497 | 463 | ||
498 | #if SAMPLE_SIZE == 16 | 464 | #if SAMPLE_SIZE == 16 |
499 | #if TRANSFER_SIZE == 16 | ||
500 | *dma_rec_data.p++ = IISFIFO_RDH; | ||
501 | *dma_rec_data.p++ = IISFIFO_RDH; | ||
502 | #elif TRANSFER_SIZE == 32 | ||
503 | *dma_rec_data.p++ = IISFIFO_RD; | 465 | *dma_rec_data.p++ = IISFIFO_RD; |
504 | #endif | ||
505 | #elif SAMPLE_SIZE == 32 | 466 | #elif SAMPLE_SIZE == 32 |
506 | *dma_rec_data.p++ = IISFIFO_RD >> 16; | 467 | *dma_rec_data.p++ = IISFIFO_RD >> 16; |
507 | *dma_rec_data.p++ = IISFIFO_RD >> 16; | 468 | *dma_rec_data.p++ = IISFIFO_RD >> 16; |