diff options
Diffstat (limited to 'firmware/target')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/fiiom3k/power-fiiom3k.c | 10 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/system-target.h | 3 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/system-x1000.c | 2 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/usb-x1000.c | 223 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/cpm.h | 394 |
5 files changed, 632 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/power-fiiom3k.c b/firmware/target/mips/ingenic_x1000/fiiom3k/power-fiiom3k.c index a3760d145a..c346d16890 100644 --- a/firmware/target/mips/ingenic_x1000/fiiom3k/power-fiiom3k.c +++ b/firmware/target/mips/ingenic_x1000/fiiom3k/power-fiiom3k.c | |||
@@ -23,6 +23,9 @@ | |||
23 | #include "adc.h" | 23 | #include "adc.h" |
24 | #include "system.h" | 24 | #include "system.h" |
25 | #include "kernel.h" | 25 | #include "kernel.h" |
26 | #ifdef HAVE_USB_CHARGING_ENABLE | ||
27 | # include "usb_core.h" | ||
28 | #endif | ||
26 | #include "axp173.h" | 29 | #include "axp173.h" |
27 | #include "i2c-x1000.h" | 30 | #include "i2c-x1000.h" |
28 | #include "gpio-x1000.h" | 31 | #include "gpio-x1000.h" |
@@ -81,6 +84,13 @@ void power_init(void) | |||
81 | mdelay(5); | 84 | mdelay(5); |
82 | } | 85 | } |
83 | 86 | ||
87 | #ifdef HAVE_USB_CHARGING_ENABLE | ||
88 | void usb_charging_maxcurrent_change(int maxcurrent) | ||
89 | { | ||
90 | axp173_set_charge_current(maxcurrent); | ||
91 | } | ||
92 | #endif | ||
93 | |||
84 | void adc_init(void) | 94 | void adc_init(void) |
85 | { | 95 | { |
86 | } | 96 | } |
diff --git a/firmware/target/mips/ingenic_x1000/system-target.h b/firmware/target/mips/ingenic_x1000/system-target.h index 45a1eab1ff..e5e48e382b 100644 --- a/firmware/target/mips/ingenic_x1000/system-target.h +++ b/firmware/target/mips/ingenic_x1000/system-target.h | |||
@@ -42,6 +42,9 @@ | |||
42 | # define X1000_CPUIDLE_STATS | 42 | # define X1000_CPUIDLE_STATS |
43 | #endif | 43 | #endif |
44 | 44 | ||
45 | #define OTGBASE 0xb3500000 | ||
46 | #define USB_NUM_ENDPOINTS 9 | ||
47 | |||
45 | #include "mmu-mips.h" | 48 | #include "mmu-mips.h" |
46 | #include "mipsregs.h" | 49 | #include "mipsregs.h" |
47 | #include "mipsr2-endian.h" | 50 | #include "mipsr2-endian.h" |
diff --git a/firmware/target/mips/ingenic_x1000/system-x1000.c b/firmware/target/mips/ingenic_x1000/system-x1000.c index 33d8db7222..c0b0dbc65e 100644 --- a/firmware/target/mips/ingenic_x1000/system-x1000.c +++ b/firmware/target/mips/ingenic_x1000/system-x1000.c | |||
@@ -191,6 +191,8 @@ static void UIRQ(void) | |||
191 | } | 191 | } |
192 | 192 | ||
193 | #define intr(name) extern __attribute__((weak, alias("UIRQ"))) void name(void) | 193 | #define intr(name) extern __attribute__((weak, alias("UIRQ"))) void name(void) |
194 | /* DWC2 USB interrupt */ | ||
195 | #define OTG INT_USB_FUNC | ||
194 | 196 | ||
195 | /* Main interrupts */ | 197 | /* Main interrupts */ |
196 | intr(DMIC); intr(AIC); intr(SFC); intr(SSI0); intr(OTG); intr(AES); | 198 | intr(DMIC); intr(AIC); intr(SFC); intr(SSI0); intr(OTG); intr(AES); |
diff --git a/firmware/target/mips/ingenic_x1000/usb-x1000.c b/firmware/target/mips/ingenic_x1000/usb-x1000.c new file mode 100644 index 0000000000..32413b0b94 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/usb-x1000.c | |||
@@ -0,0 +1,223 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "system.h" | ||
23 | #include "usb.h" | ||
24 | #include "usb_core.h" | ||
25 | #include "usb_drv.h" | ||
26 | #include "usb-designware.h" | ||
27 | #include "irq-x1000.h" | ||
28 | #include "gpio-x1000.h" | ||
29 | #include "x1000/cpm.h" | ||
30 | |||
31 | #ifdef FIIO_M3K | ||
32 | # define USB_DETECT_PORT GPIO_B | ||
33 | # define USB_DETECT_PIN (1 << 11) | ||
34 | # define USB_DETECT_PIN_INT GPIOB11 | ||
35 | # define USB_ID_PORT GPIO_B | ||
36 | # define USB_ID_PIN (1 << 7) | ||
37 | #else | ||
38 | # ifndef USB_NONE | ||
39 | # error "please add USB GPIO pins" | ||
40 | # endif | ||
41 | #endif | ||
42 | |||
43 | #define USB_DRVVBUS_PORT GPIO_B | ||
44 | #define USB_DRVVBUS_PIN (1 << 25) | ||
45 | |||
46 | /* | ||
47 | * USB-Designware driver API | ||
48 | */ | ||
49 | |||
50 | const struct usb_dw_config usb_dw_config = { | ||
51 | .phytype = DWC_PHYTYPE_UTMI_16, | ||
52 | |||
53 | /* Available FIFO memory: 3576 words */ | ||
54 | .rx_fifosz = 1024, | ||
55 | .nptx_fifosz = 128, /* 1 dedicated FIFO for EP0 */ | ||
56 | .ptx_fifosz = 768, /* 3 dedicated FIFOs */ | ||
57 | |||
58 | #ifndef USB_DW_ARCH_SLAVE | ||
59 | .ahb_burst_len = HBSTLEN_INCR16, | ||
60 | /* Disable Rx FIFO thresholding. It appears to cause problems, | ||
61 | * apparently a known issue -- Synopsys recommends disabling it | ||
62 | * because it can cause issues during certain error conditions. | ||
63 | */ | ||
64 | .ahb_threshold = 0, | ||
65 | #else | ||
66 | .disable_double_buffering = false, | ||
67 | #endif | ||
68 | }; | ||
69 | |||
70 | /* USB PHY init from Linux kernel code: | ||
71 | * - arch/mips/xburst/soc-x1000/common/cpm_usb.c | ||
72 | * Copyright (C) 2005-2017 Ingenic Semiconductor | ||
73 | */ | ||
74 | void usb_dw_target_enable_clocks(void) | ||
75 | { | ||
76 | /* Enable CPM clock */ | ||
77 | jz_writef(CPM_CLKGR, OTG(0)); | ||
78 | #if X1000_EXCLK_FREQ == 24000000 | ||
79 | jz_writef(CPM_USBCDR, CLKSRC_V(EXCLK), CE(1), CLKDIV(0), PHY_GATE(0)); | ||
80 | #else | ||
81 | # error "please add USB clock settings for 26 MHz EXCLK" | ||
82 | #endif | ||
83 | while(jz_readf(CPM_USBCDR, BUSY)); | ||
84 | jz_writef(CPM_USBCDR, CE(0)); | ||
85 | |||
86 | /* PHY soft reset */ | ||
87 | jz_writef(CPM_SRBC, OTG_SR(1)); | ||
88 | udelay(10); | ||
89 | jz_writef(CPM_SRBC, OTG_SR(0)); | ||
90 | |||
91 | /* Ungate PHY clock */ | ||
92 | jz_writef(CPM_OPCR, GATE_USBPHY_CLK(0)); | ||
93 | |||
94 | /* Exit suspend state */ | ||
95 | jz_writef(CPM_OPCR, SPENDN0(1)); | ||
96 | udelay(45); | ||
97 | |||
98 | /* Program core configuration */ | ||
99 | jz_overwritef(CPM_USBVBFIL, | ||
100 | IDDIGFIL(0), | ||
101 | VBFIL(0)); | ||
102 | jz_overwritef(CPM_USBRDT, | ||
103 | HB_MASK(0), | ||
104 | VBFIL_LD_EN(1), | ||
105 | IDDIG_EN(0), | ||
106 | RDT(0x96)); | ||
107 | jz_overwritef(CPM_USBPCR, | ||
108 | OTG_DISABLE(1), | ||
109 | COMMONONN(1), | ||
110 | VBUSVLDEXT(1), | ||
111 | VBUSVLDEXTSEL(1), | ||
112 | SQRXTUNE(7), | ||
113 | TXPREEMPHTUNE(1), | ||
114 | TXHSXVTUNE(1), | ||
115 | TXVREFTUNE(7)); | ||
116 | jz_overwritef(CPM_USBPCR1, | ||
117 | BVLD_REG(1), | ||
118 | REFCLK_SEL_V(CLKCORE), | ||
119 | REFCLK_DIV_V(24MHZ), /* applies for 26 MHz EXCLK too */ | ||
120 | WORD_IF_V(16BIT)); | ||
121 | |||
122 | /* Power on reset */ | ||
123 | jz_writef(CPM_USBPCR, POR(1)); | ||
124 | mdelay(1); | ||
125 | jz_writef(CPM_USBPCR, POR(0)); | ||
126 | mdelay(1); | ||
127 | } | ||
128 | |||
129 | void usb_dw_target_disable_clocks(void) | ||
130 | { | ||
131 | /* Suspend and power down PHY, then gate its clock */ | ||
132 | jz_writef(CPM_OPCR, SPENDN0(0)); | ||
133 | udelay(5); | ||
134 | jz_writef(CPM_USBPCR, OTG_DISABLE(1), SIDDQ(1)); | ||
135 | jz_writef(CPM_OPCR, GATE_USBPHY_CLK(1)); | ||
136 | |||
137 | /* Disable CPM clock */ | ||
138 | jz_writef(CPM_USBCDR, CE(1), STOP(1), PHY_GATE(1)); | ||
139 | while(jz_readf(CPM_USBCDR, BUSY)); | ||
140 | jz_writef(CPM_USBCDR, CE(0)); | ||
141 | jz_writef(CPM_CLKGR, OTG(1)); | ||
142 | } | ||
143 | |||
144 | void usb_dw_target_enable_irq(void) | ||
145 | { | ||
146 | system_enable_irq(IRQ_OTG); | ||
147 | } | ||
148 | |||
149 | void usb_dw_target_disable_irq(void) | ||
150 | { | ||
151 | system_disable_irq(IRQ_OTG); | ||
152 | } | ||
153 | |||
154 | void usb_dw_target_clear_irq(void) | ||
155 | { | ||
156 | } | ||
157 | |||
158 | /* | ||
159 | * Rockbox API | ||
160 | */ | ||
161 | |||
162 | #ifdef USB_STATUS_BY_EVENT | ||
163 | static volatile int usb_status = USB_EXTRACTED; | ||
164 | #endif | ||
165 | |||
166 | static int __usb_detect(void) | ||
167 | { | ||
168 | if(REG_GPIO_PIN(USB_DETECT_PORT) & USB_DETECT_PIN) | ||
169 | return USB_INSERTED; | ||
170 | else | ||
171 | return USB_EXTRACTED; | ||
172 | } | ||
173 | |||
174 | void usb_enable(bool on) | ||
175 | { | ||
176 | if(on) | ||
177 | usb_core_init(); | ||
178 | else | ||
179 | usb_core_exit(); | ||
180 | } | ||
181 | |||
182 | void usb_init_device(void) | ||
183 | { | ||
184 | /* Disable drvvbus pin -- it is only used when acting as a host, | ||
185 | * which Rockbox does not support */ | ||
186 | gpio_config(USB_DRVVBUS_PORT, USB_DRVVBUS_PIN, GPIO_OUTPUT(0)); | ||
187 | |||
188 | /* Power up the core clocks to allow writing | ||
189 | to some registers needed to power it down */ | ||
190 | usb_dw_target_disable_irq(); | ||
191 | usb_dw_target_enable_clocks(); | ||
192 | usb_drv_exit(); | ||
193 | |||
194 | #ifdef USB_STATUS_BY_EVENT | ||
195 | /* Setup USB detect pin IRQ */ | ||
196 | usb_status = __usb_detect(); | ||
197 | int level = (REG_GPIO_PIN(USB_DETECT_PORT) & USB_DETECT_PIN) ? 1 : 0; | ||
198 | gpio_config(USB_DETECT_PORT, USB_DETECT_PIN, GPIO_IRQ_EDGE(level ? 0 : 1)); | ||
199 | gpio_enable_irq(USB_DETECT_PORT, USB_DETECT_PIN); | ||
200 | #endif | ||
201 | } | ||
202 | |||
203 | #ifndef USB_STATUS_BY_EVENT | ||
204 | int usb_detect(void) | ||
205 | { | ||
206 | return __usb_detect(); | ||
207 | } | ||
208 | #else | ||
209 | int usb_detect(void) | ||
210 | { | ||
211 | return usb_status; | ||
212 | } | ||
213 | |||
214 | void USB_DETECT_PIN_INT(void) | ||
215 | { | ||
216 | /* Update status and flip the IRQ trigger edge */ | ||
217 | usb_status = __usb_detect(); | ||
218 | REG_GPIO_PAT0(USB_DETECT_PORT) ^= USB_DETECT_PIN; | ||
219 | |||
220 | /* Notify Rockbox of event */ | ||
221 | usb_status_event(usb_status); | ||
222 | } | ||
223 | #endif | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/cpm.h b/firmware/target/mips/ingenic_x1000/x1000/cpm.h index 752d270f20..8c5d74b2e9 100644 --- a/firmware/target/mips/ingenic_x1000/x1000/cpm.h +++ b/firmware/target/mips/ingenic_x1000/x1000/cpm.h | |||
@@ -401,6 +401,51 @@ | |||
401 | #define BF_CPM_MSC1CDR_S_CLK1_SEL_V(e) BF_CPM_MSC1CDR_S_CLK1_SEL(BV_CPM_MSC1CDR_S_CLK1_SEL__##e) | 401 | #define BF_CPM_MSC1CDR_S_CLK1_SEL_V(e) BF_CPM_MSC1CDR_S_CLK1_SEL(BV_CPM_MSC1CDR_S_CLK1_SEL__##e) |
402 | #define BFM_CPM_MSC1CDR_S_CLK1_SEL_V(v) BM_CPM_MSC1CDR_S_CLK1_SEL | 402 | #define BFM_CPM_MSC1CDR_S_CLK1_SEL_V(v) BM_CPM_MSC1CDR_S_CLK1_SEL |
403 | 403 | ||
404 | #define REG_CPM_USBCDR jz_reg(CPM_USBCDR) | ||
405 | #define JA_CPM_USBCDR (0xb0000000 + 0x50) | ||
406 | #define JT_CPM_USBCDR JIO_32_RW | ||
407 | #define JN_CPM_USBCDR CPM_USBCDR | ||
408 | #define JI_CPM_USBCDR | ||
409 | #define BP_CPM_USBCDR_CLKSRC 30 | ||
410 | #define BM_CPM_USBCDR_CLKSRC 0xc0000000 | ||
411 | #define BV_CPM_USBCDR_CLKSRC__EXCLK 0x0 | ||
412 | #define BV_CPM_USBCDR_CLKSRC__SCLK_A 0x2 | ||
413 | #define BV_CPM_USBCDR_CLKSRC__MPLL 0x3 | ||
414 | #define BF_CPM_USBCDR_CLKSRC(v) (((v) & 0x3) << 30) | ||
415 | #define BFM_CPM_USBCDR_CLKSRC(v) BM_CPM_USBCDR_CLKSRC | ||
416 | #define BF_CPM_USBCDR_CLKSRC_V(e) BF_CPM_USBCDR_CLKSRC(BV_CPM_USBCDR_CLKSRC__##e) | ||
417 | #define BFM_CPM_USBCDR_CLKSRC_V(v) BM_CPM_USBCDR_CLKSRC | ||
418 | #define BP_CPM_USBCDR_CLKDIV 0 | ||
419 | #define BM_CPM_USBCDR_CLKDIV 0xff | ||
420 | #define BF_CPM_USBCDR_CLKDIV(v) (((v) & 0xff) << 0) | ||
421 | #define BFM_CPM_USBCDR_CLKDIV(v) BM_CPM_USBCDR_CLKDIV | ||
422 | #define BF_CPM_USBCDR_CLKDIV_V(e) BF_CPM_USBCDR_CLKDIV(BV_CPM_USBCDR_CLKDIV__##e) | ||
423 | #define BFM_CPM_USBCDR_CLKDIV_V(v) BM_CPM_USBCDR_CLKDIV | ||
424 | #define BP_CPM_USBCDR_CE 29 | ||
425 | #define BM_CPM_USBCDR_CE 0x20000000 | ||
426 | #define BF_CPM_USBCDR_CE(v) (((v) & 0x1) << 29) | ||
427 | #define BFM_CPM_USBCDR_CE(v) BM_CPM_USBCDR_CE | ||
428 | #define BF_CPM_USBCDR_CE_V(e) BF_CPM_USBCDR_CE(BV_CPM_USBCDR_CE__##e) | ||
429 | #define BFM_CPM_USBCDR_CE_V(v) BM_CPM_USBCDR_CE | ||
430 | #define BP_CPM_USBCDR_BUSY 28 | ||
431 | #define BM_CPM_USBCDR_BUSY 0x10000000 | ||
432 | #define BF_CPM_USBCDR_BUSY(v) (((v) & 0x1) << 28) | ||
433 | #define BFM_CPM_USBCDR_BUSY(v) BM_CPM_USBCDR_BUSY | ||
434 | #define BF_CPM_USBCDR_BUSY_V(e) BF_CPM_USBCDR_BUSY(BV_CPM_USBCDR_BUSY__##e) | ||
435 | #define BFM_CPM_USBCDR_BUSY_V(v) BM_CPM_USBCDR_BUSY | ||
436 | #define BP_CPM_USBCDR_STOP 27 | ||
437 | #define BM_CPM_USBCDR_STOP 0x8000000 | ||
438 | #define BF_CPM_USBCDR_STOP(v) (((v) & 0x1) << 27) | ||
439 | #define BFM_CPM_USBCDR_STOP(v) BM_CPM_USBCDR_STOP | ||
440 | #define BF_CPM_USBCDR_STOP_V(e) BF_CPM_USBCDR_STOP(BV_CPM_USBCDR_STOP__##e) | ||
441 | #define BFM_CPM_USBCDR_STOP_V(v) BM_CPM_USBCDR_STOP | ||
442 | #define BP_CPM_USBCDR_PHY_GATE 26 | ||
443 | #define BM_CPM_USBCDR_PHY_GATE 0x4000000 | ||
444 | #define BF_CPM_USBCDR_PHY_GATE(v) (((v) & 0x1) << 26) | ||
445 | #define BFM_CPM_USBCDR_PHY_GATE(v) BM_CPM_USBCDR_PHY_GATE | ||
446 | #define BF_CPM_USBCDR_PHY_GATE_V(e) BF_CPM_USBCDR_PHY_GATE(BV_CPM_USBCDR_PHY_GATE__##e) | ||
447 | #define BFM_CPM_USBCDR_PHY_GATE_V(v) BM_CPM_USBCDR_PHY_GATE | ||
448 | |||
404 | #define REG_CPM_SSICDR jz_reg(CPM_SSICDR) | 449 | #define REG_CPM_SSICDR jz_reg(CPM_SSICDR) |
405 | #define JA_CPM_SSICDR (0xb0000000 + 0x74) | 450 | #define JA_CPM_SSICDR (0xb0000000 + 0x74) |
406 | #define JT_CPM_SSICDR JIO_32_RW | 451 | #define JT_CPM_SSICDR JIO_32_RW |
@@ -447,12 +492,265 @@ | |||
447 | #define BF_CPM_SSICDR_STOP_V(e) BF_CPM_SSICDR_STOP(BV_CPM_SSICDR_STOP__##e) | 492 | #define BF_CPM_SSICDR_STOP_V(e) BF_CPM_SSICDR_STOP(BV_CPM_SSICDR_STOP__##e) |
448 | #define BFM_CPM_SSICDR_STOP_V(v) BM_CPM_SSICDR_STOP | 493 | #define BFM_CPM_SSICDR_STOP_V(v) BM_CPM_SSICDR_STOP |
449 | 494 | ||
495 | #define REG_CPM_INTR jz_reg(CPM_INTR) | ||
496 | #define JA_CPM_INTR (0xb0000000 + 0xb0) | ||
497 | #define JT_CPM_INTR JIO_32_RW | ||
498 | #define JN_CPM_INTR CPM_INTR | ||
499 | #define JI_CPM_INTR | ||
500 | #define BP_CPM_INTR_VBUS 1 | ||
501 | #define BM_CPM_INTR_VBUS 0x2 | ||
502 | #define BF_CPM_INTR_VBUS(v) (((v) & 0x1) << 1) | ||
503 | #define BFM_CPM_INTR_VBUS(v) BM_CPM_INTR_VBUS | ||
504 | #define BF_CPM_INTR_VBUS_V(e) BF_CPM_INTR_VBUS(BV_CPM_INTR_VBUS__##e) | ||
505 | #define BFM_CPM_INTR_VBUS_V(v) BM_CPM_INTR_VBUS | ||
506 | #define BP_CPM_INTR_ADEV 0 | ||
507 | #define BM_CPM_INTR_ADEV 0x1 | ||
508 | #define BF_CPM_INTR_ADEV(v) (((v) & 0x1) << 0) | ||
509 | #define BFM_CPM_INTR_ADEV(v) BM_CPM_INTR_ADEV | ||
510 | #define BF_CPM_INTR_ADEV_V(e) BF_CPM_INTR_ADEV(BV_CPM_INTR_ADEV__##e) | ||
511 | #define BFM_CPM_INTR_ADEV_V(v) BM_CPM_INTR_ADEV | ||
512 | |||
513 | #define REG_CPM_INTR_EN jz_reg(CPM_INTR_EN) | ||
514 | #define JA_CPM_INTR_EN (0xb0000000 + 0xb4) | ||
515 | #define JT_CPM_INTR_EN JIO_32_RW | ||
516 | #define JN_CPM_INTR_EN CPM_INTR_EN | ||
517 | #define JI_CPM_INTR_EN | ||
518 | #define BP_CPM_INTR_EN_VBUS 1 | ||
519 | #define BM_CPM_INTR_EN_VBUS 0x2 | ||
520 | #define BF_CPM_INTR_EN_VBUS(v) (((v) & 0x1) << 1) | ||
521 | #define BFM_CPM_INTR_EN_VBUS(v) BM_CPM_INTR_EN_VBUS | ||
522 | #define BF_CPM_INTR_EN_VBUS_V(e) BF_CPM_INTR_EN_VBUS(BV_CPM_INTR_EN_VBUS__##e) | ||
523 | #define BFM_CPM_INTR_EN_VBUS_V(v) BM_CPM_INTR_EN_VBUS | ||
524 | #define BP_CPM_INTR_EN_ADEV 0 | ||
525 | #define BM_CPM_INTR_EN_ADEV 0x1 | ||
526 | #define BF_CPM_INTR_EN_ADEV(v) (((v) & 0x1) << 0) | ||
527 | #define BFM_CPM_INTR_EN_ADEV(v) BM_CPM_INTR_EN_ADEV | ||
528 | #define BF_CPM_INTR_EN_ADEV_V(e) BF_CPM_INTR_EN_ADEV(BV_CPM_INTR_EN_ADEV__##e) | ||
529 | #define BFM_CPM_INTR_EN_ADEV_V(v) BM_CPM_INTR_EN_ADEV | ||
530 | |||
450 | #define REG_CPM_DRCG jz_reg(CPM_DRCG) | 531 | #define REG_CPM_DRCG jz_reg(CPM_DRCG) |
451 | #define JA_CPM_DRCG (0xb0000000 + 0xd0) | 532 | #define JA_CPM_DRCG (0xb0000000 + 0xd0) |
452 | #define JT_CPM_DRCG JIO_32_RW | 533 | #define JT_CPM_DRCG JIO_32_RW |
453 | #define JN_CPM_DRCG CPM_DRCG | 534 | #define JN_CPM_DRCG CPM_DRCG |
454 | #define JI_CPM_DRCG | 535 | #define JI_CPM_DRCG |
455 | 536 | ||
537 | #define REG_CPM_USBPCR jz_reg(CPM_USBPCR) | ||
538 | #define JA_CPM_USBPCR (0xb0000000 + 0x3c) | ||
539 | #define JT_CPM_USBPCR JIO_32_RW | ||
540 | #define JN_CPM_USBPCR CPM_USBPCR | ||
541 | #define JI_CPM_USBPCR | ||
542 | #define BP_CPM_USBPCR_IDPULLUP_MASK 28 | ||
543 | #define BM_CPM_USBPCR_IDPULLUP_MASK 0x30000000 | ||
544 | #define BV_CPM_USBPCR_IDPULLUP_MASK__ALWAYS 0x2 | ||
545 | #define BV_CPM_USBPCR_IDPULLUP_MASK__ALWAYS_SUSPEND 0x1 | ||
546 | #define BV_CPM_USBPCR_IDPULLUP_MASK__FROM_OTG 0x0 | ||
547 | #define BF_CPM_USBPCR_IDPULLUP_MASK(v) (((v) & 0x3) << 28) | ||
548 | #define BFM_CPM_USBPCR_IDPULLUP_MASK(v) BM_CPM_USBPCR_IDPULLUP_MASK | ||
549 | #define BF_CPM_USBPCR_IDPULLUP_MASK_V(e) BF_CPM_USBPCR_IDPULLUP_MASK(BV_CPM_USBPCR_IDPULLUP_MASK__##e) | ||
550 | #define BFM_CPM_USBPCR_IDPULLUP_MASK_V(v) BM_CPM_USBPCR_IDPULLUP_MASK | ||
551 | #define BP_CPM_USBPCR_COMPDISTUNE 17 | ||
552 | #define BM_CPM_USBPCR_COMPDISTUNE 0xe0000 | ||
553 | #define BF_CPM_USBPCR_COMPDISTUNE(v) (((v) & 0x7) << 17) | ||
554 | #define BFM_CPM_USBPCR_COMPDISTUNE(v) BM_CPM_USBPCR_COMPDISTUNE | ||
555 | #define BF_CPM_USBPCR_COMPDISTUNE_V(e) BF_CPM_USBPCR_COMPDISTUNE(BV_CPM_USBPCR_COMPDISTUNE__##e) | ||
556 | #define BFM_CPM_USBPCR_COMPDISTUNE_V(v) BM_CPM_USBPCR_COMPDISTUNE | ||
557 | #define BP_CPM_USBPCR_OTGTUNE 14 | ||
558 | #define BM_CPM_USBPCR_OTGTUNE 0x1c000 | ||
559 | #define BF_CPM_USBPCR_OTGTUNE(v) (((v) & 0x7) << 14) | ||
560 | #define BFM_CPM_USBPCR_OTGTUNE(v) BM_CPM_USBPCR_OTGTUNE | ||
561 | #define BF_CPM_USBPCR_OTGTUNE_V(e) BF_CPM_USBPCR_OTGTUNE(BV_CPM_USBPCR_OTGTUNE__##e) | ||
562 | #define BFM_CPM_USBPCR_OTGTUNE_V(v) BM_CPM_USBPCR_OTGTUNE | ||
563 | #define BP_CPM_USBPCR_SQRXTUNE 11 | ||
564 | #define BM_CPM_USBPCR_SQRXTUNE 0x3800 | ||
565 | #define BF_CPM_USBPCR_SQRXTUNE(v) (((v) & 0x7) << 11) | ||
566 | #define BFM_CPM_USBPCR_SQRXTUNE(v) BM_CPM_USBPCR_SQRXTUNE | ||
567 | #define BF_CPM_USBPCR_SQRXTUNE_V(e) BF_CPM_USBPCR_SQRXTUNE(BV_CPM_USBPCR_SQRXTUNE__##e) | ||
568 | #define BFM_CPM_USBPCR_SQRXTUNE_V(v) BM_CPM_USBPCR_SQRXTUNE | ||
569 | #define BP_CPM_USBPCR_TXFSLSTUNE 7 | ||
570 | #define BM_CPM_USBPCR_TXFSLSTUNE 0x780 | ||
571 | #define BF_CPM_USBPCR_TXFSLSTUNE(v) (((v) & 0xf) << 7) | ||
572 | #define BFM_CPM_USBPCR_TXFSLSTUNE(v) BM_CPM_USBPCR_TXFSLSTUNE | ||
573 | #define BF_CPM_USBPCR_TXFSLSTUNE_V(e) BF_CPM_USBPCR_TXFSLSTUNE(BV_CPM_USBPCR_TXFSLSTUNE__##e) | ||
574 | #define BFM_CPM_USBPCR_TXFSLSTUNE_V(v) BM_CPM_USBPCR_TXFSLSTUNE | ||
575 | #define BP_CPM_USBPCR_TXHSXVTUNE 4 | ||
576 | #define BM_CPM_USBPCR_TXHSXVTUNE 0x30 | ||
577 | #define BF_CPM_USBPCR_TXHSXVTUNE(v) (((v) & 0x3) << 4) | ||
578 | #define BFM_CPM_USBPCR_TXHSXVTUNE(v) BM_CPM_USBPCR_TXHSXVTUNE | ||
579 | #define BF_CPM_USBPCR_TXHSXVTUNE_V(e) BF_CPM_USBPCR_TXHSXVTUNE(BV_CPM_USBPCR_TXHSXVTUNE__##e) | ||
580 | #define BFM_CPM_USBPCR_TXHSXVTUNE_V(v) BM_CPM_USBPCR_TXHSXVTUNE | ||
581 | #define BP_CPM_USBPCR_TXVREFTUNE 0 | ||
582 | #define BM_CPM_USBPCR_TXVREFTUNE 0xf | ||
583 | #define BF_CPM_USBPCR_TXVREFTUNE(v) (((v) & 0xf) << 0) | ||
584 | #define BFM_CPM_USBPCR_TXVREFTUNE(v) BM_CPM_USBPCR_TXVREFTUNE | ||
585 | #define BF_CPM_USBPCR_TXVREFTUNE_V(e) BF_CPM_USBPCR_TXVREFTUNE(BV_CPM_USBPCR_TXVREFTUNE__##e) | ||
586 | #define BFM_CPM_USBPCR_TXVREFTUNE_V(v) BM_CPM_USBPCR_TXVREFTUNE | ||
587 | #define BP_CPM_USBPCR_USB_MODE 31 | ||
588 | #define BM_CPM_USBPCR_USB_MODE 0x80000000 | ||
589 | #define BV_CPM_USBPCR_USB_MODE__USB 0x0 | ||
590 | #define BV_CPM_USBPCR_USB_MODE__OTG 0x1 | ||
591 | #define BF_CPM_USBPCR_USB_MODE(v) (((v) & 0x1) << 31) | ||
592 | #define BFM_CPM_USBPCR_USB_MODE(v) BM_CPM_USBPCR_USB_MODE | ||
593 | #define BF_CPM_USBPCR_USB_MODE_V(e) BF_CPM_USBPCR_USB_MODE(BV_CPM_USBPCR_USB_MODE__##e) | ||
594 | #define BFM_CPM_USBPCR_USB_MODE_V(v) BM_CPM_USBPCR_USB_MODE | ||
595 | #define BP_CPM_USBPCR_AVLD_REG 30 | ||
596 | #define BM_CPM_USBPCR_AVLD_REG 0x40000000 | ||
597 | #define BF_CPM_USBPCR_AVLD_REG(v) (((v) & 0x1) << 30) | ||
598 | #define BFM_CPM_USBPCR_AVLD_REG(v) BM_CPM_USBPCR_AVLD_REG | ||
599 | #define BF_CPM_USBPCR_AVLD_REG_V(e) BF_CPM_USBPCR_AVLD_REG(BV_CPM_USBPCR_AVLD_REG__##e) | ||
600 | #define BFM_CPM_USBPCR_AVLD_REG_V(v) BM_CPM_USBPCR_AVLD_REG | ||
601 | #define BP_CPM_USBPCR_INCR_MASK 27 | ||
602 | #define BM_CPM_USBPCR_INCR_MASK 0x8000000 | ||
603 | #define BF_CPM_USBPCR_INCR_MASK(v) (((v) & 0x1) << 27) | ||
604 | #define BFM_CPM_USBPCR_INCR_MASK(v) BM_CPM_USBPCR_INCR_MASK | ||
605 | #define BF_CPM_USBPCR_INCR_MASK_V(e) BF_CPM_USBPCR_INCR_MASK(BV_CPM_USBPCR_INCR_MASK__##e) | ||
606 | #define BFM_CPM_USBPCR_INCR_MASK_V(v) BM_CPM_USBPCR_INCR_MASK | ||
607 | #define BP_CPM_USBPCR_TXRISETUNE 26 | ||
608 | #define BM_CPM_USBPCR_TXRISETUNE 0x4000000 | ||
609 | #define BF_CPM_USBPCR_TXRISETUNE(v) (((v) & 0x1) << 26) | ||
610 | #define BFM_CPM_USBPCR_TXRISETUNE(v) BM_CPM_USBPCR_TXRISETUNE | ||
611 | #define BF_CPM_USBPCR_TXRISETUNE_V(e) BF_CPM_USBPCR_TXRISETUNE(BV_CPM_USBPCR_TXRISETUNE__##e) | ||
612 | #define BFM_CPM_USBPCR_TXRISETUNE_V(v) BM_CPM_USBPCR_TXRISETUNE | ||
613 | #define BP_CPM_USBPCR_COMMONONN 25 | ||
614 | #define BM_CPM_USBPCR_COMMONONN 0x2000000 | ||
615 | #define BF_CPM_USBPCR_COMMONONN(v) (((v) & 0x1) << 25) | ||
616 | #define BFM_CPM_USBPCR_COMMONONN(v) BM_CPM_USBPCR_COMMONONN | ||
617 | #define BF_CPM_USBPCR_COMMONONN_V(e) BF_CPM_USBPCR_COMMONONN(BV_CPM_USBPCR_COMMONONN__##e) | ||
618 | #define BFM_CPM_USBPCR_COMMONONN_V(v) BM_CPM_USBPCR_COMMONONN | ||
619 | #define BP_CPM_USBPCR_VBUSVLDEXT 24 | ||
620 | #define BM_CPM_USBPCR_VBUSVLDEXT 0x1000000 | ||
621 | #define BF_CPM_USBPCR_VBUSVLDEXT(v) (((v) & 0x1) << 24) | ||
622 | #define BFM_CPM_USBPCR_VBUSVLDEXT(v) BM_CPM_USBPCR_VBUSVLDEXT | ||
623 | #define BF_CPM_USBPCR_VBUSVLDEXT_V(e) BF_CPM_USBPCR_VBUSVLDEXT(BV_CPM_USBPCR_VBUSVLDEXT__##e) | ||
624 | #define BFM_CPM_USBPCR_VBUSVLDEXT_V(v) BM_CPM_USBPCR_VBUSVLDEXT | ||
625 | #define BP_CPM_USBPCR_VBUSVLDEXTSEL 23 | ||
626 | #define BM_CPM_USBPCR_VBUSVLDEXTSEL 0x800000 | ||
627 | #define BF_CPM_USBPCR_VBUSVLDEXTSEL(v) (((v) & 0x1) << 23) | ||
628 | #define BFM_CPM_USBPCR_VBUSVLDEXTSEL(v) BM_CPM_USBPCR_VBUSVLDEXTSEL | ||
629 | #define BF_CPM_USBPCR_VBUSVLDEXTSEL_V(e) BF_CPM_USBPCR_VBUSVLDEXTSEL(BV_CPM_USBPCR_VBUSVLDEXTSEL__##e) | ||
630 | #define BFM_CPM_USBPCR_VBUSVLDEXTSEL_V(v) BM_CPM_USBPCR_VBUSVLDEXTSEL | ||
631 | #define BP_CPM_USBPCR_POR 22 | ||
632 | #define BM_CPM_USBPCR_POR 0x400000 | ||
633 | #define BF_CPM_USBPCR_POR(v) (((v) & 0x1) << 22) | ||
634 | #define BFM_CPM_USBPCR_POR(v) BM_CPM_USBPCR_POR | ||
635 | #define BF_CPM_USBPCR_POR_V(e) BF_CPM_USBPCR_POR(BV_CPM_USBPCR_POR__##e) | ||
636 | #define BFM_CPM_USBPCR_POR_V(v) BM_CPM_USBPCR_POR | ||
637 | #define BP_CPM_USBPCR_SIDDQ 21 | ||
638 | #define BM_CPM_USBPCR_SIDDQ 0x200000 | ||
639 | #define BF_CPM_USBPCR_SIDDQ(v) (((v) & 0x1) << 21) | ||
640 | #define BFM_CPM_USBPCR_SIDDQ(v) BM_CPM_USBPCR_SIDDQ | ||
641 | #define BF_CPM_USBPCR_SIDDQ_V(e) BF_CPM_USBPCR_SIDDQ(BV_CPM_USBPCR_SIDDQ__##e) | ||
642 | #define BFM_CPM_USBPCR_SIDDQ_V(v) BM_CPM_USBPCR_SIDDQ | ||
643 | #define BP_CPM_USBPCR_OTG_DISABLE 20 | ||
644 | #define BM_CPM_USBPCR_OTG_DISABLE 0x100000 | ||
645 | #define BF_CPM_USBPCR_OTG_DISABLE(v) (((v) & 0x1) << 20) | ||
646 | #define BFM_CPM_USBPCR_OTG_DISABLE(v) BM_CPM_USBPCR_OTG_DISABLE | ||
647 | #define BF_CPM_USBPCR_OTG_DISABLE_V(e) BF_CPM_USBPCR_OTG_DISABLE(BV_CPM_USBPCR_OTG_DISABLE__##e) | ||
648 | #define BFM_CPM_USBPCR_OTG_DISABLE_V(v) BM_CPM_USBPCR_OTG_DISABLE | ||
649 | #define BP_CPM_USBPCR_TXPREEMPHTUNE 6 | ||
650 | #define BM_CPM_USBPCR_TXPREEMPHTUNE 0x40 | ||
651 | #define BF_CPM_USBPCR_TXPREEMPHTUNE(v) (((v) & 0x1) << 6) | ||
652 | #define BFM_CPM_USBPCR_TXPREEMPHTUNE(v) BM_CPM_USBPCR_TXPREEMPHTUNE | ||
653 | #define BF_CPM_USBPCR_TXPREEMPHTUNE_V(e) BF_CPM_USBPCR_TXPREEMPHTUNE(BV_CPM_USBPCR_TXPREEMPHTUNE__##e) | ||
654 | #define BFM_CPM_USBPCR_TXPREEMPHTUNE_V(v) BM_CPM_USBPCR_TXPREEMPHTUNE | ||
655 | |||
656 | #define REG_CPM_USBRDT jz_reg(CPM_USBRDT) | ||
657 | #define JA_CPM_USBRDT (0xb0000000 + 0x40) | ||
658 | #define JT_CPM_USBRDT JIO_32_RW | ||
659 | #define JN_CPM_USBRDT CPM_USBRDT | ||
660 | #define JI_CPM_USBRDT | ||
661 | #define BP_CPM_USBRDT_RDT 0 | ||
662 | #define BM_CPM_USBRDT_RDT 0x7fffff | ||
663 | #define BF_CPM_USBRDT_RDT(v) (((v) & 0x7fffff) << 0) | ||
664 | #define BFM_CPM_USBRDT_RDT(v) BM_CPM_USBRDT_RDT | ||
665 | #define BF_CPM_USBRDT_RDT_V(e) BF_CPM_USBRDT_RDT(BV_CPM_USBRDT_RDT__##e) | ||
666 | #define BFM_CPM_USBRDT_RDT_V(v) BM_CPM_USBRDT_RDT | ||
667 | #define BP_CPM_USBRDT_HB_MASK 26 | ||
668 | #define BM_CPM_USBRDT_HB_MASK 0x4000000 | ||
669 | #define BF_CPM_USBRDT_HB_MASK(v) (((v) & 0x1) << 26) | ||
670 | #define BFM_CPM_USBRDT_HB_MASK(v) BM_CPM_USBRDT_HB_MASK | ||
671 | #define BF_CPM_USBRDT_HB_MASK_V(e) BF_CPM_USBRDT_HB_MASK(BV_CPM_USBRDT_HB_MASK__##e) | ||
672 | #define BFM_CPM_USBRDT_HB_MASK_V(v) BM_CPM_USBRDT_HB_MASK | ||
673 | #define BP_CPM_USBRDT_VBFIL_LD_EN 25 | ||
674 | #define BM_CPM_USBRDT_VBFIL_LD_EN 0x2000000 | ||
675 | #define BF_CPM_USBRDT_VBFIL_LD_EN(v) (((v) & 0x1) << 25) | ||
676 | #define BFM_CPM_USBRDT_VBFIL_LD_EN(v) BM_CPM_USBRDT_VBFIL_LD_EN | ||
677 | #define BF_CPM_USBRDT_VBFIL_LD_EN_V(e) BF_CPM_USBRDT_VBFIL_LD_EN(BV_CPM_USBRDT_VBFIL_LD_EN__##e) | ||
678 | #define BFM_CPM_USBRDT_VBFIL_LD_EN_V(v) BM_CPM_USBRDT_VBFIL_LD_EN | ||
679 | #define BP_CPM_USBRDT_IDDIG_EN 24 | ||
680 | #define BM_CPM_USBRDT_IDDIG_EN 0x1000000 | ||
681 | #define BF_CPM_USBRDT_IDDIG_EN(v) (((v) & 0x1) << 24) | ||
682 | #define BFM_CPM_USBRDT_IDDIG_EN(v) BM_CPM_USBRDT_IDDIG_EN | ||
683 | #define BF_CPM_USBRDT_IDDIG_EN_V(e) BF_CPM_USBRDT_IDDIG_EN(BV_CPM_USBRDT_IDDIG_EN__##e) | ||
684 | #define BFM_CPM_USBRDT_IDDIG_EN_V(v) BM_CPM_USBRDT_IDDIG_EN | ||
685 | #define BP_CPM_USBRDT_IDDIG_REG 23 | ||
686 | #define BM_CPM_USBRDT_IDDIG_REG 0x800000 | ||
687 | #define BF_CPM_USBRDT_IDDIG_REG(v) (((v) & 0x1) << 23) | ||
688 | #define BFM_CPM_USBRDT_IDDIG_REG(v) BM_CPM_USBRDT_IDDIG_REG | ||
689 | #define BF_CPM_USBRDT_IDDIG_REG_V(e) BF_CPM_USBRDT_IDDIG_REG(BV_CPM_USBRDT_IDDIG_REG__##e) | ||
690 | #define BFM_CPM_USBRDT_IDDIG_REG_V(v) BM_CPM_USBRDT_IDDIG_REG | ||
691 | |||
692 | #define REG_CPM_USBVBFIL jz_reg(CPM_USBVBFIL) | ||
693 | #define JA_CPM_USBVBFIL (0xb0000000 + 0x44) | ||
694 | #define JT_CPM_USBVBFIL JIO_32_RW | ||
695 | #define JN_CPM_USBVBFIL CPM_USBVBFIL | ||
696 | #define JI_CPM_USBVBFIL | ||
697 | #define BP_CPM_USBVBFIL_IDDIGFIL 16 | ||
698 | #define BM_CPM_USBVBFIL_IDDIGFIL 0xffff0000 | ||
699 | #define BF_CPM_USBVBFIL_IDDIGFIL(v) (((v) & 0xffff) << 16) | ||
700 | #define BFM_CPM_USBVBFIL_IDDIGFIL(v) BM_CPM_USBVBFIL_IDDIGFIL | ||
701 | #define BF_CPM_USBVBFIL_IDDIGFIL_V(e) BF_CPM_USBVBFIL_IDDIGFIL(BV_CPM_USBVBFIL_IDDIGFIL__##e) | ||
702 | #define BFM_CPM_USBVBFIL_IDDIGFIL_V(v) BM_CPM_USBVBFIL_IDDIGFIL | ||
703 | #define BP_CPM_USBVBFIL_VBFIL 0 | ||
704 | #define BM_CPM_USBVBFIL_VBFIL 0xffff | ||
705 | #define BF_CPM_USBVBFIL_VBFIL(v) (((v) & 0xffff) << 0) | ||
706 | #define BFM_CPM_USBVBFIL_VBFIL(v) BM_CPM_USBVBFIL_VBFIL | ||
707 | #define BF_CPM_USBVBFIL_VBFIL_V(e) BF_CPM_USBVBFIL_VBFIL(BV_CPM_USBVBFIL_VBFIL__##e) | ||
708 | #define BFM_CPM_USBVBFIL_VBFIL_V(v) BM_CPM_USBVBFIL_VBFIL | ||
709 | |||
710 | #define REG_CPM_USBPCR1 jz_reg(CPM_USBPCR1) | ||
711 | #define JA_CPM_USBPCR1 (0xb0000000 + 0x48) | ||
712 | #define JT_CPM_USBPCR1 JIO_32_RW | ||
713 | #define JN_CPM_USBPCR1 CPM_USBPCR1 | ||
714 | #define JI_CPM_USBPCR1 | ||
715 | #define BP_CPM_USBPCR1_REFCLK_SEL 26 | ||
716 | #define BM_CPM_USBPCR1_REFCLK_SEL 0xc000000 | ||
717 | #define BV_CPM_USBPCR1_REFCLK_SEL__CLKCORE 0x2 | ||
718 | #define BV_CPM_USBPCR1_REFCLK_SEL__EXTERNAL 0x1 | ||
719 | #define BV_CPM_USBPCR1_REFCLK_SEL__CRYSTAL 0x0 | ||
720 | #define BF_CPM_USBPCR1_REFCLK_SEL(v) (((v) & 0x3) << 26) | ||
721 | #define BFM_CPM_USBPCR1_REFCLK_SEL(v) BM_CPM_USBPCR1_REFCLK_SEL | ||
722 | #define BF_CPM_USBPCR1_REFCLK_SEL_V(e) BF_CPM_USBPCR1_REFCLK_SEL(BV_CPM_USBPCR1_REFCLK_SEL__##e) | ||
723 | #define BFM_CPM_USBPCR1_REFCLK_SEL_V(v) BM_CPM_USBPCR1_REFCLK_SEL | ||
724 | #define BP_CPM_USBPCR1_REFCLK_DIV 24 | ||
725 | #define BM_CPM_USBPCR1_REFCLK_DIV 0x3000000 | ||
726 | #define BV_CPM_USBPCR1_REFCLK_DIV__48MHZ 0x2 | ||
727 | #define BV_CPM_USBPCR1_REFCLK_DIV__24MHZ 0x1 | ||
728 | #define BV_CPM_USBPCR1_REFCLK_DIV__12MHZ 0x0 | ||
729 | #define BF_CPM_USBPCR1_REFCLK_DIV(v) (((v) & 0x3) << 24) | ||
730 | #define BFM_CPM_USBPCR1_REFCLK_DIV(v) BM_CPM_USBPCR1_REFCLK_DIV | ||
731 | #define BF_CPM_USBPCR1_REFCLK_DIV_V(e) BF_CPM_USBPCR1_REFCLK_DIV(BV_CPM_USBPCR1_REFCLK_DIV__##e) | ||
732 | #define BFM_CPM_USBPCR1_REFCLK_DIV_V(v) BM_CPM_USBPCR1_REFCLK_DIV | ||
733 | #define BP_CPM_USBPCR1_BVLD_REG 31 | ||
734 | #define BM_CPM_USBPCR1_BVLD_REG 0x80000000 | ||
735 | #define BF_CPM_USBPCR1_BVLD_REG(v) (((v) & 0x1) << 31) | ||
736 | #define BFM_CPM_USBPCR1_BVLD_REG(v) BM_CPM_USBPCR1_BVLD_REG | ||
737 | #define BF_CPM_USBPCR1_BVLD_REG_V(e) BF_CPM_USBPCR1_BVLD_REG(BV_CPM_USBPCR1_BVLD_REG__##e) | ||
738 | #define BFM_CPM_USBPCR1_BVLD_REG_V(v) BM_CPM_USBPCR1_BVLD_REG | ||
739 | #define BP_CPM_USBPCR1_PORT_RST 21 | ||
740 | #define BM_CPM_USBPCR1_PORT_RST 0x200000 | ||
741 | #define BF_CPM_USBPCR1_PORT_RST(v) (((v) & 0x1) << 21) | ||
742 | #define BFM_CPM_USBPCR1_PORT_RST(v) BM_CPM_USBPCR1_PORT_RST | ||
743 | #define BF_CPM_USBPCR1_PORT_RST_V(e) BF_CPM_USBPCR1_PORT_RST(BV_CPM_USBPCR1_PORT_RST__##e) | ||
744 | #define BFM_CPM_USBPCR1_PORT_RST_V(v) BM_CPM_USBPCR1_PORT_RST | ||
745 | #define BP_CPM_USBPCR1_WORD_IF 19 | ||
746 | #define BM_CPM_USBPCR1_WORD_IF 0x80000 | ||
747 | #define BV_CPM_USBPCR1_WORD_IF__16BIT 0x1 | ||
748 | #define BV_CPM_USBPCR1_WORD_IF__8BIT 0x0 | ||
749 | #define BF_CPM_USBPCR1_WORD_IF(v) (((v) & 0x1) << 19) | ||
750 | #define BFM_CPM_USBPCR1_WORD_IF(v) BM_CPM_USBPCR1_WORD_IF | ||
751 | #define BF_CPM_USBPCR1_WORD_IF_V(e) BF_CPM_USBPCR1_WORD_IF(BV_CPM_USBPCR1_WORD_IF__##e) | ||
752 | #define BFM_CPM_USBPCR1_WORD_IF_V(v) BM_CPM_USBPCR1_WORD_IF | ||
753 | |||
456 | #define REG_CPM_APCR jz_reg(CPM_APCR) | 754 | #define REG_CPM_APCR jz_reg(CPM_APCR) |
457 | #define JA_CPM_APCR (0xb0000000 + 0x10) | 755 | #define JA_CPM_APCR (0xb0000000 + 0x10) |
458 | #define JT_CPM_APCR JIO_32_RW | 756 | #define JT_CPM_APCR JIO_32_RW |
@@ -791,6 +1089,102 @@ | |||
791 | #define BF_CPM_CLKGR_EFUSE_V(e) BF_CPM_CLKGR_EFUSE(BV_CPM_CLKGR_EFUSE__##e) | 1089 | #define BF_CPM_CLKGR_EFUSE_V(e) BF_CPM_CLKGR_EFUSE(BV_CPM_CLKGR_EFUSE__##e) |
792 | #define BFM_CPM_CLKGR_EFUSE_V(v) BM_CPM_CLKGR_EFUSE | 1090 | #define BFM_CPM_CLKGR_EFUSE_V(v) BM_CPM_CLKGR_EFUSE |
793 | 1091 | ||
1092 | #define REG_CPM_SRBC jz_reg(CPM_SRBC) | ||
1093 | #define JA_CPM_SRBC (0xb0000000 + 0xc4) | ||
1094 | #define JT_CPM_SRBC JIO_32_RW | ||
1095 | #define JN_CPM_SRBC CPM_SRBC | ||
1096 | #define JI_CPM_SRBC | ||
1097 | #define BP_CPM_SRBC_JPEG_SR 31 | ||
1098 | #define BM_CPM_SRBC_JPEG_SR 0x80000000 | ||
1099 | #define BF_CPM_SRBC_JPEG_SR(v) (((v) & 0x1) << 31) | ||
1100 | #define BFM_CPM_SRBC_JPEG_SR(v) BM_CPM_SRBC_JPEG_SR | ||
1101 | #define BF_CPM_SRBC_JPEG_SR_V(e) BF_CPM_SRBC_JPEG_SR(BV_CPM_SRBC_JPEG_SR__##e) | ||
1102 | #define BFM_CPM_SRBC_JPEG_SR_V(v) BM_CPM_SRBC_JPEG_SR | ||
1103 | #define BP_CPM_SRBC_JPEG_STOP 30 | ||
1104 | #define BM_CPM_SRBC_JPEG_STOP 0x40000000 | ||
1105 | #define BF_CPM_SRBC_JPEG_STOP(v) (((v) & 0x1) << 30) | ||
1106 | #define BFM_CPM_SRBC_JPEG_STOP(v) BM_CPM_SRBC_JPEG_STOP | ||
1107 | #define BF_CPM_SRBC_JPEG_STOP_V(e) BF_CPM_SRBC_JPEG_STOP(BV_CPM_SRBC_JPEG_STOP__##e) | ||
1108 | #define BFM_CPM_SRBC_JPEG_STOP_V(v) BM_CPM_SRBC_JPEG_STOP | ||
1109 | #define BP_CPM_SRBC_JPEG_ACK 29 | ||
1110 | #define BM_CPM_SRBC_JPEG_ACK 0x20000000 | ||
1111 | #define BF_CPM_SRBC_JPEG_ACK(v) (((v) & 0x1) << 29) | ||
1112 | #define BFM_CPM_SRBC_JPEG_ACK(v) BM_CPM_SRBC_JPEG_ACK | ||
1113 | #define BF_CPM_SRBC_JPEG_ACK_V(e) BF_CPM_SRBC_JPEG_ACK(BV_CPM_SRBC_JPEG_ACK__##e) | ||
1114 | #define BFM_CPM_SRBC_JPEG_ACK_V(v) BM_CPM_SRBC_JPEG_ACK | ||
1115 | #define BP_CPM_SRBC_LCD_SR 25 | ||
1116 | #define BM_CPM_SRBC_LCD_SR 0x2000000 | ||
1117 | #define BF_CPM_SRBC_LCD_SR(v) (((v) & 0x1) << 25) | ||
1118 | #define BFM_CPM_SRBC_LCD_SR(v) BM_CPM_SRBC_LCD_SR | ||
1119 | #define BF_CPM_SRBC_LCD_SR_V(e) BF_CPM_SRBC_LCD_SR(BV_CPM_SRBC_LCD_SR__##e) | ||
1120 | #define BFM_CPM_SRBC_LCD_SR_V(v) BM_CPM_SRBC_LCD_SR | ||
1121 | #define BP_CPM_SRBC_LCD_STOP 24 | ||
1122 | #define BM_CPM_SRBC_LCD_STOP 0x1000000 | ||
1123 | #define BF_CPM_SRBC_LCD_STOP(v) (((v) & 0x1) << 24) | ||
1124 | #define BFM_CPM_SRBC_LCD_STOP(v) BM_CPM_SRBC_LCD_STOP | ||
1125 | #define BF_CPM_SRBC_LCD_STOP_V(e) BF_CPM_SRBC_LCD_STOP(BV_CPM_SRBC_LCD_STOP__##e) | ||
1126 | #define BFM_CPM_SRBC_LCD_STOP_V(v) BM_CPM_SRBC_LCD_STOP | ||
1127 | #define BP_CPM_SRBC_LCD_ACK 23 | ||
1128 | #define BM_CPM_SRBC_LCD_ACK 0x800000 | ||
1129 | #define BF_CPM_SRBC_LCD_ACK(v) (((v) & 0x1) << 23) | ||
1130 | #define BFM_CPM_SRBC_LCD_ACK(v) BM_CPM_SRBC_LCD_ACK | ||
1131 | #define BF_CPM_SRBC_LCD_ACK_V(e) BF_CPM_SRBC_LCD_ACK(BV_CPM_SRBC_LCD_ACK__##e) | ||
1132 | #define BFM_CPM_SRBC_LCD_ACK_V(v) BM_CPM_SRBC_LCD_ACK | ||
1133 | #define BP_CPM_SRBC_CIM_STOP 21 | ||
1134 | #define BM_CPM_SRBC_CIM_STOP 0x200000 | ||
1135 | #define BF_CPM_SRBC_CIM_STOP(v) (((v) & 0x1) << 21) | ||
1136 | #define BFM_CPM_SRBC_CIM_STOP(v) BM_CPM_SRBC_CIM_STOP | ||
1137 | #define BF_CPM_SRBC_CIM_STOP_V(e) BF_CPM_SRBC_CIM_STOP(BV_CPM_SRBC_CIM_STOP__##e) | ||
1138 | #define BFM_CPM_SRBC_CIM_STOP_V(v) BM_CPM_SRBC_CIM_STOP | ||
1139 | #define BP_CPM_SRBC_CIM_ACK 20 | ||
1140 | #define BM_CPM_SRBC_CIM_ACK 0x100000 | ||
1141 | #define BF_CPM_SRBC_CIM_ACK(v) (((v) & 0x1) << 20) | ||
1142 | #define BFM_CPM_SRBC_CIM_ACK(v) BM_CPM_SRBC_CIM_ACK | ||
1143 | #define BF_CPM_SRBC_CIM_ACK_V(e) BF_CPM_SRBC_CIM_ACK(BV_CPM_SRBC_CIM_ACK__##e) | ||
1144 | #define BFM_CPM_SRBC_CIM_ACK_V(v) BM_CPM_SRBC_CIM_ACK | ||
1145 | #define BP_CPM_SRBC_CPU_STOP 15 | ||
1146 | #define BM_CPM_SRBC_CPU_STOP 0x8000 | ||
1147 | #define BF_CPM_SRBC_CPU_STOP(v) (((v) & 0x1) << 15) | ||
1148 | #define BFM_CPM_SRBC_CPU_STOP(v) BM_CPM_SRBC_CPU_STOP | ||
1149 | #define BF_CPM_SRBC_CPU_STOP_V(e) BF_CPM_SRBC_CPU_STOP(BV_CPM_SRBC_CPU_STOP__##e) | ||
1150 | #define BFM_CPM_SRBC_CPU_STOP_V(v) BM_CPM_SRBC_CPU_STOP | ||
1151 | #define BP_CPM_SRBC_CPU_ACK 14 | ||
1152 | #define BM_CPM_SRBC_CPU_ACK 0x4000 | ||
1153 | #define BF_CPM_SRBC_CPU_ACK(v) (((v) & 0x1) << 14) | ||
1154 | #define BFM_CPM_SRBC_CPU_ACK(v) BM_CPM_SRBC_CPU_ACK | ||
1155 | #define BF_CPM_SRBC_CPU_ACK_V(e) BF_CPM_SRBC_CPU_ACK(BV_CPM_SRBC_CPU_ACK__##e) | ||
1156 | #define BFM_CPM_SRBC_CPU_ACK_V(v) BM_CPM_SRBC_CPU_ACK | ||
1157 | #define BP_CPM_SRBC_OTG_SR 12 | ||
1158 | #define BM_CPM_SRBC_OTG_SR 0x1000 | ||
1159 | #define BF_CPM_SRBC_OTG_SR(v) (((v) & 0x1) << 12) | ||
1160 | #define BFM_CPM_SRBC_OTG_SR(v) BM_CPM_SRBC_OTG_SR | ||
1161 | #define BF_CPM_SRBC_OTG_SR_V(e) BF_CPM_SRBC_OTG_SR(BV_CPM_SRBC_OTG_SR__##e) | ||
1162 | #define BFM_CPM_SRBC_OTG_SR_V(v) BM_CPM_SRBC_OTG_SR | ||
1163 | #define BP_CPM_SRBC_AHB2_STOP 8 | ||
1164 | #define BM_CPM_SRBC_AHB2_STOP 0x100 | ||
1165 | #define BF_CPM_SRBC_AHB2_STOP(v) (((v) & 0x1) << 8) | ||
1166 | #define BFM_CPM_SRBC_AHB2_STOP(v) BM_CPM_SRBC_AHB2_STOP | ||
1167 | #define BF_CPM_SRBC_AHB2_STOP_V(e) BF_CPM_SRBC_AHB2_STOP(BV_CPM_SRBC_AHB2_STOP__##e) | ||
1168 | #define BFM_CPM_SRBC_AHB2_STOP_V(v) BM_CPM_SRBC_AHB2_STOP | ||
1169 | #define BP_CPM_SRBC_AHB2_ACK 7 | ||
1170 | #define BM_CPM_SRBC_AHB2_ACK 0x80 | ||
1171 | #define BF_CPM_SRBC_AHB2_ACK(v) (((v) & 0x1) << 7) | ||
1172 | #define BFM_CPM_SRBC_AHB2_ACK(v) BM_CPM_SRBC_AHB2_ACK | ||
1173 | #define BF_CPM_SRBC_AHB2_ACK_V(e) BF_CPM_SRBC_AHB2_ACK(BV_CPM_SRBC_AHB2_ACK__##e) | ||
1174 | #define BFM_CPM_SRBC_AHB2_ACK_V(v) BM_CPM_SRBC_AHB2_ACK | ||
1175 | #define BP_CPM_SRBC_DDR_STOP 6 | ||
1176 | #define BM_CPM_SRBC_DDR_STOP 0x40 | ||
1177 | #define BF_CPM_SRBC_DDR_STOP(v) (((v) & 0x1) << 6) | ||
1178 | #define BFM_CPM_SRBC_DDR_STOP(v) BM_CPM_SRBC_DDR_STOP | ||
1179 | #define BF_CPM_SRBC_DDR_STOP_V(e) BF_CPM_SRBC_DDR_STOP(BV_CPM_SRBC_DDR_STOP__##e) | ||
1180 | #define BFM_CPM_SRBC_DDR_STOP_V(v) BM_CPM_SRBC_DDR_STOP | ||
1181 | #define BP_CPM_SRBC_DDR_ACK 5 | ||
1182 | #define BM_CPM_SRBC_DDR_ACK 0x20 | ||
1183 | #define BF_CPM_SRBC_DDR_ACK(v) (((v) & 0x1) << 5) | ||
1184 | #define BFM_CPM_SRBC_DDR_ACK(v) BM_CPM_SRBC_DDR_ACK | ||
1185 | #define BF_CPM_SRBC_DDR_ACK_V(e) BF_CPM_SRBC_DDR_ACK(BV_CPM_SRBC_DDR_ACK__##e) | ||
1186 | #define BFM_CPM_SRBC_DDR_ACK_V(v) BM_CPM_SRBC_DDR_ACK | ||
1187 | |||
794 | #define REG_CPM_OPCR jz_reg(CPM_OPCR) | 1188 | #define REG_CPM_OPCR jz_reg(CPM_OPCR) |
795 | #define JA_CPM_OPCR (0xb0000000 + 0x24) | 1189 | #define JA_CPM_OPCR (0xb0000000 + 0x24) |
796 | #define JT_CPM_OPCR JIO_32_RW | 1190 | #define JT_CPM_OPCR JIO_32_RW |