diff options
Diffstat (limited to 'firmware/target')
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c | 104 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/ata-nand-jz4760.c | 88 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/dma_acc-jz4740.c | 30 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c | 60 | ||||
-rw-r--r-- | firmware/target/mips/mmu-mips.c | 12 |
5 files changed, 147 insertions, 147 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c b/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c index 1ae3bb2cc8..a582db82cc 100644 --- a/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c | |||
@@ -149,20 +149,20 @@ static inline void jz_nand_read_buf8(void *buf, int count) | |||
149 | static void jz_nand_write_dma(void *source, unsigned int len, int bw) | 149 | static void jz_nand_write_dma(void *source, unsigned int len, int bw) |
150 | { | 150 | { |
151 | mutex_lock(&nand_dma_mtx); | 151 | mutex_lock(&nand_dma_mtx); |
152 | 152 | ||
153 | if(((unsigned int)source < 0xa0000000) && len) | 153 | if(((unsigned int)source < 0xa0000000) && len) |
154 | dma_cache_wback_inv((unsigned long)source, len); | 154 | dma_cache_wback_inv((unsigned long)source, len); |
155 | 155 | ||
156 | dma_enable(); | 156 | dma_enable(); |
157 | 157 | ||
158 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) = DMAC_DCCSR_NDES; | 158 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) = DMAC_DCCSR_NDES; |
159 | REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)source); | 159 | REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)source); |
160 | REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT); | 160 | REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT); |
161 | REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 16; | 161 | REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 16; |
162 | REG_DMAC_DRSR(DMA_NAND_CHANNEL) = DMAC_DRSR_RS_AUTO; | 162 | REG_DMAC_DRSR(DMA_NAND_CHANNEL) = DMAC_DRSR_RS_AUTO; |
163 | REG_DMAC_DCMD(DMA_NAND_CHANNEL) = (DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_16BYTE | | 163 | REG_DMAC_DCMD(DMA_NAND_CHANNEL) = (DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_16BYTE | |
164 | (bw == 8 ? DMAC_DCMD_DWDH_8 : DMAC_DCMD_DWDH_16)); | 164 | (bw == 8 ? DMAC_DCMD_DWDH_8 : DMAC_DCMD_DWDH_16)); |
165 | 165 | ||
166 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */ | 166 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */ |
167 | #if 1 | 167 | #if 1 |
168 | while( REG_DMAC_DTCR(DMA_NAND_CHANNEL) ) | 168 | while( REG_DMAC_DTCR(DMA_NAND_CHANNEL) ) |
@@ -173,26 +173,26 @@ static void jz_nand_write_dma(void *source, unsigned int len, int bw) | |||
173 | #endif | 173 | #endif |
174 | 174 | ||
175 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ | 175 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ |
176 | 176 | ||
177 | dma_disable(); | 177 | dma_disable(); |
178 | 178 | ||
179 | mutex_unlock(&nand_dma_mtx); | 179 | mutex_unlock(&nand_dma_mtx); |
180 | } | 180 | } |
181 | 181 | ||
182 | static void jz_nand_read_dma(void *target, unsigned int len, int bw) | 182 | static void jz_nand_read_dma(void *target, unsigned int len, int bw) |
183 | { | 183 | { |
184 | mutex_lock(&nand_dma_mtx); | 184 | mutex_lock(&nand_dma_mtx); |
185 | 185 | ||
186 | if(((unsigned int)target < 0xa0000000) && len) | 186 | if(((unsigned int)target < 0xa0000000) && len) |
187 | dma_cache_wback_inv((unsigned long)target, len); | 187 | dma_cache_wback_inv((unsigned long)target, len); |
188 | 188 | ||
189 | dma_enable(); | 189 | dma_enable(); |
190 | 190 | ||
191 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) = DMAC_DCCSR_NDES ; | 191 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) = DMAC_DCCSR_NDES ; |
192 | REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT); | 192 | REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT); |
193 | REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)target); | 193 | REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)target); |
194 | REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 4; | 194 | REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 4; |
195 | REG_DMAC_DRSR(DMA_NAND_CHANNEL) = DMAC_DRSR_RS_AUTO; | 195 | REG_DMAC_DRSR(DMA_NAND_CHANNEL) = DMAC_DRSR_RS_AUTO; |
196 | REG_DMAC_DCMD(DMA_NAND_CHANNEL) = (DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT | | 196 | REG_DMAC_DCMD(DMA_NAND_CHANNEL) = (DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT | |
197 | (bw == 8 ? DMAC_DCMD_SWDH_8 : DMAC_DCMD_SWDH_16)); | 197 | (bw == 8 ? DMAC_DCMD_SWDH_8 : DMAC_DCMD_SWDH_16)); |
198 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */ | 198 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */ |
@@ -205,9 +205,9 @@ static void jz_nand_read_dma(void *target, unsigned int len, int bw) | |||
205 | #endif | 205 | #endif |
206 | 206 | ||
207 | //REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ | 207 | //REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ |
208 | 208 | ||
209 | dma_disable(); | 209 | dma_disable(); |
210 | 210 | ||
211 | mutex_unlock(&nand_dma_mtx); | 211 | mutex_unlock(&nand_dma_mtx); |
212 | } | 212 | } |
213 | 213 | ||
@@ -224,7 +224,7 @@ void DMA_CALLBACK(DMA_NAND_CHANNEL)(void) | |||
224 | 224 | ||
225 | if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_TT) | 225 | if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_TT) |
226 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_TT; | 226 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_TT; |
227 | 227 | ||
228 | semaphore_release(&nand_dma_complete); | 228 | semaphore_release(&nand_dma_complete); |
229 | } | 229 | } |
230 | #endif /* USE_DMA */ | 230 | #endif /* USE_DMA */ |
@@ -246,7 +246,7 @@ static inline void jz_nand_read_buf(void *buf, int count, int bw) | |||
246 | 246 | ||
247 | #ifdef USE_ECC | 247 | #ifdef USE_ECC |
248 | /* | 248 | /* |
249 | * Correct 1~9-bit errors in 512-bytes data | 249 | * Correct 1~9-bit errors in 512-bytes data |
250 | */ | 250 | */ |
251 | static void jz_rs_correct(unsigned char *dat, int idx, int mask) | 251 | static void jz_rs_correct(unsigned char *dat, int idx, int mask) |
252 | { | 252 | { |
@@ -349,7 +349,7 @@ static int jz_nand_read_page(unsigned long page_addr, unsigned char *dst) | |||
349 | #endif | 349 | #endif |
350 | unsigned char *data_buf; | 350 | unsigned char *data_buf; |
351 | unsigned char oob_buf[nandp->oob_size]; | 351 | unsigned char oob_buf[nandp->oob_size]; |
352 | 352 | ||
353 | if(nand_address == 0) | 353 | if(nand_address == 0) |
354 | return -1; | 354 | return -1; |
355 | 355 | ||
@@ -484,28 +484,28 @@ static void jz_nand_disable(void) | |||
484 | * Enable NAND controller | 484 | * Enable NAND controller |
485 | */ | 485 | */ |
486 | static void jz_nand_enable(void) | 486 | static void jz_nand_enable(void) |
487 | { | 487 | { |
488 | #if 0 | 488 | #if 0 |
489 | /* OF RE */ | 489 | /* OF RE */ |
490 | REG_GPIO_PXFUNS(1) = 0x1E018000; // __gpio_as_func0() start | 490 | REG_GPIO_PXFUNS(1) = 0x1E018000; // __gpio_as_func0() start |
491 | REG_GPIO_PXSELC(1) = 0x1E018000; // __gpio_as_func0() end | 491 | REG_GPIO_PXSELC(1) = 0x1E018000; // __gpio_as_func0() end |
492 | 492 | ||
493 | REG_GPIO_PXFUNS(2) = 0x3000<<16; // __gpio_as_func0() start | 493 | REG_GPIO_PXFUNS(2) = 0x3000<<16; // __gpio_as_func0() start |
494 | REG_GPIO_PXSELC(2) = 0x3000<<16; // __gpio_as_func0() end | 494 | REG_GPIO_PXSELC(2) = 0x3000<<16; // __gpio_as_func0() end |
495 | 495 | ||
496 | REG_GPIO_PXFUNC(2) = 0x4000<<16; // __gpio_port_as_input() start | 496 | REG_GPIO_PXFUNC(2) = 0x4000<<16; // __gpio_port_as_input() start |
497 | REG_GPIO_PXSELC(2) = 0x4000<<16; | 497 | REG_GPIO_PXSELC(2) = 0x4000<<16; |
498 | REG_GPIO_PXDIRC(2) = 0x4000<<16; // __gpio_port_as_input() end | 498 | REG_GPIO_PXDIRC(2) = 0x4000<<16; // __gpio_port_as_input() end |
499 | REG_GPIO_PXPES(2) = 0x4000<<16; // __gpio_disable_pull() | 499 | REG_GPIO_PXPES(2) = 0x4000<<16; // __gpio_disable_pull() |
500 | 500 | ||
501 | REG_GPIO_PXFUNS(1) = 0x40<<16; // __gpio_as_func0() start | 501 | REG_GPIO_PXFUNS(1) = 0x40<<16; // __gpio_as_func0() start |
502 | REG_GPIO_PXSELC(1) = 0x40<<16; // __gpio_as_func0() end | 502 | REG_GPIO_PXSELC(1) = 0x40<<16; // __gpio_as_func0() end |
503 | 503 | ||
504 | REG_EMC_SMCR1 = (REG_EMC_SMCR1 & 0xFF) | 0x4621200; | 504 | REG_EMC_SMCR1 = (REG_EMC_SMCR1 & 0xFF) | 0x4621200; |
505 | REG_EMC_SMCR2 = (REG_EMC_SMCR2 & 0xFF) | 0x4621200; | 505 | REG_EMC_SMCR2 = (REG_EMC_SMCR2 & 0xFF) | 0x4621200; |
506 | REG_EMC_SMCR3 = (REG_EMC_SMCR3 & 0xFF) | 0x4621200; | 506 | REG_EMC_SMCR3 = (REG_EMC_SMCR3 & 0xFF) | 0x4621200; |
507 | REG_EMC_SMCR4 = (REG_EMC_SMCR4 & 0xFF) | 0x4621200; | 507 | REG_EMC_SMCR4 = (REG_EMC_SMCR4 & 0xFF) | 0x4621200; |
508 | 508 | ||
509 | REG_EMC_SMCR1 = REG_EMC_SMCR2 = REG_EMC_SMCR3 = REG_EMC_SMCR4 = 0x6621200; | 509 | REG_EMC_SMCR1 = REG_EMC_SMCR2 = REG_EMC_SMCR3 = REG_EMC_SMCR4 = 0x6621200; |
510 | #else | 510 | #else |
511 | REG_EMC_SMCR1 = REG_EMC_SMCR2 = REG_EMC_SMCR3 = REG_EMC_SMCR4 = 0x04444400; | 511 | REG_EMC_SMCR1 = REG_EMC_SMCR2 = REG_EMC_SMCR3 = REG_EMC_SMCR4 = 0x04444400; |
@@ -543,13 +543,13 @@ static int jz_nand_init(void) | |||
543 | { | 543 | { |
544 | unsigned char cData[5]; | 544 | unsigned char cData[5]; |
545 | int i; | 545 | int i; |
546 | 546 | ||
547 | jz_nand_enable(); | 547 | jz_nand_enable(); |
548 | 548 | ||
549 | for(i=0; i<4; i++) | 549 | for(i=0; i<4; i++) |
550 | { | 550 | { |
551 | jz_nand_select(i); | 551 | jz_nand_select(i); |
552 | 552 | ||
553 | __nand_cmd(NAND_CMD_READID); | 553 | __nand_cmd(NAND_CMD_READID); |
554 | __nand_addr(NAND_CMD_READ0); | 554 | __nand_addr(NAND_CMD_READ0); |
555 | cData[0] = __nand_data8(); | 555 | cData[0] = __nand_data8(); |
@@ -557,17 +557,17 @@ static int jz_nand_init(void) | |||
557 | cData[2] = __nand_data8(); | 557 | cData[2] = __nand_data8(); |
558 | cData[3] = __nand_data8(); | 558 | cData[3] = __nand_data8(); |
559 | cData[4] = __nand_data8(); | 559 | cData[4] = __nand_data8(); |
560 | 560 | ||
561 | jz_nand_deselect(i); | 561 | jz_nand_deselect(i); |
562 | 562 | ||
563 | logf("NAND chip %d: 0x%x 0x%x 0x%x 0x%x 0x%x", i+1, cData[0], cData[1], | 563 | logf("NAND chip %d: 0x%x 0x%x 0x%x 0x%x 0x%x", i+1, cData[0], cData[1], |
564 | cData[2], cData[3], cData[4]); | 564 | cData[2], cData[3], cData[4]); |
565 | 565 | ||
566 | banks[i] = nand_identify(cData); | 566 | banks[i] = nand_identify(cData); |
567 | 567 | ||
568 | if(banks[i] != NULL) | 568 | if(banks[i] != NULL) |
569 | nr_banks++; | 569 | nr_banks++; |
570 | 570 | ||
571 | if(i == 0 && banks[i] == NULL) | 571 | if(i == 0 && banks[i] == NULL) |
572 | { | 572 | { |
573 | panicf("Unknown NAND flash chip: 0x%x 0x%x 0x%x 0x%x 0x%x", cData[0], | 573 | panicf("Unknown NAND flash chip: 0x%x 0x%x 0x%x 0x%x 0x%x", cData[0], |
@@ -576,17 +576,17 @@ static int jz_nand_init(void) | |||
576 | } | 576 | } |
577 | } | 577 | } |
578 | chip_info = banks[0]; | 578 | chip_info = banks[0]; |
579 | 579 | ||
580 | internal_param.bus_width = 8; | 580 | internal_param.bus_width = 8; |
581 | internal_param.row_cycle = chip_info->row_cycles; | 581 | internal_param.row_cycle = chip_info->row_cycles; |
582 | internal_param.page_size = chip_info->page_size; | 582 | internal_param.page_size = chip_info->page_size; |
583 | internal_param.oob_size = chip_info->spare_size; | 583 | internal_param.oob_size = chip_info->spare_size; |
584 | internal_param.page_per_block = chip_info->pages_per_block; | 584 | internal_param.page_per_block = chip_info->pages_per_block; |
585 | 585 | ||
586 | bank_size = chip_info->page_size * chip_info->blocks_per_bank / 512 * chip_info->pages_per_block; | 586 | bank_size = chip_info->page_size * chip_info->blocks_per_bank / 512 * chip_info->pages_per_block; |
587 | 587 | ||
588 | jz_nand_disable(); | 588 | jz_nand_disable(); |
589 | 589 | ||
590 | return 0; | 590 | return 0; |
591 | } | 591 | } |
592 | 592 | ||
@@ -594,7 +594,7 @@ int nand_init(void) | |||
594 | { | 594 | { |
595 | int res = 0; | 595 | int res = 0; |
596 | static bool inited = false; | 596 | static bool inited = false; |
597 | 597 | ||
598 | if(!inited) | 598 | if(!inited) |
599 | { | 599 | { |
600 | res = jz_nand_init(); | 600 | res = jz_nand_init(); |
@@ -604,7 +604,7 @@ int nand_init(void) | |||
604 | semaphore_init(&nand_dma_complete, 1, 0); | 604 | semaphore_init(&nand_dma_complete, 1, 0); |
605 | system_enable_irq(DMA_IRQ(DMA_NAND_CHANNEL)); | 605 | system_enable_irq(DMA_IRQ(DMA_NAND_CHANNEL)); |
606 | #endif | 606 | #endif |
607 | 607 | ||
608 | inited = true; | 608 | inited = true; |
609 | } | 609 | } |
610 | 610 | ||
@@ -615,7 +615,7 @@ static inline int read_sector(unsigned long start, unsigned int count, | |||
615 | void* buf, unsigned int chip_size) | 615 | void* buf, unsigned int chip_size) |
616 | { | 616 | { |
617 | register int ret; | 617 | register int ret; |
618 | 618 | ||
619 | if(UNLIKELY(start % chip_size == 0 && count == chip_size)) | 619 | if(UNLIKELY(start % chip_size == 0 && count == chip_size)) |
620 | ret = jz_nand_read_page(start / chip_size, buf); | 620 | ret = jz_nand_read_page(start / chip_size, buf); |
621 | else | 621 | else |
@@ -623,7 +623,7 @@ static inline int read_sector(unsigned long start, unsigned int count, | |||
623 | ret = jz_nand_read_page(start / chip_size, temp_page); | 623 | ret = jz_nand_read_page(start / chip_size, temp_page); |
624 | memcpy(buf, temp_page + (start % chip_size), count); | 624 | memcpy(buf, temp_page + (start % chip_size), count); |
625 | } | 625 | } |
626 | 626 | ||
627 | return ret; | 627 | return ret; |
628 | } | 628 | } |
629 | 629 | ||
@@ -635,13 +635,13 @@ int nand_read_sectors(IF_MV(int drive,) unsigned long start, int count, void* bu | |||
635 | int ret = 0; | 635 | int ret = 0; |
636 | unsigned int i, _count, chip_size = chip_info->page_size; | 636 | unsigned int i, _count, chip_size = chip_info->page_size; |
637 | unsigned long _start; | 637 | unsigned long _start; |
638 | 638 | ||
639 | logf("start"); | 639 | logf("start"); |
640 | mutex_lock(&nand_mtx); | 640 | mutex_lock(&nand_mtx); |
641 | 641 | ||
642 | _start = start << 9; | 642 | _start = start << 9; |
643 | _count = count << 9; | 643 | _count = count << 9; |
644 | 644 | ||
645 | if(_count <= chip_size) | 645 | if(_count <= chip_size) |
646 | { | 646 | { |
647 | jz_nand_select(start / bank_size); | 647 | jz_nand_select(start / bank_size); |
@@ -653,19 +653,19 @@ int nand_read_sectors(IF_MV(int drive,) unsigned long start, int count, void* bu | |||
653 | for(i=0; i<_count && ret==0; i+=chip_size) | 653 | for(i=0; i<_count && ret==0; i+=chip_size) |
654 | { | 654 | { |
655 | jz_nand_select((start+(i>>9)) / bank_size); | 655 | jz_nand_select((start+(i>>9)) / bank_size); |
656 | 656 | ||
657 | ret = read_sector(_start+i, (_count-i < chip_size ? | 657 | ret = read_sector(_start+i, (_count-i < chip_size ? |
658 | _count-i : chip_size), | 658 | _count-i : chip_size), |
659 | buf+i, chip_size); | 659 | buf+i, chip_size); |
660 | 660 | ||
661 | jz_nand_deselect((start+(i>>9)) / bank_size); | 661 | jz_nand_deselect((start+(i>>9)) / bank_size); |
662 | } | 662 | } |
663 | } | 663 | } |
664 | 664 | ||
665 | mutex_unlock(&nand_mtx); | 665 | mutex_unlock(&nand_mtx); |
666 | 666 | ||
667 | logf("nand_read_sectors(%ld, %d, 0x%x): %d", start, count, (int)buf, ret); | 667 | logf("nand_read_sectors(%ld, %d, 0x%x): %d", start, count, (int)buf, ret); |
668 | 668 | ||
669 | return ret; | 669 | return ret; |
670 | } | 670 | } |
671 | 671 | ||
@@ -732,7 +732,7 @@ void nand_get_info(IF_MV(int drive,) struct storage_info *info) | |||
732 | #ifdef HAVE_MULTIVOLUME | 732 | #ifdef HAVE_MULTIVOLUME |
733 | (void)drive; | 733 | (void)drive; |
734 | #endif | 734 | #endif |
735 | 735 | ||
736 | /* firmware version */ | 736 | /* firmware version */ |
737 | info->revision="0.00"; | 737 | info->revision="0.00"; |
738 | 738 | ||
@@ -750,7 +750,7 @@ int nand_num_drives(int first_drive) | |||
750 | { | 750 | { |
751 | /* We don't care which logical drive number(s) we have been assigned */ | 751 | /* We don't care which logical drive number(s) we have been assigned */ |
752 | (void)first_drive; | 752 | (void)first_drive; |
753 | 753 | ||
754 | return 1; | 754 | return 1; |
755 | } | 755 | } |
756 | #endif | 756 | #endif |
diff --git a/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4760.c b/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4760.c index 3b1a1aad59..1eacf9170a 100644 --- a/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4760.c | |||
@@ -148,20 +148,20 @@ static inline void jz_nand_read_buf8(void *buf, int count) | |||
148 | static void jz_nand_write_dma(void *source, unsigned int len, int bw) | 148 | static void jz_nand_write_dma(void *source, unsigned int len, int bw) |
149 | { | 149 | { |
150 | mutex_lock(&nand_dma_mtx); | 150 | mutex_lock(&nand_dma_mtx); |
151 | 151 | ||
152 | if(((unsigned int)source < 0xa0000000) && len) | 152 | if(((unsigned int)source < 0xa0000000) && len) |
153 | dma_cache_wback_inv((unsigned long)source, len); | 153 | dma_cache_wback_inv((unsigned long)source, len); |
154 | 154 | ||
155 | dma_enable(); | 155 | dma_enable(); |
156 | 156 | ||
157 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) = DMAC_DCCSR_NDES; | 157 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) = DMAC_DCCSR_NDES; |
158 | REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)source); | 158 | REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)source); |
159 | REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT); | 159 | REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT); |
160 | REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 16; | 160 | REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 16; |
161 | REG_DMAC_DRSR(DMA_NAND_CHANNEL) = DMAC_DRSR_RS_AUTO; | 161 | REG_DMAC_DRSR(DMA_NAND_CHANNEL) = DMAC_DRSR_RS_AUTO; |
162 | REG_DMAC_DCMD(DMA_NAND_CHANNEL) = (DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_16BYTE | | 162 | REG_DMAC_DCMD(DMA_NAND_CHANNEL) = (DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_16BYTE | |
163 | (bw == 8 ? DMAC_DCMD_DWDH_8 : DMAC_DCMD_DWDH_16)); | 163 | (bw == 8 ? DMAC_DCMD_DWDH_8 : DMAC_DCMD_DWDH_16)); |
164 | 164 | ||
165 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */ | 165 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */ |
166 | #if 1 | 166 | #if 1 |
167 | while( REG_DMAC_DTCR(DMA_NAND_CHANNEL) ) | 167 | while( REG_DMAC_DTCR(DMA_NAND_CHANNEL) ) |
@@ -172,26 +172,26 @@ static void jz_nand_write_dma(void *source, unsigned int len, int bw) | |||
172 | #endif | 172 | #endif |
173 | 173 | ||
174 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ | 174 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ |
175 | 175 | ||
176 | dma_disable(); | 176 | dma_disable(); |
177 | 177 | ||
178 | mutex_unlock(&nand_dma_mtx); | 178 | mutex_unlock(&nand_dma_mtx); |
179 | } | 179 | } |
180 | 180 | ||
181 | static void jz_nand_read_dma(void *target, unsigned int len, int bw) | 181 | static void jz_nand_read_dma(void *target, unsigned int len, int bw) |
182 | { | 182 | { |
183 | mutex_lock(&nand_dma_mtx); | 183 | mutex_lock(&nand_dma_mtx); |
184 | 184 | ||
185 | if(((unsigned int)target < 0xa0000000) && len) | 185 | if(((unsigned int)target < 0xa0000000) && len) |
186 | dma_cache_wback_inv((unsigned long)target, len); | 186 | dma_cache_wback_inv((unsigned long)target, len); |
187 | 187 | ||
188 | dma_enable(); | 188 | dma_enable(); |
189 | 189 | ||
190 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) = DMAC_DCCSR_NDES ; | 190 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) = DMAC_DCCSR_NDES ; |
191 | REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT); | 191 | REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT); |
192 | REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)target); | 192 | REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)target); |
193 | REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 4; | 193 | REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 4; |
194 | REG_DMAC_DRSR(DMA_NAND_CHANNEL) = DMAC_DRSR_RS_AUTO; | 194 | REG_DMAC_DRSR(DMA_NAND_CHANNEL) = DMAC_DRSR_RS_AUTO; |
195 | REG_DMAC_DCMD(DMA_NAND_CHANNEL) = (DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT | | 195 | REG_DMAC_DCMD(DMA_NAND_CHANNEL) = (DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT | |
196 | (bw == 8 ? DMAC_DCMD_SWDH_8 : DMAC_DCMD_SWDH_16)); | 196 | (bw == 8 ? DMAC_DCMD_SWDH_8 : DMAC_DCMD_SWDH_16)); |
197 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */ | 197 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */ |
@@ -204,9 +204,9 @@ static void jz_nand_read_dma(void *target, unsigned int len, int bw) | |||
204 | #endif | 204 | #endif |
205 | 205 | ||
206 | //REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ | 206 | //REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ |
207 | 207 | ||
208 | dma_disable(); | 208 | dma_disable(); |
209 | 209 | ||
210 | mutex_unlock(&nand_dma_mtx); | 210 | mutex_unlock(&nand_dma_mtx); |
211 | } | 211 | } |
212 | 212 | ||
@@ -223,7 +223,7 @@ void DMA_CALLBACK(DMA_NAND_CHANNEL)(void) | |||
223 | 223 | ||
224 | if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_TT) | 224 | if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_TT) |
225 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_TT; | 225 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_TT; |
226 | 226 | ||
227 | semaphore_release(&nand_dma_complete); | 227 | semaphore_release(&nand_dma_complete); |
228 | } | 228 | } |
229 | #endif /* USE_DMA */ | 229 | #endif /* USE_DMA */ |
@@ -245,7 +245,7 @@ static inline void jz_nand_read_buf(void *buf, int count, int bw) | |||
245 | 245 | ||
246 | #ifdef USE_ECC | 246 | #ifdef USE_ECC |
247 | /* | 247 | /* |
248 | * Correct 1~9-bit errors in 512-bytes data | 248 | * Correct 1~9-bit errors in 512-bytes data |
249 | */ | 249 | */ |
250 | static void jz_rs_correct(unsigned char *dat, int idx, int mask) | 250 | static void jz_rs_correct(unsigned char *dat, int idx, int mask) |
251 | { | 251 | { |
@@ -348,7 +348,7 @@ static int jz_nand_read_page(unsigned long page_addr, unsigned char *dst) | |||
348 | #endif | 348 | #endif |
349 | unsigned char *data_buf; | 349 | unsigned char *data_buf; |
350 | unsigned char oob_buf[nandp->oob_size]; | 350 | unsigned char oob_buf[nandp->oob_size]; |
351 | 351 | ||
352 | page_size = nandp->page_size; | 352 | page_size = nandp->page_size; |
353 | oob_size = nandp->oob_size; | 353 | oob_size = nandp->oob_size; |
354 | row_cycle = nandp->row_cycle; | 354 | row_cycle = nandp->row_cycle; |
@@ -472,9 +472,9 @@ static int jz_nand_init(void) | |||
472 | __gpio_as_nand_16bit(1); | 472 | __gpio_as_nand_16bit(1); |
473 | 473 | ||
474 | REG_NEMC_SMCR1 = CFG_NAND_SMCR1 | 0x40; | 474 | REG_NEMC_SMCR1 = CFG_NAND_SMCR1 | 0x40; |
475 | 475 | ||
476 | __nand_select(); | 476 | __nand_select(); |
477 | 477 | ||
478 | __nand_cmd(NAND_CMD_READID); | 478 | __nand_cmd(NAND_CMD_READID); |
479 | __nand_addr(NAND_CMD_READ0); | 479 | __nand_addr(NAND_CMD_READ0); |
480 | cData[0] = __nand_data8(); | 480 | cData[0] = __nand_data8(); |
@@ -482,14 +482,14 @@ static int jz_nand_init(void) | |||
482 | cData[2] = __nand_data8(); | 482 | cData[2] = __nand_data8(); |
483 | cData[3] = __nand_data8(); | 483 | cData[3] = __nand_data8(); |
484 | cData[4] = __nand_data8(); | 484 | cData[4] = __nand_data8(); |
485 | 485 | ||
486 | __nand_deselect(); | 486 | __nand_deselect(); |
487 | 487 | ||
488 | logf("NAND chip %d: 0x%x 0x%x 0x%x 0x%x 0x%x", i+1, cData[0], cData[1], | 488 | logf("NAND chip %d: 0x%x 0x%x 0x%x 0x%x 0x%x", i+1, cData[0], cData[1], |
489 | cData[2], cData[3], cData[4]); | 489 | cData[2], cData[3], cData[4]); |
490 | 490 | ||
491 | bank = nand_identify(cData); | 491 | bank = nand_identify(cData); |
492 | 492 | ||
493 | if(bank == NULL) | 493 | if(bank == NULL) |
494 | { | 494 | { |
495 | panicf("Unknown NAND flash chip: 0x%x 0x%x 0x%x 0x%x 0x%x", cData[0], | 495 | panicf("Unknown NAND flash chip: 0x%x 0x%x 0x%x 0x%x 0x%x", cData[0], |
@@ -498,16 +498,16 @@ static int jz_nand_init(void) | |||
498 | } | 498 | } |
499 | 499 | ||
500 | chip_info = bank; | 500 | chip_info = bank; |
501 | 501 | ||
502 | internal_param.bus_width = 16; | 502 | internal_param.bus_width = 16; |
503 | internal_param.row_cycle = chip_info->row_cycles; | 503 | internal_param.row_cycle = chip_info->row_cycles; |
504 | internal_param.page_size = chip_info->page_size; | 504 | internal_param.page_size = chip_info->page_size; |
505 | internal_param.oob_size = chip_info->spare_size; | 505 | internal_param.oob_size = chip_info->spare_size; |
506 | internal_param.page_per_block = chip_info->pages_per_block; | 506 | internal_param.page_per_block = chip_info->pages_per_block; |
507 | internal_param.bad_block_pos = 0; | 507 | internal_param.bad_block_pos = 0; |
508 | 508 | ||
509 | nand_size = ((chip_info->page_size * chip_info->blocks_per_bank * chip_info->pages_per_block) - 0x200000) / 512; | 509 | nand_size = ((chip_info->page_size * chip_info->blocks_per_bank * chip_info->pages_per_block) - 0x200000) / 512; |
510 | 510 | ||
511 | return 0; | 511 | return 0; |
512 | } | 512 | } |
513 | 513 | ||
@@ -515,7 +515,7 @@ int nand_init(void) | |||
515 | { | 515 | { |
516 | int res = 0; | 516 | int res = 0; |
517 | static bool inited = false; | 517 | static bool inited = false; |
518 | 518 | ||
519 | if(!inited) | 519 | if(!inited) |
520 | { | 520 | { |
521 | res = jz_nand_init(); | 521 | res = jz_nand_init(); |
@@ -525,7 +525,7 @@ int nand_init(void) | |||
525 | semaphore_init(&nand_dma_complete, 1, 0); | 525 | semaphore_init(&nand_dma_complete, 1, 0); |
526 | system_enable_irq(DMA_IRQ(DMA_NAND_CHANNEL)); | 526 | system_enable_irq(DMA_IRQ(DMA_NAND_CHANNEL)); |
527 | #endif | 527 | #endif |
528 | 528 | ||
529 | inited = true; | 529 | inited = true; |
530 | } | 530 | } |
531 | 531 | ||
@@ -536,7 +536,7 @@ static inline int read_sector(unsigned long start, unsigned int count, | |||
536 | void* buf, unsigned int chip_size) | 536 | void* buf, unsigned int chip_size) |
537 | { | 537 | { |
538 | register int ret; | 538 | register int ret; |
539 | 539 | ||
540 | if(UNLIKELY(start % chip_size == 0 && count == chip_size)) | 540 | if(UNLIKELY(start % chip_size == 0 && count == chip_size)) |
541 | ret = jz_nand_read_page(start / chip_size, buf); | 541 | ret = jz_nand_read_page(start / chip_size, buf); |
542 | else | 542 | else |
@@ -544,7 +544,7 @@ static inline int read_sector(unsigned long start, unsigned int count, | |||
544 | ret = jz_nand_read_page(start / chip_size, temp_page); | 544 | ret = jz_nand_read_page(start / chip_size, temp_page); |
545 | memcpy(buf, temp_page + (start % chip_size), count); | 545 | memcpy(buf, temp_page + (start % chip_size), count); |
546 | } | 546 | } |
547 | 547 | ||
548 | return ret; | 548 | return ret; |
549 | } | 549 | } |
550 | 550 | ||
@@ -559,7 +559,7 @@ static inline int write_sector(unsigned long start, unsigned int count, | |||
559 | (void)chip_size; | 559 | (void)chip_size; |
560 | 560 | ||
561 | /* TODO */ | 561 | /* TODO */ |
562 | 562 | ||
563 | return ret; | 563 | return ret; |
564 | } | 564 | } |
565 | 565 | ||
@@ -571,20 +571,20 @@ int nand_read_sectors(IF_MV(int drive,) unsigned long start, int count, void* bu | |||
571 | int ret = 0; | 571 | int ret = 0; |
572 | unsigned int _count, chip_size = chip_info->page_size; | 572 | unsigned int _count, chip_size = chip_info->page_size; |
573 | unsigned long _start; | 573 | unsigned long _start; |
574 | 574 | ||
575 | logf("start"); | 575 | logf("start"); |
576 | mutex_lock(&nand_mtx); | 576 | mutex_lock(&nand_mtx); |
577 | 577 | ||
578 | _start = start << 9; | 578 | _start = start << 9; |
579 | _start += 0x200000; /* skip BL */ | 579 | _start += 0x200000; /* skip BL */ |
580 | _count = count << 9; | 580 | _count = count << 9; |
581 | 581 | ||
582 | __nand_select(); | 582 | __nand_select(); |
583 | ret = read_sector(_start, _count, buf, chip_size); | 583 | ret = read_sector(_start, _count, buf, chip_size); |
584 | __nand_deselect(); | 584 | __nand_deselect(); |
585 | 585 | ||
586 | mutex_unlock(&nand_mtx); | 586 | mutex_unlock(&nand_mtx); |
587 | 587 | ||
588 | logf("nand_read_sectors(%ld, %d, 0x%x): %d", start, count, (int)buf, ret); | 588 | logf("nand_read_sectors(%ld, %d, 0x%x): %d", start, count, (int)buf, ret); |
589 | 589 | ||
590 | return ret; | 590 | return ret; |
@@ -598,20 +598,20 @@ int nand_write_sectors(IF_MV(int drive,) unsigned long start, int count, const v | |||
598 | int ret = 0; | 598 | int ret = 0; |
599 | unsigned int _count, chip_size = chip_info->page_size; | 599 | unsigned int _count, chip_size = chip_info->page_size; |
600 | unsigned long _start; | 600 | unsigned long _start; |
601 | 601 | ||
602 | logf("start"); | 602 | logf("start"); |
603 | mutex_lock(&nand_mtx); | 603 | mutex_lock(&nand_mtx); |
604 | 604 | ||
605 | _start = start << 9; | 605 | _start = start << 9; |
606 | _start += chip_info->page_size * chip_info->pages_per_block; /* skip BL */ | 606 | _start += chip_info->page_size * chip_info->pages_per_block; /* skip BL */ |
607 | _count = count << 9; | 607 | _count = count << 9; |
608 | 608 | ||
609 | __nand_select(); | 609 | __nand_select(); |
610 | ret = write_sector(_start, _count, buf, chip_size); | 610 | ret = write_sector(_start, _count, buf, chip_size); |
611 | __nand_deselect(); | 611 | __nand_deselect(); |
612 | 612 | ||
613 | mutex_unlock(&nand_mtx); | 613 | mutex_unlock(&nand_mtx); |
614 | 614 | ||
615 | logf("nand_write_sectors(%ld, %d, 0x%x): %d", start, count, (int)buf, ret); | 615 | logf("nand_write_sectors(%ld, %d, 0x%x): %d", start, count, (int)buf, ret); |
616 | 616 | ||
617 | return ret; | 617 | return ret; |
@@ -667,7 +667,7 @@ void nand_get_info(IF_MV(int drive,) struct storage_info *info) | |||
667 | #ifdef HAVE_MULTIVOLUME | 667 | #ifdef HAVE_MULTIVOLUME |
668 | (void)drive; | 668 | (void)drive; |
669 | #endif | 669 | #endif |
670 | 670 | ||
671 | /* firmware version */ | 671 | /* firmware version */ |
672 | info->revision="0.00"; | 672 | info->revision="0.00"; |
673 | 673 | ||
@@ -685,7 +685,7 @@ int nand_num_drives(int first_drive) | |||
685 | { | 685 | { |
686 | /* We don't care which logical drive number(s) we have been assigned */ | 686 | /* We don't care which logical drive number(s) we have been assigned */ |
687 | (void)first_drive; | 687 | (void)first_drive; |
688 | 688 | ||
689 | return 1; | 689 | return 1; |
690 | } | 690 | } |
691 | #endif | 691 | #endif |
diff --git a/firmware/target/mips/ingenic_jz47xx/dma_acc-jz4740.c b/firmware/target/mips/ingenic_jz47xx/dma_acc-jz4740.c index c4d79a7567..6f317f7b3f 100644 --- a/firmware/target/mips/ingenic_jz47xx/dma_acc-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/dma_acc-jz4740.c | |||
@@ -26,14 +26,14 @@ void memset(void *target, unsigned char c, size_t len) | |||
26 | int ch = DMA_CHANNEL; | 26 | int ch = DMA_CHANNEL; |
27 | unsigned int d; | 27 | unsigned int d; |
28 | unsigned char *dp; | 28 | unsigned char *dp; |
29 | 29 | ||
30 | if(len < 32) | 30 | if(len < 32) |
31 | _memset(target,c,len); | 31 | _memset(target,c,len); |
32 | else | 32 | else |
33 | { | 33 | { |
34 | if(((unsigned int)target < 0xa0000000) && len) | 34 | if(((unsigned int)target < 0xa0000000) && len) |
35 | dma_cache_wback_inv((unsigned long)target, len); | 35 | dma_cache_wback_inv((unsigned long)target, len); |
36 | 36 | ||
37 | dp = (unsigned char *)((unsigned int)(&d) | 0xa0000000); | 37 | dp = (unsigned char *)((unsigned int)(&d) | 0xa0000000); |
38 | *(dp + 0) = c; | 38 | *(dp + 0) = c; |
39 | *(dp + 1) = c; | 39 | *(dp + 1) = c; |
@@ -45,16 +45,16 @@ void memset(void *target, unsigned char c, size_t len) | |||
45 | REG_DMAC_DRSR(ch) = DMAC_DRSR_RS_AUTO; | 45 | REG_DMAC_DRSR(ch) = DMAC_DRSR_RS_AUTO; |
46 | REG_DMAC_DCMD(ch) = DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BYTE; | 46 | REG_DMAC_DCMD(ch) = DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BYTE; |
47 | REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES; | 47 | REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES; |
48 | 48 | ||
49 | while (REG_DMAC_DTCR(ch)); | 49 | while (REG_DMAC_DTCR(ch)); |
50 | if(len % 32) | 50 | if(len % 32) |
51 | { | 51 | { |
52 | dp = (unsigned char *)((unsigned int)target + (len & (32 - 1))); | 52 | dp = (unsigned char *)((unsigned int)target + (len & (32 - 1))); |
53 | for(d = 0;d < (len % 32); d++) | 53 | for(d = 0;d < (len % 32); d++) |
54 | *dp++ = c; | 54 | *dp++ = c; |
55 | 55 | ||
56 | } | 56 | } |
57 | } | 57 | } |
58 | } | 58 | } |
59 | 59 | ||
60 | void memset16(void *target, unsigned short c, size_t len) | 60 | void memset16(void *target, unsigned short c, size_t len) |
@@ -62,14 +62,14 @@ void memset16(void *target, unsigned short c, size_t len) | |||
62 | int ch = DMA_CHANNEL; | 62 | int ch = DMA_CHANNEL; |
63 | unsigned short d; | 63 | unsigned short d; |
64 | unsigned short *dp; | 64 | unsigned short *dp; |
65 | 65 | ||
66 | if(len < 32) | 66 | if(len < 32) |
67 | _memset16(target,c,len); | 67 | _memset16(target,c,len); |
68 | else | 68 | else |
69 | { | 69 | { |
70 | if(((unsigned int)target < 0xa0000000) && len) | 70 | if(((unsigned int)target < 0xa0000000) && len) |
71 | dma_cache_wback_inv((unsigned long)target, len); | 71 | dma_cache_wback_inv((unsigned long)target, len); |
72 | 72 | ||
73 | d = c; | 73 | d = c; |
74 | REG_DMAC_DSAR(ch) = PHYSADDR((unsigned long)&d); | 74 | REG_DMAC_DSAR(ch) = PHYSADDR((unsigned long)&d); |
75 | REG_DMAC_DTAR(ch) = PHYSADDR((unsigned long)target); | 75 | REG_DMAC_DTAR(ch) = PHYSADDR((unsigned long)target); |
@@ -77,7 +77,7 @@ void memset16(void *target, unsigned short c, size_t len) | |||
77 | REG_DMAC_DRSR(ch) = DMAC_DRSR_RS_AUTO; | 77 | REG_DMAC_DRSR(ch) = DMAC_DRSR_RS_AUTO; |
78 | REG_DMAC_DCMD(ch) = DMAC_DCMD_DAI | DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_32BYTE; | 78 | REG_DMAC_DCMD(ch) = DMAC_DCMD_DAI | DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_32BYTE; |
79 | REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES; | 79 | REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES; |
80 | 80 | ||
81 | while (REG_DMAC_DTCR(ch)); | 81 | while (REG_DMAC_DTCR(ch)); |
82 | if(len % 32) | 82 | if(len % 32) |
83 | { | 83 | { |
@@ -85,29 +85,29 @@ void memset16(void *target, unsigned short c, size_t len) | |||
85 | for(d = 0; d < (len % 32); d++) | 85 | for(d = 0; d < (len % 32); d++) |
86 | *dp++ = c; | 86 | *dp++ = c; |
87 | } | 87 | } |
88 | } | 88 | } |
89 | } | 89 | } |
90 | 90 | ||
91 | void memcpy(void *target, const void *source, size_t len) | 91 | void memcpy(void *target, const void *source, size_t len) |
92 | { | 92 | { |
93 | int ch = DMA_CHANNEL; | 93 | int ch = DMA_CHANNEL; |
94 | unsigned char *dp; | 94 | unsigned char *dp; |
95 | 95 | ||
96 | if(len < 4) | 96 | if(len < 4) |
97 | _memcpy(target, source, len); | 97 | _memcpy(target, source, len); |
98 | 98 | ||
99 | if(((unsigned int)source < 0xa0000000) && len) | 99 | if(((unsigned int)source < 0xa0000000) && len) |
100 | dma_cache_wback_inv((unsigned long)source, len); | 100 | dma_cache_wback_inv((unsigned long)source, len); |
101 | 101 | ||
102 | if(((unsigned int)target < 0xa0000000) && len) | 102 | if(((unsigned int)target < 0xa0000000) && len) |
103 | dma_cache_wback_inv((unsigned long)target, len); | 103 | dma_cache_wback_inv((unsigned long)target, len); |
104 | 104 | ||
105 | REG_DMAC_DSAR(ch) = PHYSADDR((unsigned long)source); | 105 | REG_DMAC_DSAR(ch) = PHYSADDR((unsigned long)source); |
106 | REG_DMAC_DTAR(ch) = PHYSADDR((unsigned long)target); | 106 | REG_DMAC_DTAR(ch) = PHYSADDR((unsigned long)target); |
107 | REG_DMAC_DTCR(ch) = len / 4; | 107 | REG_DMAC_DTCR(ch) = len / 4; |
108 | REG_DMAC_DRSR(ch) = DMAC_DRSR_RS_AUTO; | 108 | REG_DMAC_DRSR(ch) = DMAC_DRSR_RS_AUTO; |
109 | REG_DMAC_DCMD(ch) = DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT; | 109 | REG_DMAC_DCMD(ch) = DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT; |
110 | 110 | ||
111 | REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES; | 111 | REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES; |
112 | while (REG_DMAC_DTCR(ch)); | 112 | while (REG_DMAC_DTCR(ch)); |
113 | if(len % 4) | 113 | if(len % 4) |
diff --git a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c index c644b9f477..cf676622f1 100644 --- a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c | |||
@@ -53,7 +53,7 @@ void lcd_clock_disable(void) | |||
53 | void lcd_init_device(void) | 53 | void lcd_init_device(void) |
54 | { | 54 | { |
55 | lcd_init_controller(); | 55 | lcd_init_controller(); |
56 | 56 | ||
57 | lcd_is_on = true; | 57 | lcd_is_on = true; |
58 | mutex_init(&lcd_mtx); | 58 | mutex_init(&lcd_mtx); |
59 | semaphore_init(&lcd_wkup, 1, 0); | 59 | semaphore_init(&lcd_wkup, 1, 0); |
@@ -93,41 +93,41 @@ void lcd_update_rect(int x, int y, int width, int height) | |||
93 | width = LCD_WIDTH; | 93 | width = LCD_WIDTH; |
94 | 94 | ||
95 | mutex_lock(&lcd_mtx); | 95 | mutex_lock(&lcd_mtx); |
96 | 96 | ||
97 | lcd_clock_enable(); | 97 | lcd_clock_enable(); |
98 | 98 | ||
99 | lcd_set_target(x, y, width, height); | 99 | lcd_set_target(x, y, width, height); |
100 | 100 | ||
101 | dma_enable(); | 101 | dma_enable(); |
102 | 102 | ||
103 | REG_DMAC_DCCSR(DMA_LCD_CHANNEL) = DMAC_DCCSR_NDES; | 103 | REG_DMAC_DCCSR(DMA_LCD_CHANNEL) = DMAC_DCCSR_NDES; |
104 | REG_DMAC_DSAR(DMA_LCD_CHANNEL) = PHYSADDR((unsigned long)FBADDR(x,y)); | 104 | REG_DMAC_DSAR(DMA_LCD_CHANNEL) = PHYSADDR((unsigned long)FBADDR(x,y)); |
105 | REG_DMAC_DRSR(DMA_LCD_CHANNEL) = DMAC_DRSR_RS_SLCD; | 105 | REG_DMAC_DRSR(DMA_LCD_CHANNEL) = DMAC_DRSR_RS_SLCD; |
106 | REG_DMAC_DTAR(DMA_LCD_CHANNEL) = PHYSADDR(SLCD_FIFO); | 106 | REG_DMAC_DTAR(DMA_LCD_CHANNEL) = PHYSADDR(SLCD_FIFO); |
107 | REG_DMAC_DTCR(DMA_LCD_CHANNEL) = (width * height) >> 3; | 107 | REG_DMAC_DTCR(DMA_LCD_CHANNEL) = (width * height) >> 3; |
108 | 108 | ||
109 | REG_DMAC_DCMD(DMA_LCD_CHANNEL) = ( DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | 109 | REG_DMAC_DCMD(DMA_LCD_CHANNEL) = ( DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 |
110 | | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BYTE ); | 110 | | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BYTE ); |
111 | 111 | ||
112 | __dcache_writeback_all(); /* Size of framebuffer is way bigger than cache size. | 112 | __dcache_writeback_all(); /* Size of framebuffer is way bigger than cache size. |
113 | We need to find a way to make the framebuffer uncached, so this statement can get removed. */ | 113 | We need to find a way to make the framebuffer uncached, so this statement can get removed. */ |
114 | 114 | ||
115 | while(REG_SLCD_STATE & SLCD_STATE_BUSY); | 115 | while(REG_SLCD_STATE & SLCD_STATE_BUSY); |
116 | REG_SLCD_CTRL |= SLCD_CTRL_DMA_EN; /* Enable SLCD DMA support */ | 116 | REG_SLCD_CTRL |= SLCD_CTRL_DMA_EN; /* Enable SLCD DMA support */ |
117 | 117 | ||
118 | REG_DMAC_DCCSR(DMA_LCD_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */ | 118 | REG_DMAC_DCCSR(DMA_LCD_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */ |
119 | REG_DMAC_DCMD(DMA_LCD_CHANNEL) |= DMAC_DCMD_TIE; /* Enable DMA interrupt */ | 119 | REG_DMAC_DCMD(DMA_LCD_CHANNEL) |= DMAC_DCMD_TIE; /* Enable DMA interrupt */ |
120 | 120 | ||
121 | semaphore_wait(&lcd_wkup, TIMEOUT_BLOCK); /* Sleeping in lcd_update() should be safe */ | 121 | semaphore_wait(&lcd_wkup, TIMEOUT_BLOCK); /* Sleeping in lcd_update() should be safe */ |
122 | 122 | ||
123 | REG_DMAC_DCCSR(DMA_LCD_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ | 123 | REG_DMAC_DCCSR(DMA_LCD_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ |
124 | dma_disable(); | 124 | dma_disable(); |
125 | 125 | ||
126 | while(REG_SLCD_STATE & SLCD_STATE_BUSY); | 126 | while(REG_SLCD_STATE & SLCD_STATE_BUSY); |
127 | REG_SLCD_CTRL &= ~SLCD_CTRL_DMA_EN; /* Disable SLCD DMA support */ | 127 | REG_SLCD_CTRL &= ~SLCD_CTRL_DMA_EN; /* Disable SLCD DMA support */ |
128 | 128 | ||
129 | lcd_clock_disable(); | 129 | lcd_clock_disable(); |
130 | 130 | ||
131 | mutex_unlock(&lcd_mtx); | 131 | mutex_unlock(&lcd_mtx); |
132 | } | 132 | } |
133 | 133 | ||
@@ -144,7 +144,7 @@ void DMA_CALLBACK(DMA_LCD_CHANNEL)(void) | |||
144 | 144 | ||
145 | if (REG_DMAC_DCCSR(DMA_LCD_CHANNEL) & DMAC_DCCSR_TT) | 145 | if (REG_DMAC_DCCSR(DMA_LCD_CHANNEL) & DMAC_DCCSR_TT) |
146 | REG_DMAC_DCCSR(DMA_LCD_CHANNEL) &= ~DMAC_DCCSR_TT; | 146 | REG_DMAC_DCCSR(DMA_LCD_CHANNEL) &= ~DMAC_DCCSR_TT; |
147 | 147 | ||
148 | semaphore_release(&lcd_wkup); | 148 | semaphore_release(&lcd_wkup); |
149 | } | 149 | } |
150 | 150 | ||
@@ -154,7 +154,7 @@ void lcd_update(void) | |||
154 | { | 154 | { |
155 | if(!lcd_is_on) | 155 | if(!lcd_is_on) |
156 | return; | 156 | return; |
157 | 157 | ||
158 | lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT); | 158 | lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT); |
159 | } | 159 | } |
160 | 160 | ||
@@ -165,55 +165,55 @@ void lcd_blit_yuv(unsigned char * const src[3], | |||
165 | { | 165 | { |
166 | unsigned char const * yuv_src[3]; | 166 | unsigned char const * yuv_src[3]; |
167 | register off_t z; | 167 | register off_t z; |
168 | 168 | ||
169 | if(!lcd_is_on) | 169 | if(!lcd_is_on) |
170 | return; | 170 | return; |
171 | 171 | ||
172 | z = stride * src_y; | 172 | z = stride * src_y; |
173 | yuv_src[0] = src[0] + z + src_x; | 173 | yuv_src[0] = src[0] + z + src_x; |
174 | yuv_src[1] = src[1] + (z >> 2) + (src_x >> 1); | 174 | yuv_src[1] = src[1] + (z >> 2) + (src_x >> 1); |
175 | yuv_src[2] = src[2] + (yuv_src[1] - src[1]); | 175 | yuv_src[2] = src[2] + (yuv_src[1] - src[1]); |
176 | 176 | ||
177 | __dcache_writeback_all(); | 177 | __dcache_writeback_all(); |
178 | 178 | ||
179 | __cpm_start_ipu(); | 179 | __cpm_start_ipu(); |
180 | 180 | ||
181 | IPU_STOP_IPU(); | 181 | IPU_STOP_IPU(); |
182 | IPU_RESET_IPU(); | 182 | IPU_RESET_IPU(); |
183 | IPU_CLEAR_END_FLAG(); | 183 | IPU_CLEAR_END_FLAG(); |
184 | 184 | ||
185 | IPU_DISABLE_RSIZE(); | 185 | IPU_DISABLE_RSIZE(); |
186 | IPU_DISABLE_IRQ(); | 186 | IPU_DISABLE_IRQ(); |
187 | 187 | ||
188 | IPU_SET_INFMT(INFMT_YUV420); | 188 | IPU_SET_INFMT(INFMT_YUV420); |
189 | IPU_SET_OUTFMT(OUTFMT_RGB565); | 189 | IPU_SET_OUTFMT(OUTFMT_RGB565); |
190 | 190 | ||
191 | IPU_SET_IN_FM(width, height); | 191 | IPU_SET_IN_FM(width, height); |
192 | IPU_SET_Y_STRIDE(stride); | 192 | IPU_SET_Y_STRIDE(stride); |
193 | IPU_SET_UV_STRIDE(stride, stride); | 193 | IPU_SET_UV_STRIDE(stride, stride); |
194 | 194 | ||
195 | IPU_SET_Y_ADDR(PHYSADDR((unsigned long)yuv_src[0])); | 195 | IPU_SET_Y_ADDR(PHYSADDR((unsigned long)yuv_src[0])); |
196 | IPU_SET_U_ADDR(PHYSADDR((unsigned long)yuv_src[1])); | 196 | IPU_SET_U_ADDR(PHYSADDR((unsigned long)yuv_src[1])); |
197 | IPU_SET_V_ADDR(PHYSADDR((unsigned long)yuv_src[2])); | 197 | IPU_SET_V_ADDR(PHYSADDR((unsigned long)yuv_src[2])); |
198 | IPU_SET_OUT_ADDR(PHYSADDR((unsigned long)FBADDR(y,x))); | 198 | IPU_SET_OUT_ADDR(PHYSADDR((unsigned long)FBADDR(y,x))); |
199 | 199 | ||
200 | IPU_SET_OUT_FM(height, width); | 200 | IPU_SET_OUT_FM(height, width); |
201 | IPU_SET_OUT_STRIDE(height); | 201 | IPU_SET_OUT_STRIDE(height); |
202 | 202 | ||
203 | IPU_SET_CSC_C0_COEF(YUV_CSC_C0); | 203 | IPU_SET_CSC_C0_COEF(YUV_CSC_C0); |
204 | IPU_SET_CSC_C1_COEF(YUV_CSC_C1); | 204 | IPU_SET_CSC_C1_COEF(YUV_CSC_C1); |
205 | IPU_SET_CSC_C2_COEF(YUV_CSC_C2); | 205 | IPU_SET_CSC_C2_COEF(YUV_CSC_C2); |
206 | IPU_SET_CSC_C3_COEF(YUV_CSC_C3); | 206 | IPU_SET_CSC_C3_COEF(YUV_CSC_C3); |
207 | IPU_SET_CSC_C4_COEF(YUV_CSC_C4); | 207 | IPU_SET_CSC_C4_COEF(YUV_CSC_C4); |
208 | 208 | ||
209 | IPU_RUN_IPU(); | 209 | IPU_RUN_IPU(); |
210 | 210 | ||
211 | while(!(IPU_POLLING_END_FLAG()) && IPU_IS_ENABLED()); | 211 | while(!(IPU_POLLING_END_FLAG()) && IPU_IS_ENABLED()); |
212 | 212 | ||
213 | IPU_CLEAR_END_FLAG(); | 213 | IPU_CLEAR_END_FLAG(); |
214 | IPU_STOP_IPU(); | 214 | IPU_STOP_IPU(); |
215 | IPU_RESET_IPU(); | 215 | IPU_RESET_IPU(); |
216 | 216 | ||
217 | __cpm_stop_ipu(); | 217 | __cpm_stop_ipu(); |
218 | 218 | ||
219 | /* YUV speed is limited by LCD speed */ | 219 | /* YUV speed is limited by LCD speed */ |
diff --git a/firmware/target/mips/mmu-mips.c b/firmware/target/mips/mmu-mips.c index b519bf9331..552348014e 100644 --- a/firmware/target/mips/mmu-mips.c +++ b/firmware/target/mips/mmu-mips.c | |||
@@ -48,7 +48,7 @@ static void local_flush_tlb_all(void) | |||
48 | unsigned long old_ctx; | 48 | unsigned long old_ctx; |
49 | int entry; | 49 | int entry; |
50 | unsigned int old_irq = disable_irq_save(); | 50 | unsigned int old_irq = disable_irq_save(); |
51 | 51 | ||
52 | /* Save old context and create impossible VPN2 value */ | 52 | /* Save old context and create impossible VPN2 value */ |
53 | old_ctx = read_c0_entryhi(); | 53 | old_ctx = read_c0_entryhi(); |
54 | write_c0_entrylo0(0); | 54 | write_c0_entrylo0(0); |
@@ -66,7 +66,7 @@ static void local_flush_tlb_all(void) | |||
66 | } | 66 | } |
67 | BARRIER; | 67 | BARRIER; |
68 | write_c0_entryhi(old_ctx); | 68 | write_c0_entryhi(old_ctx); |
69 | 69 | ||
70 | restore_irq(old_irq); | 70 | restore_irq(old_irq); |
71 | } | 71 | } |
72 | 72 | ||
@@ -77,7 +77,7 @@ static void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, | |||
77 | unsigned long old_pagemask; | 77 | unsigned long old_pagemask; |
78 | unsigned long old_ctx; | 78 | unsigned long old_ctx; |
79 | unsigned int old_irq = disable_irq_save(); | 79 | unsigned int old_irq = disable_irq_save(); |
80 | 80 | ||
81 | old_ctx = read_c0_entryhi() & ASID_MASK; | 81 | old_ctx = read_c0_entryhi() & ASID_MASK; |
82 | old_pagemask = read_c0_pagemask(); | 82 | old_pagemask = read_c0_pagemask(); |
83 | wired = read_c0_wired(); | 83 | wired = read_c0_wired(); |
@@ -105,10 +105,10 @@ void map_address(unsigned long virtual, unsigned long physical, | |||
105 | unsigned long entry0 = (physical & PFN_MASK) << PFN_SHIFT; | 105 | unsigned long entry0 = (physical & PFN_MASK) << PFN_SHIFT; |
106 | unsigned long entry1 = ((physical+length) & PFN_MASK) << PFN_SHIFT; | 106 | unsigned long entry1 = ((physical+length) & PFN_MASK) << PFN_SHIFT; |
107 | unsigned long entryhi = virtual & ~VPN2_SHIFT; | 107 | unsigned long entryhi = virtual & ~VPN2_SHIFT; |
108 | 108 | ||
109 | entry0 |= (M_EntryLoG | M_EntryLoV | (cache_flags << S_EntryLoC) ); | 109 | entry0 |= (M_EntryLoG | M_EntryLoV | (cache_flags << S_EntryLoC) ); |
110 | entry1 |= (M_EntryLoG | M_EntryLoV | (cache_flags << S_EntryLoC) ); | 110 | entry1 |= (M_EntryLoG | M_EntryLoV | (cache_flags << S_EntryLoC) ); |
111 | 111 | ||
112 | add_wired_entry(entry0, entry1, entryhi, DEFAULT_PAGE_MASK); | 112 | add_wired_entry(entry0, entry1, entryhi, DEFAULT_PAGE_MASK); |
113 | } | 113 | } |
114 | 114 | ||
@@ -117,7 +117,7 @@ void mmu_init(void) | |||
117 | write_c0_pagemask(DEFAULT_PAGE_MASK); | 117 | write_c0_pagemask(DEFAULT_PAGE_MASK); |
118 | write_c0_wired(0); | 118 | write_c0_wired(0); |
119 | write_c0_framemask(0); | 119 | write_c0_framemask(0); |
120 | 120 | ||
121 | local_flush_tlb_all(); | 121 | local_flush_tlb_all(); |
122 | /* | 122 | /* |
123 | map_address(0x80000000, 0x80000000, 0x4000, K_CacheAttrC); | 123 | map_address(0x80000000, 0x80000000, 0x4000, K_CacheAttrC); |