diff options
Diffstat (limited to 'firmware/target')
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/system-target.h | 32 | ||||
-rw-r--r-- | firmware/target/arm/mmu-arm.c | 30 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/system-target.h | 14 | ||||
-rw-r--r-- | firmware/target/arm/system-pp5002.c | 6 | ||||
-rw-r--r-- | firmware/target/arm/system-pp502x.c | 6 | ||||
-rw-r--r-- | firmware/target/arm/system-target.h | 9 | ||||
-rw-r--r-- | firmware/target/coldfire/system-coldfire.c | 8 | ||||
-rw-r--r-- | firmware/target/coldfire/system-target.h | 9 | ||||
-rw-r--r-- | firmware/target/sh/system-target.h | 2 |
9 files changed, 54 insertions, 62 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-target.h b/firmware/target/arm/imx31/gigabeat-s/system-target.h index ae50ec4c78..921af0ec8b 100644 --- a/firmware/target/arm/imx31/gigabeat-s/system-target.h +++ b/firmware/target/arm/imx31/gigabeat-s/system-target.h | |||
@@ -57,34 +57,12 @@ void imx31_regclr32(volatile uint32_t *reg_p, uint32_t mask); | |||
57 | 57 | ||
58 | #define KDEV_INIT | 58 | #define KDEV_INIT |
59 | 59 | ||
60 | #define HAVE_INVALIDATE_ICACHE | 60 | #define HAVE_CPUCACHE_INVALIDATE |
61 | static inline void invalidate_icache(void) | 61 | #define HAVE_CPUCACHE_FLUSH |
62 | { | ||
63 | asm volatile( | ||
64 | /* Clean and invalidate entire data cache */ | ||
65 | "mcr p15, 0, %0, c7, c14, 0 \n" | ||
66 | /* Invalidate entire instruction cache | ||
67 | * Also flushes the branch target cache */ | ||
68 | "mcr p15, 0, %0, c7, c5, 0 \n" | ||
69 | /* Data synchronization barrier */ | ||
70 | "mcr p15, 0, %0, c7, c10, 4 \n" | ||
71 | /* Flush prefetch buffer */ | ||
72 | "mcr p15, 0, %0, c7, c5, 4 \n" | ||
73 | : : "r"(0) | ||
74 | ); | ||
75 | } | ||
76 | 62 | ||
77 | #define HAVE_FLUSH_ICACHE | 63 | /* Different internal names */ |
78 | static inline void flush_icache(void) | 64 | #define cpucache_flush clean_dcache |
79 | { | 65 | #define cpucache_invalidate invalidate_idcache |
80 | asm volatile ( | ||
81 | /* Clean entire data cache */ | ||
82 | "mcr p15, 0, %0, c7, c10, 0 \n" | ||
83 | /* Data synchronization barrier */ | ||
84 | "mcr p15, 0, %0, c7, c10, 4 \n" | ||
85 | : : "r"(0) | ||
86 | ); | ||
87 | } | ||
88 | 66 | ||
89 | struct ARM_REGS { | 67 | struct ARM_REGS { |
90 | int r0; | 68 | int r0; |
diff --git a/firmware/target/arm/mmu-arm.c b/firmware/target/arm/mmu-arm.c index d86cd430b5..fae7fd0b8f 100644 --- a/firmware/target/arm/mmu-arm.c +++ b/firmware/target/arm/mmu-arm.c | |||
@@ -265,6 +265,8 @@ void __attribute__((naked)) clean_dcache(void) | |||
265 | /* Clean entire data cache */ | 265 | /* Clean entire data cache */ |
266 | "mov r0, #0 \n" | 266 | "mov r0, #0 \n" |
267 | "mcr p15, 0, r0, c7, c10, 0 \n" | 267 | "mcr p15, 0, r0, c7, c10, 0 \n" |
268 | /* Data synchronization barrier */ | ||
269 | "mcr p15, 0, r0, c7, c10, 4 \n" | ||
268 | "bx lr \n" | 270 | "bx lr \n" |
269 | ); | 271 | ); |
270 | } | 272 | } |
@@ -290,3 +292,31 @@ void clean_dcache(void) | |||
290 | } | 292 | } |
291 | #endif | 293 | #endif |
292 | 294 | ||
295 | #if CONFIG_CPU == IMX31L | ||
296 | void invalidate_idcache(void) | ||
297 | { | ||
298 | asm volatile( | ||
299 | /* Clean and invalidate entire data cache */ | ||
300 | "mcr p15, 0, %0, c7, c14, 0 \n" | ||
301 | /* Invalidate entire instruction cache | ||
302 | * Also flushes the branch target cache */ | ||
303 | "mcr p15, 0, %0, c7, c5, 0 \n" | ||
304 | /* Data synchronization barrier */ | ||
305 | "mcr p15, 0, %0, c7, c10, 4 \n" | ||
306 | /* Flush prefetch buffer */ | ||
307 | "mcr p15, 0, %0, c7, c5, 4 \n" | ||
308 | : : "r"(0) | ||
309 | ); | ||
310 | } | ||
311 | #else | ||
312 | void invalidate_idcache(void) | ||
313 | { | ||
314 | clean_dcache(); | ||
315 | asm volatile( | ||
316 | "mov r0, #0 \n" | ||
317 | "mcr p15, 0, r0, c7, c5, 0 \n" | ||
318 | : : : "r0" | ||
319 | ); | ||
320 | } | ||
321 | #endif | ||
322 | |||
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h b/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h index 320c595b99..aa7c0aa50c 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h +++ b/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h | |||
@@ -41,15 +41,9 @@ void s3c_regset32(volatile unsigned long *reg, unsigned long bits); | |||
41 | /* Clear register bits */ | 41 | /* Clear register bits */ |
42 | void s3c_regclr32(volatile unsigned long *reg, unsigned long bits); | 42 | void s3c_regclr32(volatile unsigned long *reg, unsigned long bits); |
43 | 43 | ||
44 | #define HAVE_INVALIDATE_ICACHE | 44 | #define HAVE_CPUCACHE_FLUSH |
45 | static inline void invalidate_icache(void) | 45 | #define HAVE_CPUCACHE_INVALIDATE |
46 | { | 46 | #define cpucache_flush clean_dcache |
47 | clean_dcache(); | 47 | #define cpucache_invalidate invalidate_idcache |
48 | asm volatile( | ||
49 | "mov r0, #0 \n" | ||
50 | "mcr p15, 0, r0, c7, c5, 0 \n" | ||
51 | : : : "r0" | ||
52 | ); | ||
53 | } | ||
54 | 48 | ||
55 | #endif /* SYSTEM_TARGET_H */ | 49 | #endif /* SYSTEM_TARGET_H */ |
diff --git a/firmware/target/arm/system-pp5002.c b/firmware/target/arm/system-pp5002.c index a995a5464b..98bf5f21f1 100644 --- a/firmware/target/arm/system-pp5002.c +++ b/firmware/target/arm/system-pp5002.c | |||
@@ -62,8 +62,7 @@ void __attribute__((interrupt("IRQ"))) irq_handler(void) | |||
62 | some other CPU frequency scaling. */ | 62 | some other CPU frequency scaling. */ |
63 | 63 | ||
64 | #ifndef BOOTLOADER | 64 | #ifndef BOOTLOADER |
65 | void flush_icache(void) ICODE_ATTR; | 65 | void ICODE_ATTR cpucache_flush(void) |
66 | void flush_icache(void) | ||
67 | { | 66 | { |
68 | intptr_t b, e; | 67 | intptr_t b, e; |
69 | 68 | ||
@@ -73,8 +72,7 @@ void flush_icache(void) | |||
73 | } | 72 | } |
74 | } | 73 | } |
75 | 74 | ||
76 | void invalidate_icache(void) ICODE_ATTR; | 75 | void ICODE_ATTR cpucache_invalidate(void) |
77 | void invalidate_icache(void) | ||
78 | { | 76 | { |
79 | intptr_t b, e; | 77 | intptr_t b, e; |
80 | 78 | ||
diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c index b1cef7152a..10a7651f7b 100644 --- a/firmware/target/arm/system-pp502x.c +++ b/firmware/target/arm/system-pp502x.c | |||
@@ -163,8 +163,7 @@ void __attribute__((interrupt("IRQ"))) irq_handler(void) | |||
163 | to extend the funtions to do alternate cache configurations. */ | 163 | to extend the funtions to do alternate cache configurations. */ |
164 | 164 | ||
165 | #ifndef BOOTLOADER | 165 | #ifndef BOOTLOADER |
166 | void flush_icache(void) ICODE_ATTR; | 166 | void ICODE_ATTR cpucache_flush(void) |
167 | void flush_icache(void) | ||
168 | { | 167 | { |
169 | if (CACHE_CTL & CACHE_CTL_ENABLE) | 168 | if (CACHE_CTL & CACHE_CTL_ENABLE) |
170 | { | 169 | { |
@@ -173,8 +172,7 @@ void flush_icache(void) | |||
173 | } | 172 | } |
174 | } | 173 | } |
175 | 174 | ||
176 | void invalidate_icache(void) ICODE_ATTR; | 175 | void ICODE_ATTR cpucache_invalidate(void) |
177 | void invalidate_icache(void) | ||
178 | { | 176 | { |
179 | if (CACHE_CTL & CACHE_CTL_ENABLE) | 177 | if (CACHE_CTL & CACHE_CTL_ENABLE) |
180 | { | 178 | { |
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h index 4719b8c971..60844e0b5f 100644 --- a/firmware/target/arm/system-target.h +++ b/firmware/target/arm/system-target.h | |||
@@ -168,13 +168,8 @@ static inline void wake_core(int core) | |||
168 | 168 | ||
169 | /** cache functions **/ | 169 | /** cache functions **/ |
170 | #ifndef BOOTLOADER | 170 | #ifndef BOOTLOADER |
171 | #define CACHE_FUNCTIONS_AS_CALL | 171 | #define HAVE_CPUCACHE_INVALIDATE |
172 | 172 | #define HAVE_CPUCACHE_FLUSH | |
173 | #define HAVE_INVALIDATE_ICACHE | ||
174 | void invalidate_icache(void); | ||
175 | |||
176 | #define HAVE_FLUSH_ICACHE | ||
177 | void flush_icache(void); | ||
178 | #endif | 173 | #endif |
179 | 174 | ||
180 | #endif /* CPU_PP */ | 175 | #endif /* CPU_PP */ |
diff --git a/firmware/target/coldfire/system-coldfire.c b/firmware/target/coldfire/system-coldfire.c index c4651a3c80..a96cd34441 100644 --- a/firmware/target/coldfire/system-coldfire.c +++ b/firmware/target/coldfire/system-coldfire.c | |||
@@ -358,3 +358,11 @@ void coldfire_set_dataincontrol(unsigned long value) | |||
358 | DATAINCONTROL = (DATAINCONTROL & (1 << 9)) | value; | 358 | DATAINCONTROL = (DATAINCONTROL & (1 << 9)) | value; |
359 | restore_irq(level); | 359 | restore_irq(level); |
360 | } | 360 | } |
361 | |||
362 | void cpucache_invalidate(void) | ||
363 | { | ||
364 | asm volatile ("move.l #0x01000000,%d0\n" | ||
365 | "movec.l %d0,%cacr\n" | ||
366 | "move.l #0x80000000,%d0\n" | ||
367 | "movec.l %d0,%cacr"); | ||
368 | } | ||
diff --git a/firmware/target/coldfire/system-target.h b/firmware/target/coldfire/system-target.h index 9c349b1436..347d8e13dc 100644 --- a/firmware/target/coldfire/system-target.h +++ b/firmware/target/coldfire/system-target.h | |||
@@ -194,14 +194,7 @@ static inline uint32_t swap_odd_even32(uint32_t value) | |||
194 | return value; | 194 | return value; |
195 | } | 195 | } |
196 | 196 | ||
197 | #define HAVE_INVALIDATE_ICACHE | 197 | #define HAVE_CPUCACHE_INVALIDATE |
198 | static inline void invalidate_icache(void) | ||
199 | { | ||
200 | asm volatile ("move.l #0x01000000,%d0\n" | ||
201 | "movec.l %d0,%cacr\n" | ||
202 | "move.l #0x80000000,%d0\n" | ||
203 | "movec.l %d0,%cacr"); | ||
204 | } | ||
205 | 198 | ||
206 | #define DEFAULT_PLLCR_AUDIO_BITS 0x10400000 | 199 | #define DEFAULT_PLLCR_AUDIO_BITS 0x10400000 |
207 | void coldfire_set_pllcr_audio_bits(long bits); | 200 | void coldfire_set_pllcr_audio_bits(long bits); |
diff --git a/firmware/target/sh/system-target.h b/firmware/target/sh/system-target.h index aaf6c6bb2d..3c225fbb69 100644 --- a/firmware/target/sh/system-target.h +++ b/firmware/target/sh/system-target.h | |||
@@ -126,6 +126,4 @@ static inline uint32_t swap_odd_even32(uint32_t value) | |||
126 | return value; | 126 | return value; |
127 | } | 127 | } |
128 | 128 | ||
129 | #define invalidate_icache() | ||
130 | |||
131 | #endif /* SYSTEM_TARGET_H */ | 129 | #endif /* SYSTEM_TARGET_H */ |