2 files changed, 4 insertions, 4 deletions

diff --git a/firmware/target/coldfire/crt0.S b/firmware/target/coldfire/crt0.S
index c177cd4e27..215ccfe432 100644
--- a/firmware/target/coldfire/crt0.S
+++ b/firmware/target/coldfire/crt0.S
@@ -78,7 +78,7 @@ start:
     move.l  %d0,(0x0a0,%a0) /* wait states are handled by the coldfire
                              * IDE interface logic. */
 
-#if CONFIG_USBOTG == USBOTG_ISP1362
+#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362
     /* Chip select 3 - USBOTG controller */
     move.l  #0xc0000000,%d0 /* CSAR3 - Base = 0xc0000000 */
     move.l  %d0,(0x0a4,%a0)
diff --git a/firmware/target/coldfire/iriver/system-iriver.c b/firmware/target/coldfire/iriver/system-iriver.c
index 32fc44f963..1cb0a502be 100644
--- a/firmware/target/coldfire/iriver/system-iriver.c
+++ b/firmware/target/coldfire/iriver/system-iriver.c
@@ -85,7 +85,7 @@ void set_cpu_frequency(long frequency)
         PLLCR = 0x018ae025 | (PLLCR & 0x70400000);
         CSCR0 = 0x00001180; /* Flash: 4 wait states */
         CSCR1 = 0x00001580; /* LCD: 5 wait states */
-#if CONFIG_USBOTG == USBOTG_ISP1362
+#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362
         CSCR3 = 0x00002180; /* USBOTG: 8 wait states */
 #endif
         while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@@ -112,7 +112,7 @@ void set_cpu_frequency(long frequency)
         PLLCR = 0x038be025 | (PLLCR & 0x70400000);
         CSCR0 = 0x00000580; /* Flash: 1 wait state */
         CSCR1 = 0x00000180; /* LCD: 0 wait states */
-#if CONFIG_USBOTG == USBOTG_ISP1362
+#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362
         CSCR3 = 0x00000580; /* USBOTG: 1 wait state */
 #endif
         while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@@ -139,7 +139,7 @@ void set_cpu_frequency(long frequency)
         PLLCR = 0x00800200 | (PLLCR & 0x70400000);
         CSCR0 = 0x00000180; /* Flash: 0 wait states */
         CSCR1 = 0x00000180; /* LCD: 0 wait states */
-#if CONFIG_USBOTG == USBOTG_ISP1362
+#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362
         CSCR3 = 0x00000180; /* USBOTG: 0 wait states */
 #endif
         DCR = (0x8000 | DEFAULT_REFRESH_TIMER);       /* Refresh timer */