diff options
Diffstat (limited to 'firmware/target')
-rw-r--r-- | firmware/target/arm/adc-pp5020.c | 2 | ||||
-rw-r--r-- | firmware/target/arm/ipod/backlight-4g_color.c | 2 | ||||
-rw-r--r-- | firmware/target/arm/ipod/button-clickwheel.c | 97 | ||||
-rw-r--r-- | firmware/target/arm/ipod/power-ipod.c | 12 | ||||
-rw-r--r-- | firmware/target/arm/ipod/powermgmt-ipod-pcf.c | 4 | ||||
-rw-r--r-- | firmware/target/arm/system-pp502x.c | 230 | ||||
-rw-r--r-- | firmware/target/arm/usb-fw-pp502x.c | 46 | ||||
-rw-r--r-- | firmware/target/arm/wmcodec-pp.c | 8 |
8 files changed, 246 insertions, 155 deletions
diff --git a/firmware/target/arm/adc-pp5020.c b/firmware/target/arm/adc-pp5020.c index 616ef04861..7ce5ac7011 100644 --- a/firmware/target/arm/adc-pp5020.c +++ b/firmware/target/arm/adc-pp5020.c | |||
@@ -119,6 +119,7 @@ void adc_init(void) | |||
119 | ADC_ADDR |= 0x2000000; | 119 | ADC_ADDR |= 0x2000000; |
120 | ADC_STATUS |= 0x2000; | 120 | ADC_STATUS |= 0x2000; |
121 | 121 | ||
122 | #if defined (IRIVER_H10) || defined(IRIVER_H10_5GB) | ||
122 | /* Enable channel 2 (H10:remote) */ | 123 | /* Enable channel 2 (H10:remote) */ |
123 | DEV_INIT1 &=~0x300; | 124 | DEV_INIT1 &=~0x300; |
124 | DEV_INIT1 |= 0x100; | 125 | DEV_INIT1 |= 0x100; |
@@ -130,6 +131,7 @@ void adc_init(void) | |||
130 | DEV_INIT1 |= 0x1000; | 131 | DEV_INIT1 |= 0x1000; |
131 | ADC_ADDR |= 0x8000000; | 132 | ADC_ADDR |= 0x8000000; |
132 | ADC_STATUS |= 0x20000000; | 133 | ADC_STATUS |= 0x20000000; |
134 | #endif | ||
133 | 135 | ||
134 | /* Force a scan of all channels to get initial values */ | 136 | /* Force a scan of all channels to get initial values */ |
135 | adc_scan(0); | 137 | adc_scan(0); |
diff --git a/firmware/target/arm/ipod/backlight-4g_color.c b/firmware/target/arm/ipod/backlight-4g_color.c index 982bfd53ac..4e46546ef6 100644 --- a/firmware/target/arm/ipod/backlight-4g_color.c +++ b/firmware/target/arm/ipod/backlight-4g_color.c | |||
@@ -53,7 +53,7 @@ bool _backlight_init(void) | |||
53 | GPIOB_ENABLE |= 0x8; /* B03 enable */ | 53 | GPIOB_ENABLE |= 0x8; /* B03 enable */ |
54 | GPO32_ENABLE |= 0x2000000; /* D01 enable */ | 54 | GPO32_ENABLE |= 0x2000000; /* D01 enable */ |
55 | GPO32_VAL |= 0x2000000; /* D01 =1 */ | 55 | GPO32_VAL |= 0x2000000; /* D01 =1 */ |
56 | DEV_EN |= 0x20000; /* PWM enable */ | 56 | DEV_EN |= DEV_PWM; /* PWM enable */ |
57 | 57 | ||
58 | _backlight_on(); | 58 | _backlight_on(); |
59 | return true; | 59 | return true; |
diff --git a/firmware/target/arm/ipod/button-clickwheel.c b/firmware/target/arm/ipod/button-clickwheel.c index f01666a8b8..f8dd818a01 100644 --- a/firmware/target/arm/ipod/button-clickwheel.c +++ b/firmware/target/arm/ipod/button-clickwheel.c | |||
@@ -73,64 +73,40 @@ int int_btn = BUTTON_NONE; | |||
73 | 73 | ||
74 | static void opto_i2c_init(void) | 74 | static void opto_i2c_init(void) |
75 | { | 75 | { |
76 | int i, curr_value; | 76 | DEV_EN |= DEV_OPTO; |
77 | 77 | DEV_RS |= DEV_OPTO; | |
78 | /* wait for value to settle */ | ||
79 | i = 1000; | ||
80 | curr_value = (inl(0x7000c104) << 16) >> 24; | ||
81 | while (i > 0) | ||
82 | { | ||
83 | int new_value = (inl(0x7000c104) << 16) >> 24; | ||
84 | |||
85 | if (new_value != curr_value) { | ||
86 | i = 10000; | ||
87 | curr_value = new_value; | ||
88 | } | ||
89 | else { | ||
90 | i--; | ||
91 | } | ||
92 | } | ||
93 | |||
94 | GPIOB_OUTPUT_VAL |= 0x10; | ||
95 | DEV_EN |= 0x10000; | ||
96 | DEV_RS |= 0x10000; | ||
97 | udelay(5); | 78 | udelay(5); |
98 | DEV_RS &= ~0x10000; /* finish reset */ | 79 | DEV_RS &= ~DEV_OPTO; /* finish reset */ |
80 | DEV_INIT1 |= INIT_BUTTONS; /* enable buttons (needed for "hold"-detection) */ | ||
99 | 81 | ||
100 | outl(0xffffffff, 0x7000c120); | ||
101 | outl(0xffffffff, 0x7000c124); | ||
102 | outl(0xc00a1f00, 0x7000c100); | 82 | outl(0xc00a1f00, 0x7000c100); |
103 | outl(0x1000000, 0x7000c104); | 83 | outl(0x01000000, 0x7000c104); |
104 | } | 84 | } |
105 | 85 | ||
106 | static inline int ipod_4g_button_read(void) | 86 | static inline int ipod_4g_button_read(void) |
107 | { | 87 | { |
108 | int whl = -1; | 88 | int whl = -1; |
89 | int btn = BUTTON_NONE; | ||
109 | 90 | ||
110 | /* The ipodlinux source had a udelay(250) here, but testing has shown that | 91 | /* The following delay was 250 in the ipodlinux source, but 50 seems to |
111 | it is not needed - tested on Nano, Color/Photo and Video. */ | 92 | work fine - tested on Nano, Color/Photo and Video. */ |
112 | /* udelay(250);*/ | 93 | udelay(50); |
113 | 94 | ||
114 | int btn = BUTTON_NONE; | 95 | if ((inl(0x7000c104) & 0x04000000) != 0) |
115 | unsigned reg = 0x7000c104; | ||
116 | if ((inl(0x7000c104) & 0x4000000) != 0) | ||
117 | { | 96 | { |
118 | unsigned status = inl(0x7000c140); | 97 | unsigned status = inl(0x7000c140); |
119 | 98 | ||
120 | reg = reg + 0x3C; /* 0x7000c140 */ | ||
121 | outl(0x0, 0x7000c140); /* clear interrupt status? */ | ||
122 | |||
123 | if ((status & 0x800000ff) == 0x8000001a) | 99 | if ((status & 0x800000ff) == 0x8000001a) |
124 | { | 100 | { |
125 | if (status & 0x100) | 101 | if (status & 0x00000100) |
126 | btn |= BUTTON_SELECT; | 102 | btn |= BUTTON_SELECT; |
127 | if (status & 0x200) | 103 | if (status & 0x00000200) |
128 | btn |= BUTTON_RIGHT; | 104 | btn |= BUTTON_RIGHT; |
129 | if (status & 0x400) | 105 | if (status & 0x00000400) |
130 | btn |= BUTTON_LEFT; | 106 | btn |= BUTTON_LEFT; |
131 | if (status & 0x800) | 107 | if (status & 0x00000800) |
132 | btn |= BUTTON_PLAY; | 108 | btn |= BUTTON_PLAY; |
133 | if (status & 0x1000) | 109 | if (status & 0x00001000) |
134 | btn |= BUTTON_MENU; | 110 | btn |= BUTTON_MENU; |
135 | if (status & 0x40000000) | 111 | if (status & 0x40000000) |
136 | { | 112 | { |
@@ -263,19 +239,10 @@ static inline int ipod_4g_button_read(void) | |||
263 | } | 239 | } |
264 | 240 | ||
265 | } | 241 | } |
266 | else if (status == 0xffffffff) | ||
267 | { | ||
268 | opto_i2c_init(); | ||
269 | } | ||
270 | } | 242 | } |
271 | 243 | ||
272 | if ((inl(reg) & 0x8000000) != 0) | ||
273 | { | ||
274 | outl(0xffffffff, 0x7000c120); | ||
275 | outl(0xffffffff, 0x7000c124); | ||
276 | } | ||
277 | /* Save the new absolute wheel position */ | ||
278 | #ifdef HAVE_WHEEL_POSITION | 244 | #ifdef HAVE_WHEEL_POSITION |
245 | /* Save the new absolute wheel position */ | ||
279 | wheel_position = whl; | 246 | wheel_position = whl; |
280 | #endif | 247 | #endif |
281 | return btn; | 248 | return btn; |
@@ -296,16 +263,12 @@ void wheel_send_events(bool send) | |||
296 | void ipod_4g_button_int(void) | 263 | void ipod_4g_button_int(void) |
297 | { | 264 | { |
298 | CPU_HI_INT_CLR = I2C_MASK; | 265 | CPU_HI_INT_CLR = I2C_MASK; |
299 | /* The following delay was 250 in the ipodlinux source, but 50 seems to | 266 | |
300 | work fine - tested on Nano, Color/Photo and Video. */ | ||
301 | udelay(50); | ||
302 | outl(0x0, 0x7000c140); | ||
303 | int_btn = ipod_4g_button_read(); | 267 | int_btn = ipod_4g_button_read(); |
304 | outl(inl(0x7000c104) | 0xC000000, 0x7000c104); | 268 | |
269 | outl(inl(0x7000c104) | 0x0c000000, 0x7000c104); | ||
305 | outl(0x400a1f00, 0x7000c100); | 270 | outl(0x400a1f00, 0x7000c100); |
306 | 271 | ||
307 | GPIOB_OUTPUT_VAL |= 0x10; | ||
308 | CPU_INT_EN = 0x40000000; | ||
309 | CPU_HI_INT_EN = I2C_MASK; | 272 | CPU_HI_INT_EN = I2C_MASK; |
310 | } | 273 | } |
311 | 274 | ||
@@ -317,15 +280,8 @@ void button_init_device(void) | |||
317 | GPIOA_ENABLE |= 0x20; | 280 | GPIOA_ENABLE |= 0x20; |
318 | GPIOA_OUTPUT_EN &= ~0x20; | 281 | GPIOA_OUTPUT_EN &= ~0x20; |
319 | 282 | ||
320 | /* hold button - set interrupt levels */ | ||
321 | GPIOA_INT_LEV = ~(GPIOA_INPUT_VAL & 0x20); | ||
322 | GPIOA_INT_CLR = GPIOA_INT_STAT & 0x20; | ||
323 | |||
324 | /* enable interrupts */ | ||
325 | GPIOA_INT_EN = 0x20; | ||
326 | |||
327 | /* unmask interrupt */ | 283 | /* unmask interrupt */ |
328 | CPU_INT_EN = 0x40000000; | 284 | CPU_INT_EN = HI_MASK; |
329 | CPU_HI_INT_EN = I2C_MASK; | 285 | CPU_HI_INT_EN = I2C_MASK; |
330 | } | 286 | } |
331 | 287 | ||
@@ -342,7 +298,20 @@ int button_read_device(void) | |||
342 | hold_button = button_hold(); | 298 | hold_button = button_hold(); |
343 | 299 | ||
344 | if (hold_button != hold_button_old) | 300 | if (hold_button != hold_button_old) |
301 | { | ||
345 | backlight_hold_changed(hold_button); | 302 | backlight_hold_changed(hold_button); |
303 | |||
304 | if (hold_button) | ||
305 | { | ||
306 | /* lock -> disable wheel sensor */ | ||
307 | DEV_EN &= ~DEV_OPTO; | ||
308 | } | ||
309 | else | ||
310 | { | ||
311 | /* unlock -> enable wheel sensor */ | ||
312 | DEV_EN |= DEV_OPTO; | ||
313 | } | ||
314 | } | ||
346 | 315 | ||
347 | /* The int_btn variable is set in the button interrupt handler */ | 316 | /* The int_btn variable is set in the button interrupt handler */ |
348 | return int_btn; | 317 | return int_btn; |
diff --git a/firmware/target/arm/ipod/power-ipod.c b/firmware/target/arm/ipod/power-ipod.c index 4c6f6a8db5..475e55c732 100644 --- a/firmware/target/arm/ipod/power-ipod.c +++ b/firmware/target/arm/ipod/power-ipod.c | |||
@@ -70,14 +70,26 @@ void ide_power_enable(bool on) | |||
70 | #elif defined(IPOD_4G) || defined(IPOD_COLOR) \ | 70 | #elif defined(IPOD_4G) || defined(IPOD_COLOR) \ |
71 | || defined(IPOD_MINI) || defined(IPOD_MINI2G) | 71 | || defined(IPOD_MINI) || defined(IPOD_MINI2G) |
72 | if (on) | 72 | if (on) |
73 | { | ||
73 | GPIO_CLEAR_BITWISE(GPIOJ_OUTPUT_VAL, 0x04); | 74 | GPIO_CLEAR_BITWISE(GPIOJ_OUTPUT_VAL, 0x04); |
75 | DEV_EN |= DEV_IDE0; | ||
76 | } | ||
74 | else | 77 | else |
78 | { | ||
79 | DEV_EN &= ~DEV_IDE0; | ||
75 | GPIO_SET_BITWISE(GPIOJ_OUTPUT_VAL, 0x04); | 80 | GPIO_SET_BITWISE(GPIOJ_OUTPUT_VAL, 0x04); |
81 | } | ||
76 | #elif defined(IPOD_VIDEO) | 82 | #elif defined(IPOD_VIDEO) |
77 | if (on) | 83 | if (on) |
84 | { | ||
78 | GPO32_VAL &= ~0x40000000; | 85 | GPO32_VAL &= ~0x40000000; |
86 | DEV_EN |= DEV_IDE0; | ||
87 | } | ||
79 | else | 88 | else |
89 | { | ||
90 | DEV_EN &= ~DEV_IDE0; | ||
80 | GPO32_VAL |= 0x40000000; | 91 | GPO32_VAL |= 0x40000000; |
92 | } | ||
81 | #else /* Nano */ | 93 | #else /* Nano */ |
82 | (void)on; /* Do nothing. */ | 94 | (void)on; /* Do nothing. */ |
83 | #endif | 95 | #endif |
diff --git a/firmware/target/arm/ipod/powermgmt-ipod-pcf.c b/firmware/target/arm/ipod/powermgmt-ipod-pcf.c index d2f88a20f2..aaf4fabf52 100644 --- a/firmware/target/arm/ipod/powermgmt-ipod-pcf.c +++ b/firmware/target/arm/ipod/powermgmt-ipod-pcf.c | |||
@@ -27,7 +27,7 @@ const unsigned short battery_level_dangerous[BATTERY_TYPES_COUNT] = | |||
27 | #ifdef IPOD_NANO | 27 | #ifdef IPOD_NANO |
28 | 3330 | 28 | 3330 |
29 | #elif defined IPOD_VIDEO | 29 | #elif defined IPOD_VIDEO |
30 | 3450 | 30 | 3300 |
31 | #else | 31 | #else |
32 | /* FIXME: calibrate value for other 3G+ ipods */ | 32 | /* FIXME: calibrate value for other 3G+ ipods */ |
33 | 3380 | 33 | 3380 |
@@ -39,7 +39,7 @@ const unsigned short battery_level_shutoff[BATTERY_TYPES_COUNT] = | |||
39 | #ifdef IPOD_NANO | 39 | #ifdef IPOD_NANO |
40 | 3230 | 40 | 3230 |
41 | #elif defined IPOD_VIDEO | 41 | #elif defined IPOD_VIDEO |
42 | 3450 | 42 | 3300 |
43 | #else | 43 | #else |
44 | /* FIXME: calibrate value for other 3G+ ipods */ | 44 | /* FIXME: calibrate value for other 3G+ ipods */ |
45 | 3020 | 45 | 3020 |
diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c index 4ca58208ad..0b5e9e1c13 100644 --- a/firmware/target/arm/system-pp502x.c +++ b/firmware/target/arm/system-pp502x.c | |||
@@ -161,97 +161,118 @@ void set_cpu_frequency(long frequency) | |||
161 | #else | 161 | #else |
162 | static void pp_set_cpu_frequency(long frequency) | 162 | static void pp_set_cpu_frequency(long frequency) |
163 | #endif | 163 | #endif |
164 | { | 164 | { |
165 | #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1) | 165 | #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1) |
166 | spinlock_lock(&boostctrl_spin); | 166 | spinlock_lock(&boostctrl_spin); |
167 | #endif | 167 | #endif |
168 | 168 | ||
169 | scale_suspend_core(true); | ||
170 | |||
171 | cpu_frequency = frequency; | ||
172 | |||
173 | switch (frequency) | 169 | switch (frequency) |
174 | { | 170 | { |
175 | /* Note: The PP5022 PLL must be run at >= 96MHz | 171 | /* Note1: The PP5022 PLL must be run at >= 96MHz |
176 | * Bits 20..21 select the post divider (1/2/4/8). | 172 | * Bits 20..21 select the post divider (1/2/4/8). |
177 | * PP5026 is similar to PP5022 except it doesn't | 173 | * PP5026 is similar to PP5022 except it doesn't |
178 | * have this limitation (and the post divider?) */ | 174 | * have this limitation (and the post divider?) |
175 | * Note2: CLOCK_SOURCE is set via 0=32kHz, 1=16MHz, | ||
176 | * 2=24MHz, 3=33MHz, 4=48MHz, 5=SLOW, 6=FAST, 7=PLL. | ||
177 | * SLOW = 24MHz / (DIV_SLOW + 1), DIV = Bits 16-19 | ||
178 | * FAST = PLL / (DIV_FAST + 1), DIV = Bits 20-23 */ | ||
179 | case CPUFREQ_SLEEP: | ||
180 | cpu_frequency = CPUFREQ_SLEEP; | ||
181 | PLL_CONTROL |= 0x0c000000; | ||
182 | scale_suspend_core(true); | ||
183 | CLOCK_SOURCE = 0x20000000; /* source #1, #2, #3, #4: 32kHz (#2 active) */ | ||
184 | scale_suspend_core(false); | ||
185 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ | ||
186 | DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */ | ||
187 | break; | ||
188 | |||
179 | case CPUFREQ_MAX: | 189 | case CPUFREQ_MAX: |
180 | CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ | 190 | cpu_frequency = CPUFREQ_MAX; |
181 | DEV_TIMING1 = 0x00000303; | 191 | DEV_INIT2 |= INIT_PLL; /* enable PLL power */ |
182 | #ifdef IPOD_NANO | 192 | PLL_CONTROL |= 0x88000000; /* enable PLL */ |
183 | IDE0_CFG |= (0x10000000); /* Set CPU > 65MHz bit */ | 193 | scale_suspend_core(true); |
184 | #endif | 194 | CLOCK_SOURCE = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */ |
185 | #ifdef IPOD_MINI2G | 195 | DEV_TIMING1 = 0x00000303; |
196 | scale_suspend_core(false); | ||
197 | #if defined(IPOD_MINI2G) | ||
186 | MLCD_SCLK_DIV = 0x00000001; /* Mono LCD bridge serial clock divider */ | 198 | MLCD_SCLK_DIV = 0x00000001; /* Mono LCD bridge serial clock divider */ |
199 | #elif defined(IPOD_NANO) | ||
200 | IDE0_CFG |= 0x10000000; /* set ">65MHz" bit */ | ||
187 | #endif | 201 | #endif |
188 | #if CONFIG_CPU == PP5020 | 202 | #if CONFIG_CPU == PP5020 |
189 | PLL_CONTROL = 0x8a020a03; /* 10/3 * 24MHz */ | 203 | PLL_CONTROL = 0x8a020a03; /* 80 MHz = 10/3 * 24MHz */ |
190 | PLL_STATUS = 0xd19b; /* unlock frequencies > 66MHz */ | 204 | PLL_STATUS = 0xd19b; /* unlock frequencies > 66MHz */ |
191 | PLL_CONTROL = 0x8a020a03; /* repeat setup */ | 205 | PLL_CONTROL = 0x8a020a03; /* repeat setup */ |
192 | scale_suspend_core(false); | ||
193 | udelay(500); /* wait for relock */ | 206 | udelay(500); /* wait for relock */ |
194 | #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024) | 207 | #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024) |
195 | PLL_CONTROL = 0x8a121403; /* (20/3 * 24MHz) / 2 */ | 208 | PLL_CONTROL = 0x8a121403; /* 80 MHz = (20/3 * 24MHz) / 2 */ |
196 | scale_suspend_core(false); | ||
197 | udelay(250); | ||
198 | while (!(PLL_STATUS & 0x80000000)); /* wait for relock */ | 209 | while (!(PLL_STATUS & 0x80000000)); /* wait for relock */ |
199 | #endif | 210 | #endif |
200 | scale_suspend_core(true); | 211 | scale_suspend_core(true); |
212 | DEV_TIMING1 = 0x00000808; | ||
213 | CLOCK_SOURCE = 0x20007777; /* source #1, #2, #3, #4: PLL (#2 active) */ | ||
214 | scale_suspend_core(false); | ||
201 | break; | 215 | break; |
202 | 216 | #if 0 /******** CPUFREQ_NORMAL = 24MHz without PLL ********/ | |
203 | case CPUFREQ_NORMAL: | 217 | case CPUFREQ_NORMAL: |
204 | CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ | 218 | cpu_frequency = CPUFREQ_NORMAL; |
205 | DEV_TIMING1 = 0x00000303; | 219 | PLL_CONTROL |= 0x08000000; |
206 | #ifdef IPOD_NANO | 220 | scale_suspend_core(true); |
207 | IDE0_CFG &=~(0x10000000); /* clear > 65MHz bit */ | 221 | CLOCK_SOURCE = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */ |
222 | DEV_TIMING1 = 0x00000303; | ||
223 | #if defined(IPOD_MINI2G) | ||
224 | MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */ | ||
225 | #elif defined(IPOD_NANO) | ||
226 | IDE0_CFG &= ~0x10000000; /* clear ">65MHz" bit */ | ||
208 | #endif | 227 | #endif |
209 | #ifdef IPOD_MINI2G | 228 | scale_suspend_core(false); |
210 | MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */ | 229 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ |
230 | DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */ | ||
231 | break; | ||
232 | #else /******** CPUFREQ_NORMAL = 30MHz with PLL ********/ | ||
233 | case CPUFREQ_NORMAL: | ||
234 | cpu_frequency = CPUFREQ_NORMAL; | ||
235 | DEV_INIT2 |= INIT_PLL; /* enable PLL power */ | ||
236 | PLL_CONTROL |= 0x88000000; /* enable PLL */ | ||
237 | scale_suspend_core(true); | ||
238 | CLOCK_SOURCE = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */ | ||
239 | DEV_TIMING1 = 0x00000303; | ||
240 | scale_suspend_core(false); | ||
241 | #if defined(IPOD_MINI2G) | ||
242 | MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */ | ||
243 | #elif defined(IPOD_NANO) | ||
244 | IDE0_CFG &= ~0x10000000; /* clear ">65MHz" bit */ | ||
211 | #endif | 245 | #endif |
212 | #if CONFIG_CPU == PP5020 | 246 | #if CONFIG_CPU == PP5020 |
213 | PLL_CONTROL = 0x8a020504; /* 5/4 * 24MHz */ | 247 | PLL_CONTROL = 0x8a020504; /* 30 MHz = 5/4 * 24MHz */ |
214 | scale_suspend_core(false); | ||
215 | udelay(500); /* wait for relock */ | 248 | udelay(500); /* wait for relock */ |
216 | #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024) | 249 | #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024) |
217 | PLL_CONTROL = 0x8a220501; /* (5/1 * 24MHz) / 4 */ | 250 | PLL_CONTROL = 0x8a220501; /* 30 MHz = (5/1 * 24MHz) / 4 */ |
218 | scale_suspend_core(false); | ||
219 | udelay(250); | ||
220 | while (!(PLL_STATUS & 0x80000000)); /* wait for relock */ | 251 | while (!(PLL_STATUS & 0x80000000)); /* wait for relock */ |
221 | #endif | 252 | #endif |
222 | scale_suspend_core(true); | 253 | scale_suspend_core(true); |
223 | break; | 254 | DEV_TIMING1 = 0x00000808; |
224 | 255 | CLOCK_SOURCE = 0x20007777; /* source #1, #2, #3, #4: PLL (#2 active) */ | |
225 | case CPUFREQ_SLEEP: | ||
226 | CLOCK_SOURCE = 0x10002202; /* source #2: 32kHz, #1, #3, #4: 24MHz */ | ||
227 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ | ||
228 | scale_suspend_core(false); | 256 | scale_suspend_core(false); |
229 | udelay(10000); /* let 32kHz source stabilize? */ | ||
230 | scale_suspend_core(true); | ||
231 | break; | 257 | break; |
232 | 258 | #endif /******** CPUFREQ_NORMAL end ********/ | |
233 | default: | 259 | default: |
234 | CLOCK_SOURCE = 0x10002222; /* source #1, #2, #3, #4: 24MHz */ | 260 | cpu_frequency = CPUFREQ_DEFAULT; |
235 | DEV_TIMING1 = 0x00000303; | 261 | PLL_CONTROL |= 0x08000000; |
236 | #ifdef IPOD_MINI2G | 262 | scale_suspend_core(true); |
237 | MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */ | 263 | CLOCK_SOURCE = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */ |
238 | #endif | 264 | DEV_TIMING1 = 0x00000303; |
239 | #ifdef IPOD_NANO | 265 | #if defined(IPOD_MINI2G) |
240 | IDE0_CFG &=~(0x10000000); /* clear > 65MHz bit */ | 266 | MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */ |
267 | #elif defined(IPOD_NANO) | ||
268 | IDE0_CFG &= ~0x10000000; /* clear ">65MHz" bit */ | ||
241 | #endif | 269 | #endif |
242 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ | 270 | scale_suspend_core(false); |
243 | cpu_frequency = CPUFREQ_DEFAULT; | 271 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ |
244 | PROC_CTL(CURRENT_CORE) = 0x4800001f; nop; | 272 | DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */ |
245 | break; | 273 | break; |
246 | } | 274 | } |
247 | 275 | ||
248 | if (frequency == CPUFREQ_MAX) | ||
249 | DEV_TIMING1 = 0x00000808; | ||
250 | |||
251 | CLOCK_SOURCE = (CLOCK_SOURCE & ~0xf0000000) | 0x20000000; /* select source #2 */ | ||
252 | |||
253 | scale_suspend_core(false); | ||
254 | |||
255 | #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1) | 276 | #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1) |
256 | spinlock_unlock(&boostctrl_spin); | 277 | spinlock_unlock(&boostctrl_spin); |
257 | #endif | 278 | #endif |
@@ -263,19 +284,84 @@ void system_init(void) | |||
263 | #ifndef BOOTLOADER | 284 | #ifndef BOOTLOADER |
264 | if (CURRENT_CORE == CPU) | 285 | if (CURRENT_CORE == CPU) |
265 | { | 286 | { |
266 | #if defined(SANSA_E200) || defined(SANSA_C200) | 287 | #if defined (IRIVER_H10) || defined(IRIVER_H10_5GB) || defined(IPOD_COLOR) |
267 | /* Reset all devices */ | 288 | /* set minimum startup configuration */ |
268 | DEV_RS2 |= 0x20; | 289 | DEV_EN = 0xc2000124; |
269 | DEV_RS = 0x3bfffef8; | 290 | DEV_EN2 = 0x00002000; |
270 | DEV_RS2 = -1; | 291 | CACHE_PRIORITY = 0x0000003f; |
271 | DEV_RS = 0; | 292 | GPO32_VAL = 0x20000000; |
272 | DEV_RS2 = 0; | 293 | DEV_INIT1 = 0xdc000000; |
273 | #elif defined (IRIVER_H10) || defined(MROBE_100) | 294 | DEV_INIT2 = 0x40000000; |
274 | DEV_RS = 0x3ffffef8; | 295 | |
275 | DEV_RS2 = -1; | 296 | /* reset all allowed devices */ |
276 | DEV_RS = 0; | 297 | DEV_RS = 0x3ffffef8; |
277 | DEV_RS2 = 0; | 298 | DEV_RS2 = 0xffffdfff; |
278 | outl(inl(0x70000024) | 0xc0, 0x70000024); | 299 | DEV_RS = 0x00000000; |
300 | DEV_RS2 = 0x00000000; | ||
301 | #elif defined (IPOD_VIDEO) | ||
302 | /* set minimum startup configuration */ | ||
303 | DEV_EN = 0xc2000124; | ||
304 | DEV_EN2 = 0x00000000; | ||
305 | CACHE_PRIORITY = 0x0000003f; | ||
306 | GPO32_VAL = 0x00004000; | ||
307 | DEV_INIT1 = 0x00000000; | ||
308 | DEV_INIT2 = 0x40000000; | ||
309 | |||
310 | /* reset all allowed devices */ | ||
311 | DEV_RS = 0x3ffffef8; | ||
312 | DEV_RS2 = 0xffffffff; | ||
313 | DEV_RS = 0x00000000; | ||
314 | DEV_RS2 = 0x00000000; | ||
315 | #elif defined (IPOD_NANO) | ||
316 | /* set minimum startup configuration */ | ||
317 | DEV_EN = 0xc2000124; | ||
318 | DEV_EN2 = 0x00002000; | ||
319 | CACHE_PRIORITY = 0x0000003f; | ||
320 | GPO32_VAL = 0x50000000; | ||
321 | DEV_INIT1 = 0xa8000000; | ||
322 | DEV_INIT2 = 0x40000000; | ||
323 | |||
324 | /* reset all allowed devices */ | ||
325 | DEV_RS = 0x3ffffef8; | ||
326 | DEV_RS2 = 0xffffdfff; | ||
327 | DEV_RS = 0x00000000; | ||
328 | DEV_RS2 = 0x00000000; | ||
329 | #elif defined(SANSA_C200) || defined (SANSA_E200) | ||
330 | /* set minimum startup configuration */ | ||
331 | DEV_EN = 0xc4000124; | ||
332 | DEV_EN2 = 0x00000000; | ||
333 | CACHE_PRIORITY = 0x0000003f; | ||
334 | GPO32_VAL = 0x10000000; | ||
335 | DEV_INIT1 = 0x54000000; | ||
336 | DEV_INIT2 = 0x40000000; | ||
337 | |||
338 | /* reset all allowed devices */ | ||
339 | DEV_RS = 0x3bfffef8; | ||
340 | DEV_RS2 = 0xffffffff; | ||
341 | DEV_RS = 0x00000000; | ||
342 | DEV_RS2 = 0x00000000; | ||
343 | #elif defined(IPOD_4G) | ||
344 | /* set minimum startup configuration */ | ||
345 | DEV_EN = 0xc2020124; | ||
346 | DEV_EN2 = 0x00000000; | ||
347 | CACHE_PRIORITY = 0x0000003f; | ||
348 | GPO32_VAL = 0x02000000; | ||
349 | DEV_INIT1 = 0x00000000; | ||
350 | DEV_INIT2 = 0x40000000; | ||
351 | |||
352 | /* reset all allowed devices */ | ||
353 | DEV_RS = 0x3ffdfef8; | ||
354 | DEV_RS2 = 0xffffffff; | ||
355 | DEV_RS = 0x00000000; | ||
356 | DEV_RS2 = 0x00000000; | ||
357 | #elif defined (IPOD_MINI) | ||
358 | /* to be done */ | ||
359 | #elif defined (IPOD_MINI2G) | ||
360 | /* to be done */ | ||
361 | #elif defined (MROBE_100) | ||
362 | /* to be done */ | ||
363 | #elif defined (ELIO_TPJ1022) | ||
364 | /* to be done */ | ||
279 | #endif | 365 | #endif |
280 | 366 | ||
281 | #if !defined(SANSA_E200) && !defined(SANSA_C200) | 367 | #if !defined(SANSA_E200) && !defined(SANSA_C200) |
@@ -314,8 +400,6 @@ void system_init(void) | |||
314 | outl(inl(0x6000a000) | 0x80000000, 0x6000a000); /* Init DMA controller? */ | 400 | outl(inl(0x6000a000) | 0x80000000, 0x6000a000); /* Init DMA controller? */ |
315 | #endif | 401 | #endif |
316 | 402 | ||
317 | DEV_INIT2 |= 1 << 30; /* enable PLL power */ | ||
318 | |||
319 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ | 403 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ |
320 | #if NUM_CORES > 1 | 404 | #if NUM_CORES > 1 |
321 | cpu_boost_init(); | 405 | cpu_boost_init(); |
diff --git a/firmware/target/arm/usb-fw-pp502x.c b/firmware/target/arm/usb-fw-pp502x.c index 7af699c064..0813ae1c59 100644 --- a/firmware/target/arm/usb-fw-pp502x.c +++ b/firmware/target/arm/usb-fw-pp502x.c | |||
@@ -33,18 +33,29 @@ | |||
33 | void usb_init_device(void) | 33 | void usb_init_device(void) |
34 | { | 34 | { |
35 | /* enable usb module */ | 35 | /* enable usb module */ |
36 | GPO32_ENABLE |= 0x200; | ||
37 | |||
38 | outl(inl(0x7000002C) | 0x3000000, 0x7000002C); | 36 | outl(inl(0x7000002C) | 0x3000000, 0x7000002C); |
39 | DEV_EN |= DEV_USB; | 37 | DEV_EN |= DEV_USB0; |
38 | DEV_EN |= DEV_USB1; | ||
40 | 39 | ||
41 | DEV_RS |= DEV_USB; /* reset usb start */ | 40 | /* reset both USBs */ |
42 | DEV_RS &=~DEV_USB;/* reset usb end */ | 41 | DEV_RS |= DEV_USB0; |
42 | DEV_RS &=~DEV_USB0; | ||
43 | DEV_RS |= DEV_USB1; | ||
44 | DEV_RS &=~DEV_USB1; | ||
43 | 45 | ||
46 | #if CONFIG_CPU == PP5020 | ||
44 | DEV_INIT2 |= INIT_USB; | 47 | DEV_INIT2 |= INIT_USB; |
48 | #endif | ||
45 | while ((inl(0x70000028) & 0x80) == 0); | 49 | while ((inl(0x70000028) & 0x80) == 0); |
46 | outl(inl(0x70000028) | 0x2, 0x70000028); | 50 | outl(inl(0x70000028) | 0x2, 0x70000028); |
47 | udelay(0x186A0); | 51 | udelay(0x186A0); |
52 | |||
53 | /* disable USB-devices until USB is detected via GPIO */ | ||
54 | DEV_EN &= ~DEV_USB0; | ||
55 | DEV_EN &= ~DEV_USB1; | ||
56 | #if CONFIG_CPU == PP5020 | ||
57 | DEV_INIT2 &= ~INIT_USB; | ||
58 | #endif | ||
48 | 59 | ||
49 | #if defined(IPOD_COLOR) || defined(IPOD_4G) \ | 60 | #if defined(IPOD_COLOR) || defined(IPOD_4G) \ |
50 | || defined(IPOD_MINI) || defined(IPOD_MINI2G) | 61 | || defined(IPOD_MINI) || defined(IPOD_MINI2G) |
@@ -85,33 +96,46 @@ void usb_enable(bool on) | |||
85 | 96 | ||
86 | static bool usb_pin_detect(void) | 97 | static bool usb_pin_detect(void) |
87 | { | 98 | { |
99 | bool retval = false; | ||
100 | |||
88 | #if defined(IPOD_4G) || defined(IPOD_COLOR) \ | 101 | #if defined(IPOD_4G) || defined(IPOD_COLOR) \ |
89 | || defined(IPOD_MINI) || defined(IPOD_MINI2G) | 102 | || defined(IPOD_MINI) || defined(IPOD_MINI2G) |
90 | /* GPIO D bit 3 is usb detect */ | 103 | /* GPIO D bit 3 is usb detect */ |
91 | if (GPIOD_INPUT_VAL & 0x08) | 104 | if (GPIOD_INPUT_VAL & 0x08) |
92 | return true; | 105 | retval = true; |
93 | 106 | ||
94 | #elif defined(IPOD_NANO) || defined(IPOD_VIDEO) | 107 | #elif defined(IPOD_NANO) || defined(IPOD_VIDEO) |
95 | /* GPIO L bit 4 is usb detect */ | 108 | /* GPIO L bit 4 is usb detect */ |
96 | if (GPIOL_INPUT_VAL & 0x10) | 109 | if (GPIOL_INPUT_VAL & 0x10) |
97 | return true; | 110 | retval = true; |
98 | 111 | ||
99 | #elif defined(SANSA_C200) | 112 | #elif defined(SANSA_C200) |
100 | /* GPIO H bit 1 is usb detect */ | 113 | /* GPIO H bit 1 is usb detect */ |
101 | if (GPIOH_INPUT_VAL & 0x02) | 114 | if (GPIOH_INPUT_VAL & 0x02) |
102 | return true; | 115 | retval = true; |
103 | 116 | ||
104 | #elif defined(SANSA_E200) | 117 | #elif defined(SANSA_E200) |
105 | /* GPIO B bit 4 is usb detect */ | 118 | /* GPIO B bit 4 is usb detect */ |
106 | if (GPIOB_INPUT_VAL & 0x10) | 119 | if (GPIOB_INPUT_VAL & 0x10) |
107 | return true; | 120 | retval = true; |
108 | 121 | ||
109 | #elif defined(IRIVER_H10) || defined(IRIVER_H10_5GB) | 122 | #elif defined(IRIVER_H10) || defined(IRIVER_H10_5GB) |
110 | /* GPIO L bit 2 is usb detect */ | 123 | /* GPIO L bit 2 is usb detect */ |
111 | if (GPIOL_INPUT_VAL & 0x4) | 124 | if (GPIOL_INPUT_VAL & 0x4) |
112 | return true; | 125 | retval = true; |
113 | #endif | 126 | #endif |
114 | return false; | 127 | |
128 | /* if USB is detected, re-enable the USB-devices */ | ||
129 | if (retval) | ||
130 | { | ||
131 | DEV_EN |= DEV_USB0; | ||
132 | DEV_EN |= DEV_USB1; | ||
133 | #if CONFIG_CPU == PP5020 | ||
134 | DEV_INIT2 |= INIT_USB; | ||
135 | #endif | ||
136 | } | ||
137 | |||
138 | return retval; | ||
115 | } | 139 | } |
116 | 140 | ||
117 | /* detect host or charger (INSERTED or POWERED) */ | 141 | /* detect host or charger (INSERTED or POWERED) */ |
diff --git a/firmware/target/arm/wmcodec-pp.c b/firmware/target/arm/wmcodec-pp.c index c9e034a188..3bd9d7fd2b 100644 --- a/firmware/target/arm/wmcodec-pp.c +++ b/firmware/target/arm/wmcodec-pp.c | |||
@@ -52,15 +52,15 @@ void audiohw_init(void) { | |||
52 | DEV_INIT1 &=~0x3000000; | 52 | DEV_INIT1 &=~0x3000000; |
53 | /*mini2?*/ | 53 | /*mini2?*/ |
54 | 54 | ||
55 | /* device reset */ | 55 | /* I2S device reset */ |
56 | DEV_RS |= DEV_I2S; | 56 | DEV_RS |= DEV_I2S; |
57 | DEV_RS &=~DEV_I2S; | 57 | DEV_RS &=~DEV_I2S; |
58 | 58 | ||
59 | /* device enable */ | 59 | /* I2S device enable */ |
60 | DEV_EN |= (DEV_I2S | 0x7); | 60 | DEV_EN |= DEV_I2S; |
61 | 61 | ||
62 | /* enable external dev clock clocks */ | 62 | /* enable external dev clock clocks */ |
63 | DEV_EN |= 0x2; | 63 | DEV_EN |= DEV_EXTCLOCKS; |
64 | 64 | ||
65 | /* external dev clock to 24MHz */ | 65 | /* external dev clock to 24MHz */ |
66 | outl(inl(0x70000018) & ~0xc, 0x70000018); | 66 | outl(inl(0x70000018) & ~0xc, 0x70000018); |