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diff --git a/firmware/target/sh/archos/lcd-as-archos-bitmap.S b/firmware/target/sh/archos/lcd-as-archos-bitmap.S
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1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2004 by Jens Arnold
11 * Based on the work of Alan Korr and Jörg Hohensohn
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
17 *
18 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
19 * KIND, either express or implied.
20 *
21 ****************************************************************************/
22
23#include "config.h"
24#include "cpu.h"
25
26#define LCDR (PBDR_ADDR+1)
27
28#define LCD_SD 1 /* PB0 = 1 --- 0001 */
29#define LCD_SC 2 /* PB1 = 1 --- 0010 */
30#define LCD_DS 4 /* PB2 = 1 --- 0100 */
31#define LCD_CS 8 /* PB3 = 1 --- 1000 */
32
33/*
34 * About /CS,DS,SC,SD
35 * ------------------
36 *
37 * LCD on JBP and JBR uses a SPI protocol to receive orders (SDA and SCK lines)
38 *
39 * - /CS -> Chip Selection line :
40 * 0 : LCD chipset is activated.
41 * - DS -> Data Selection line, latched at the rising edge
42 * of the 8th serial clock (*) :
43 * 0 : instruction register,
44 * 1 : data register;
45 * - SC -> Serial Clock line (SDA).
46 * - SD -> Serial Data line (SCK), latched at the rising edge
47 * of each serial clock (*).
48 *
49 * _ _
50 * /CS \ /
51 * \______________________________________________________/
52 * _____ ____ ____ ____ ____ ____ ____ ____ ____ _____
53 * SD \/ D7 \/ D6 \/ D5 \/ D4 \/ D3 \/ D2 \/ D1 \/ D0 \/
54 * _____/\____/\____/\____/\____/\____/\____/\____/\____/\_____
55 *
56 * _____ _ _ _ _ _ _ _ ________
57 * SC \ * \ * \ * \ * \ * \ * \ * \ *
58 * \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
59 * _ _________________________________________________________
60 * DS \/
61 * _/\_________________________________________________________
62 *
63 */
64
65 .section .icode,"ax",@progbits
66
67 .align 2
68 .global _lcd_write_command
69 .type _lcd_write_command,@function
70
71/* Write a command byte to the lcd controller
72 *
73 * Arguments:
74 * r4 - data byte (int)
75 *
76 * Register usage:
77 * r0 - scratch
78 * r1 - data byte (copied)
79 * r2 - precalculated port value (CS, DS and SC low, SD high),
80 * negated (neg)!
81 * r3 - lcd port address
82 * r5 - 1 (byte count for reuse of the loop in _lcd_write_data)
83 */
84
85_lcd_write_command:
86 mov.l .lcdr, r3 /* put lcd data port address in r3 */
87 mov r4, r1 /* copy data byte to r1 */
88
89 /* This code will fail if an interrupt changes the contents of PBDRL.
90 * If so, we must disable the interrupt here. */
91
92 mov.b @r3, r0 /* r0 = PBDRL */
93 mov #0, r5 /* fake end address - stop after first iteration */
94 or #(LCD_SD), r0 /* r0 |= LCD_SD */
95 and #(~(LCD_CS|LCD_DS|LCD_SC)), r0 /* r0 &= ~(LCD_CS|LCD_DS|LCD_SC) */
96
97 bra .single_transfer /* jump into the transfer loop */
98 neg r0, r2 /* r2 = 0 - r0 */
99
100
101 .align 2
102 .global _lcd_write_data
103 .type _lcd_write_data,@function
104
105/* A high performance function to write data to the display,
106 * one or multiple bytes.
107 *
108 * Arguments:
109 * r4 - data address
110 * r5 - byte count
111 *
112 * Register usage:
113 * r0 - scratch
114 * r1 - current data byte
115 * r2 - precalculated port value (CS and SC low, DS and SD high),
116 * negated (neg)!
117 * r3 - lcd port address
118 */
119
120_lcd_write_data:
121 mov.l .lcdr, r3 /* put lcd data port address in r3 */
122 add r4, r5 /* end address */
123
124 /* This code will fail if an interrupt changes the contents of PBDRL.
125 * If so, we must disable the interrupt here. If disabling interrupts
126 * for a long time (~9200 clks = ~830 µs for transferring 112 bytes on
127 * recorders)is undesirable, the loop has to be rewritten to
128 * disable/precalculate/transfer/enable for each iteration. However,
129 * this would significantly decrease performance. */
130
131 mov.b @r3, r0 /* r0 = PBDRL */
132 or #(LCD_DS|LCD_SD), r0 /* r0 |= LCD_DS|LCD_SD */
133 and #(~(LCD_CS|LCD_SC)), r0 /* r0 &= ~(LCD_CS|LCD_SC) */
134 neg r0, r2 /* r2 = 0 - r0 */
135
136 /* loop exploits that SD is on bit 0 for recorders and Ondios */
137
138 .align 2
139.multi_transfer:
140 mov.b @r4+, r1 /* load data byte from memory */
141 nop
142
143.single_transfer:
144 shll16 r1 /* shift data to most significant byte */
145 shll8 r1
146 not r1, r1 /* and invert for use with negc */
147
148 shll r1 /* shift the MSB into carry */
149 negc r2, r0 /* carry to SD, SC low */
150 shll r1 /* next shift here for alignment */
151 mov.b r0, @r3 /* set data to port */
152 or #(LCD_SC), r0 /* rise SC (independent of SD level) */
153 mov.b r0, @r3 /* set to port */
154
155 negc r2, r0
156 mov.b r0, @r3
157 or #(LCD_SC), r0
158 mov.b r0, @r3
159
160 shll r1
161 negc r2, r0
162 shll r1
163 mov.b r0, @r3
164 or #(LCD_SC), r0
165 mov.b r0, @r3
166
167 negc r2, r0
168 mov.b r0, @r3
169 or #(LCD_SC), r0
170 mov.b r0, @r3
171
172 shll r1
173 negc r2, r0
174 shll r1
175 mov.b r0, @r3
176 or #(LCD_SC), r0
177 mov.b r0, @r3
178
179 negc r2, r0
180 mov.b r0, @r3
181 or #(LCD_SC), r0
182 mov.b r0, @r3
183
184 shll r1
185 negc r2, r0
186 shll r1
187 mov.b r0, @r3
188 or #(LCD_SC), r0
189 mov.b r0, @r3
190
191 negc r2, r0
192 mov.b r0, @r3
193 or #(LCD_SC), r0
194 mov.b r0, @r3
195
196 cmp/hi r4, r5 /* some blocks left? */
197 bt .multi_transfer
198
199 or #(LCD_CS|LCD_DS|LCD_SD|LCD_SC), r0 /* restore port */
200 rts
201 mov.b r0, @r3
202
203 /* This is the place to reenable the interrupts, if we have disabled
204 * them. See above. */
205
206#ifndef BOOTLOADER
207 .align 2
208 .global _lcd_grey_data
209 .type _lcd_grey_data,@function
210
211/* A high performance function to write grey phase data to the display,
212 * one or multiple pixels.
213 *
214 * Arguments:
215 * r4 - pixel value data address
216 * r5 - pixel phase data address
217 * r6 - pixel block count
218 *
219 * Register usage:
220 * r0 - scratch / phase signs mask
221 * r1 - scratch
222 * r2 - precalculated port value (CS and SC low, DS and SD high),
223 * negated (neg)!
224 * r3 - lcd port address
225 * r4 - current value address
226 * r5 - current phase address
227 * r6 - end address
228 * r7/r8 - current/next block of phases (alternating)
229 * r9/r10 - current blocks of values
230 * r11 - 0x00000080 \
231 * r12 - 0x00008000 > for phase sign check
232 * r13 - 0x00800000 /
233 */
234
235_lcd_grey_data:
236 mov.l r8, @-r15 /* save r8 */
237 mov.l r9, @-r15 /* save r9 */
238 mov.l r10, @-r15 /* save r10 */
239 shll2 r6 /* v */
240 mov.l r11, @-r15 /* save r11 */
241 shll r6 /* r6 *= 8; (8 pixels per block) */
242 mov.l .lcdr, r3 /* put lcd data port address in r3 */
243 add r4, r6 /* end address */
244
245 /* This code will fail if an interrupt changes the contents of PBDRL.
246 * If so, we must disable the interrupt here. If disabling interrupts
247 * for a long time is undesirable, the loop has to be rewritten to
248 * disable/precalculate/transfer/enable for each iteration. However,
249 * this would significantly decrease performance. */
250
251 mov.b @r3, r0 /* r0 = PBDRL */
252 or #(LCD_DS|LCD_SD), r0 /* r0 |= LCD_DS|LCD_SD */
253 mov.l r12, @-r15 /* save r12 */
254 and #(~(LCD_CS|LCD_SC)), r0 /* r0 &= ~(LCD_CS|LCD_SC) */
255 mov.l r13, @-r15 /* save r13 */
256 neg r0, r2 /* r2 = 0 - r0 */
257
258 /* loop exploits that SD is on bit 0 for recorders and Ondios */
259
260 mov.w .ptest, r11
261 swap.b r11, r12
262 mov.l @r5, r7
263 swap.w r11, r13
264 mov.l .pmask, r0
265
266.greyloop:
267 cmp/pz r7
268 mov.l @r4+, r9
269 negc r2, r1
270 mov.b r1, @r3
271 add #(LCD_SC), r1
272 mov.b r1, @r3
273
274 tst r13, r7
275 mov.l @r4+, r10
276 negc r2, r1
277 mov.b r1, @r3
278 add #(LCD_SC), r1
279 mov.b r1, @r3
280
281 tst r12, r7
282 mov.l @(4,r5), r8
283 negc r2, r1
284 mov.b r1, @r3
285 add #(LCD_SC), r1
286 mov.b r1, @r3
287
288 tst r11, r7
289 or r0, r7
290 negc r2, r1
291 mov.b r1, @r3
292 add #(LCD_SC), r1
293 mov.b r1, @r3
294
295 cmp/pz r8
296 sub r9, r7
297 negc r2, r1
298 mov.b r1, @r3
299 add #(LCD_SC), r1
300 mov.b r1, @r3
301
302 tst r13, r8
303 mov.l r7, @r5
304 negc r2, r1
305 mov.b r1, @r3
306 add #(LCD_SC), r1
307 mov.b r1, @r3
308
309 tst r12, r8
310 mov.l @(8,r5), r7
311 negc r2, r1
312 mov.b r1, @r3
313 add #(LCD_SC), r1
314 mov.b r1, @r3
315
316 tst r11, r8
317 or r0, r8
318 negc r2, r1
319 mov.b r1, @r3
320 add #(LCD_SC), r1
321 mov.b r1, @r3
322
323 sub r10, r8
324 mov.l r8, @(4,r5)
325
326 add #8, r5
327 cmp/hi r4, r6
328 bt .greyloop
329
330 mov.l @r15+, r13 /* restore r13 */
331 mov #(LCD_CS|LCD_DS|LCD_SD|LCD_SC), r0
332 mov.l @r15+, r12 /* restore r12 */
333 or r0, r1 /* restore port */
334 mov.l @r15+, r11 /* restore r11 */
335 mov.l @r15+, r10 /* restore r10 */
336 mov.l @r15+, r9 /* restore r9 */
337 mov.l @r15+, r8 /* restore r8 */
338 rts
339 mov.b r1, @r3
340
341 /* This is the place to reenable the interrupts, if we have disabled
342 * them. See above. */
343
344.ptest:
345 .short 0x0080
346
347 .align 2
348.pmask:
349 .long 0x80808080
350#endif
351
352 .align 2
353.lcdr:
354 .long LCDR
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