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-rw-r--r--firmware/target/mips/ingenic_jz47xx/codec-jz4740.c59
-rw-r--r--firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c25
-rw-r--r--firmware/target/mips/ingenic_jz47xx/usb-jz4740.c11
3 files changed, 49 insertions, 46 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/codec-jz4740.c b/firmware/target/mips/ingenic_jz47xx/codec-jz4740.c
index dec343a0da..d144a03553 100644
--- a/firmware/target/mips/ingenic_jz47xx/codec-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/codec-jz4740.c
@@ -32,50 +32,52 @@ static int IS_WRITE_PCM;
32 32
33static void i2s_codec_set_samplerate(unsigned short rate); 33static void i2s_codec_set_samplerate(unsigned short rate);
34 34
35static void i2s_codec_clear(void) 35static void i2s_codec_reset(void)
36{ 36{
37 REG_ICDC_CDCCR1 = (ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_PDVR | ICDC_CDCCR1_PDVRA | ICDC_CDCCR1_VRCGL | 37 REG_ICDC_CDCCR1 = (ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_PDVR | ICDC_CDCCR1_PDVRA | ICDC_CDCCR1_VRCGL |
38 ICDC_CDCCR1_VRCGH | ICDC_CDCCR1_HPOV0 | ICDC_CDCCR1_PDHPM | ICDC_CDCCR1_PDHP | 38 ICDC_CDCCR1_VRCGH | ICDC_CDCCR1_HPOV0 | ICDC_CDCCR1_PDHPM | ICDC_CDCCR1_PDHP |
39 ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST); 39 ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST);
40 udelay(10);
41 REG_ICDC_CDCCR1 = (ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_PDVR | ICDC_CDCCR1_PDVRA | ICDC_CDCCR1_VRCGL |
42 ICDC_CDCCR1_VRCGH | ICDC_CDCCR1_HPOV0 | ICDC_CDCCR1_PDHPM | ICDC_CDCCR1_PDHP );
40} 43}
41 44
42static void i2s_codec_init(void) 45static void i2s_codec_init(void)
43{ 46{
44 __aic_enable(); 47 __aic_enable();
45 48
46 __aic_select_i2s();
47 __i2s_internal_codec(); 49 __i2s_internal_codec();
50 __i2s_as_slave();
51 __i2s_select_i2s();
52 __aic_select_i2s();
48 53
49 __i2s_set_oss_sample_size(16); 54 __aic_disable_byteswap();
55 __aic_disable_unsignadj();
56 __aic_disable_mono2stereo();
50 57
51 REG_ICDC_CDCCR1 = (ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_PDVR | ICDC_CDCCR1_PDVRA | ICDC_CDCCR1_VRCGL | 58 i2s_codec_reset();
52 ICDC_CDCCR1_VRCGH | ICDC_CDCCR1_HPOV0 | ICDC_CDCCR1_PDHPM | ICDC_CDCCR1_PDHP |
53 ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST); /* reset */
54 udelay(10);
55 REG_ICDC_CDCCR1 = (ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_PDVR | ICDC_CDCCR1_PDVRA | ICDC_CDCCR1_VRCGL |
56 ICDC_CDCCR1_VRCGH | ICDC_CDCCR1_HPOV0 | ICDC_CDCCR1_PDHPM | ICDC_CDCCR1_PDHP |
57 ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST);
58 //REG_ICDC_CDCCR2 = (ICDC_CDCCR2_AINVOL(ICDC_CDCCR2_AINVOL_DB(0)) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_48) |
59 REG_ICDC_CDCCR2 = (ICDC_CDCCR2_AINVOL(23) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_48) |
60 ICDC_CDCCR2_HPVOL(ICDC_CDCCR2_HPVOL_6));
61 59
62 REG_ICDC_CDCCR1 &= 0xfffffffc; 60 //REG_ICDC_CDCCR2 = (ICDC_CDCCR2_AINVOL(ICDC_CDCCR2_AINVOL_DB(0)) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_48)
63 61 REG_ICDC_CDCCR2 = ( ICDC_CDCCR2_AINVOL(23) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_48)
64 mdelay(15); 62 | ICDC_CDCCR2_HPVOL(ICDC_CDCCR2_HPVOL_6));
65 REG_ICDC_CDCCR1 &= 0xffecffff;
66 REG_ICDC_CDCCR1 |= (ICDC_CDCCR1_EDAC | ICDC_CDCCR1_HPCG);
67
68 mdelay(600);
69 REG_ICDC_CDCCR1 &= 0xfff7ecff;
70
71 mdelay(2);
72 63
73 /* CDCCR1.ELININ=0, CDCCR1.EMIC=0, CDCCR1.EADC=0, CDCCR1.SW1ON=0, CDCCR1.EDAC=1, CDCCR1.SW2ON=1, CDCCR1.HPMUTE=0 */ 64 REG_ICDC_CDCCR1 &= ~(ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST);
74 REG_ICDC_CDCCR1 = (REG_ICDC_CDCCR1 & ~((1 << 29) | (1 << 28) | (1 << 26) | (1 << 27) | (1 << 14))) | ((1 << 24) | (1 << 25)); 65
66 mdelay(15);
67 REG_ICDC_CDCCR1 &= ~(ICDC_CDCCR1_PDVR | ICDC_CDCCR1_VRCGL | ICDC_CDCCR1_VRCGH);
68 REG_ICDC_CDCCR1 |= (ICDC_CDCCR1_EDAC | ICDC_CDCCR1_HPCG);
75 69
76 REG_ICDC_CDCCR2 = ((REG_ICDC_CDCCR2 & ~(0x3)) | 3); 70 mdelay(600);
71 REG_ICDC_CDCCR1 &= ~(ICDC_CDCCR1_PDVRA | ICDC_CDCCR1_HPCG | ICDC_CDCCR1_PDHPM | ICDC_CDCCR1_PDHP);
77 72
78 i2s_codec_set_samplerate(44100); 73 mdelay(2);
74
75 /* CDCCR1.ELININ=0, CDCCR1.EMIC=0, CDCCR1.EADC=0, CDCCR1.SW1ON=0, CDCCR1.EDAC=1, CDCCR1.SW2ON=1, CDCCR1.HPMUTE=0 */
76 REG_ICDC_CDCCR1 = (REG_ICDC_CDCCR1 & ~(ICDC_CDCCR1_ELININ | ICDC_CDCCR1_EMIC | ICDC_CDCCR1_EADC |
77 ICDC_CDCCR1_SW1ON | ICDC_CDCCR1_HPMUTE)) | (ICDC_CDCCR1_EDAC
78 | ICDC_CDCCR1_SW2ON);
79
80 REG_ICDC_CDCCR2 |= 3;
79 81
80 HP_on_off_flag = 0; /* HP is off */ 82 HP_on_off_flag = 0; /* HP is off */
81} 83}
@@ -296,7 +298,6 @@ void audiohw_mute(bool mute)
296 298
297void audiohw_preinit(void) 299void audiohw_preinit(void)
298{ 300{
299 i2s_codec_init();
300} 301}
301 302
302void audiohw_postinit(void) 303void audiohw_postinit(void)
@@ -306,5 +307,5 @@ void audiohw_postinit(void)
306 307
307void audiohw_init(void) 308void audiohw_init(void)
308{ 309{
309 310 i2s_codec_init();
310} 311}
diff --git a/firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c b/firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c
index 5549ce4dbf..e4d9127c21 100644
--- a/firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c
@@ -35,6 +35,11 @@
35void pcm_postinit(void) 35void pcm_postinit(void)
36{ 36{
37 audiohw_postinit(); 37 audiohw_postinit();
38
39 /* playback sample:16 bits, burst:16 bytes */
40 __i2s_set_transmit_trigger(4);
41 __i2s_set_oss_sample_size(16);
42
38 pcm_apply_settings(); 43 pcm_apply_settings();
39} 44}
40 45
@@ -53,11 +58,6 @@ void pcm_play_dma_init(void)
53 audiohw_init(); 58 audiohw_init();
54} 59}
55 60
56void pcm_apply_settings(void)
57{
58 /* TODO */
59}
60
61void pcm_set_frequency(unsigned int frequency) 61void pcm_set_frequency(unsigned int frequency)
62{ 62{
63 (void) frequency; 63 (void) frequency;
@@ -71,10 +71,8 @@ void pcm_set_frequency(unsigned int frequency)
71 71
72static void play_start_pcm(void) 72static void play_start_pcm(void)
73{ 73{
74 pcm_apply_settings(); 74 __i2s_enable_transmit_dma();
75 75 __i2s_enable_replay();
76 __aic_enable_transmit_dma();
77 __aic_enable_replay();
78 76
79 REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) |= DMAC_DCCSR_EN; 77 REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) |= DMAC_DCCSR_EN;
80} 78}
@@ -83,18 +81,18 @@ static void play_stop_pcm(void)
83{ 81{
84 REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) = (REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) | DMAC_DCCSR_HLT) & ~DMAC_DCCSR_EN; 82 REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) = (REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) | DMAC_DCCSR_HLT) & ~DMAC_DCCSR_EN;
85 83
86 __aic_disable_transmit_dma(); 84 __i2s_disable_transmit_dma();
87 __aic_disable_replay(); 85 __i2s_disable_replay();
88} 86}
89 87
90void pcm_play_dma_start(const void *addr, size_t size) 88void pcm_play_dma_start(const void *addr, size_t size)
91{ 89{
92 REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) = 0; 90 REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) = DMAC_DCCSR_NDES;
93 REG_DMAC_DSAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)addr); 91 REG_DMAC_DSAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)addr);
94 REG_DMAC_DTAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)AIC_DR); 92 REG_DMAC_DTAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)AIC_DR);
95 REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL) = size; 93 REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL) = size;
96 REG_DMAC_DRSR(DMA_AIC_TX_CHANNEL) = DMAC_DRSR_RS_AICOUT; 94 REG_DMAC_DRSR(DMA_AIC_TX_CHANNEL) = DMAC_DRSR_RS_AICOUT;
97 REG_DMAC_DCMD(DMA_AIC_TX_CHANNEL) = ( DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_32BIT | DMAC_DCMD_DWDH_32 95 REG_DMAC_DCMD(DMA_AIC_TX_CHANNEL) = ( DMAC_DCMD_SAI| DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_32BIT | DMAC_DCMD_DWDH_32
98 | DMAC_DCMD_TIE); 96 | DMAC_DCMD_TIE);
99 97
100 play_start_pcm(); 98 play_start_pcm();
@@ -134,7 +132,6 @@ void pcm_play_dma_pause(bool pause)
134 play_stop_pcm(); 132 play_stop_pcm();
135 else 133 else
136 play_start_pcm(); 134 play_start_pcm();
137
138} 135}
139 136
140#ifdef HAVE_RECORDING 137#ifdef HAVE_RECORDING
diff --git a/firmware/target/mips/ingenic_jz47xx/usb-jz4740.c b/firmware/target/mips/ingenic_jz47xx/usb-jz4740.c
index 1d58cbc14d..16965159f6 100644
--- a/firmware/target/mips/ingenic_jz47xx/usb-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/usb-jz4740.c
@@ -28,8 +28,11 @@
28#include "jz4740.h" 28#include "jz4740.h"
29#include "thread.h" 29#include "thread.h"
30 30
31//#define DEBUGF printf 31#if 1
32#define DEBUGF printf
33#else
32#define DEBUGF(...) 34#define DEBUGF(...)
35#endif
33 36
34#define USB_EP0_IDLE 0 37#define USB_EP0_IDLE 0
35#define USB_EP0_RX 1 38#define USB_EP0_RX 1
@@ -86,7 +89,7 @@ static void readFIFO(struct usb_endpoint *ep, unsigned int size)
86 89
87 register unsigned char *ptr = (unsigned char*)EP_PTR(ep); 90 register unsigned char *ptr = (unsigned char*)EP_PTR(ep);
88 register unsigned int *ptr32 = (unsigned int*)ptr; 91 register unsigned int *ptr32 = (unsigned int*)ptr;
89 register unsigned int s = size / 4; 92 register unsigned int s = size >> 2;
90 register unsigned int x; 93 register unsigned int x;
91 94
92 if(size > 0) 95 if(size > 0)
@@ -333,7 +336,7 @@ void usb_drv_stall(int endpoint, bool stall, bool in)
333 336
334 select_endpoint(endpoint); 337 select_endpoint(endpoint);
335 338
336 if(endpoint == 0) 339 if(endpoint == EP_CONTROL)
337 { 340 {
338 if(stall) 341 if(stall)
339 REG_USB_REG_CSR0 |= USB_CSR0_SENDSTALL; 342 REG_USB_REG_CSR0 |= USB_CSR0_SENDSTALL;
@@ -458,6 +461,8 @@ int usb_drv_recv(int endpoint, void* ptr, int length)
458 461
459void usb_drv_set_test_mode(int mode) 462void usb_drv_set_test_mode(int mode)
460{ 463{
464 DEBUGF("usb_drv_set_test_mode(%d)", mode);
465
461 switch(mode) 466 switch(mode)
462 { 467 {
463 case 0: 468 case 0: