diff options
Diffstat (limited to 'firmware/target/mips')
65 files changed, 13286 insertions, 2 deletions
diff --git a/firmware/target/mips/ingenic_x1000/aic-x1000.c b/firmware/target/mips/ingenic_x1000/aic-x1000.c new file mode 100644 index 0000000000..a0e509d3b6 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/aic-x1000.c | |||
@@ -0,0 +1,119 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "system.h" | ||
23 | #include "aic-x1000.h" | ||
24 | #include "gpio-x1000.h" | ||
25 | #include "x1000/aic.h" | ||
26 | #include "x1000/cpm.h" | ||
27 | |||
28 | /* Given a rational number m/n < 1, find its representation as a continued | ||
29 | * fraction [0; a1, a2, a3, ..., a_k]. At most "cnt" terms are calculated | ||
30 | * and written out to "buf". Returns the number of terms written; the result | ||
31 | * is complete if this value is less than "cnt", and may be incomplete if it | ||
32 | * is equal to "cnt". (Note the leading zero term is not written to "buf".) | ||
33 | */ | ||
34 | static unsigned cf_derive(unsigned m, unsigned n, unsigned* buf, unsigned cnt) | ||
35 | { | ||
36 | unsigned wrote = 0; | ||
37 | unsigned a = m / n; | ||
38 | while(cnt--) { | ||
39 | unsigned tmp = n; | ||
40 | n = m - n * a; | ||
41 | if(n == 0) | ||
42 | break; | ||
43 | |||
44 | m = tmp; | ||
45 | a = m / n; | ||
46 | *buf++ = a; | ||
47 | wrote++; | ||
48 | } | ||
49 | |||
50 | return wrote; | ||
51 | } | ||
52 | |||
53 | /* Given a finite continued fraction [0; buf[0], buf[1], ..., buf[count-1]], | ||
54 | * calculate the rational number m/n which it represents. Returns m and n. | ||
55 | * If count is zero, then m and n are undefined. | ||
56 | */ | ||
57 | static void cf_expand(const unsigned* buf, unsigned count, | ||
58 | unsigned* m, unsigned* n) | ||
59 | { | ||
60 | if(count == 0) | ||
61 | return; | ||
62 | |||
63 | unsigned i = count - 1; | ||
64 | unsigned mx = 1, nx = buf[i]; | ||
65 | while(i--) { | ||
66 | unsigned tmp = nx; | ||
67 | nx = mx + buf[i] * nx; | ||
68 | mx = tmp; | ||
69 | } | ||
70 | |||
71 | *m = mx; | ||
72 | *n = nx; | ||
73 | } | ||
74 | |||
75 | int aic_i2s_set_mclk(x1000_clk_t clksrc, unsigned fs, unsigned mult) | ||
76 | { | ||
77 | /* get the input clock rate */ | ||
78 | uint32_t src_freq = clk_get(clksrc); | ||
79 | |||
80 | /* reject invalid parameters */ | ||
81 | if(mult % 64 != 0) | ||
82 | return -1; | ||
83 | |||
84 | if(clksrc == X1000_EXCLK_FREQ) { | ||
85 | if(mult != 0) | ||
86 | return -1; | ||
87 | |||
88 | jz_writef(AIC_I2SCR, STPBK(1)); | ||
89 | jz_writef(CPM_I2SCDR, CS(0), CE(0)); | ||
90 | REG_AIC_I2SDIV = X1000_EXCLK_FREQ / 64 / fs; | ||
91 | } else { | ||
92 | if(mult == 0) | ||
93 | return -1; | ||
94 | if(fs*mult > src_freq) | ||
95 | return -1; | ||
96 | |||
97 | /* calculate best rational approximation that fits our constraints */ | ||
98 | unsigned m = 0, n = 0; | ||
99 | unsigned buf[16]; | ||
100 | unsigned cnt = cf_derive(fs*mult, src_freq, &buf[0], 16); | ||
101 | do { | ||
102 | cf_expand(&buf[0], cnt, &m, &n); | ||
103 | cnt -= 1; | ||
104 | } while(cnt > 0 && (m > 512 || n > 8192) && (n >= 2*m)); | ||
105 | |||
106 | /* wrong values */ | ||
107 | if(cnt == 0 || n == 0 || m == 0) | ||
108 | return -1; | ||
109 | |||
110 | jz_writef(AIC_I2SCR, STPBK(1)); | ||
111 | jz_writef(CPM_I2SCDR, PCS(clksrc == X1000_CLK_MPLL ? 1 : 0), | ||
112 | CS(1), CE(1), DIV_M(m), DIV_N(n)); | ||
113 | jz_write(CPM_I2SCDR1, REG_CPM_I2SCDR1); | ||
114 | REG_AIC_I2SDIV = (mult / 64) - 1; | ||
115 | } | ||
116 | |||
117 | jz_writef(AIC_I2SCR, STPBK(0)); | ||
118 | return 0; | ||
119 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/aic-x1000.h b/firmware/target/mips/ingenic_x1000/aic-x1000.h new file mode 100644 index 0000000000..eda0f80f04 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/aic-x1000.h | |||
@@ -0,0 +1,46 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef __AIC_X1000_H__ | ||
23 | #define __AIC_X1000_H__ | ||
24 | |||
25 | #include "clk-x1000.h" | ||
26 | #include <stdbool.h> | ||
27 | |||
28 | /* Set frequency of I2S master clock supplied by AIC. Has no use if an | ||
29 | * external DAC is supplying the master clock. Must be called with the | ||
30 | * bit clock disabled. | ||
31 | * | ||
32 | * - clksrc can be one of EXCLK, SCLK_A, MPLL. | ||
33 | * - This function does not modify PLL settings. It's the caller's job | ||
34 | * to ensure the PLL is configured and runing. | ||
35 | * - fs is the audio sampling frequency (8 KHz - 192 KHz) | ||
36 | * - mult is multiplied by fs to get the master clock rate. | ||
37 | * - mult must be a multiple of 64 due to AIC bit clock requirements. | ||
38 | * - Note: EXCLK bypasses the decimal divider so it is not very flexible. | ||
39 | * If using EXCLK you must set mult=0. If EXCLK is not a multiple of | ||
40 | * the bit clock (= 64*fs), then the clock rate will be inaccurate. | ||
41 | * | ||
42 | * Returns zero on success and nonzero if the frequency is not achievable. | ||
43 | */ | ||
44 | extern int aic_i2s_set_mclk(x1000_clk_t clksrc, unsigned fs, unsigned mult); | ||
45 | |||
46 | #endif /* __AIC_X1000_H__ */ | ||
diff --git a/firmware/target/mips/ingenic_x1000/app.lds b/firmware/target/mips/ingenic_x1000/app.lds new file mode 100644 index 0000000000..0f6352b8ee --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/app.lds | |||
@@ -0,0 +1,119 @@ | |||
1 | #include "config.h" | ||
2 | |||
3 | OUTPUT_FORMAT("elf32-littlemips") | ||
4 | OUTPUT_ARCH(MIPS) | ||
5 | ENTRY(_start) | ||
6 | STARTUP(target/mips/ingenic_x1000/crt0.o) | ||
7 | |||
8 | /* Stub area is used for loading new firmware via RoLo */ | ||
9 | #define STUBSIZE 0x4000 | ||
10 | #define SDRAM_ORIG 0x80000000 | ||
11 | |||
12 | /* IRAM contains stub, DRAM contains main app */ | ||
13 | #define IRAMORIG SDRAM_ORIG | ||
14 | #define IRAMSIZE STUBSIZE | ||
15 | #define DRAMORIG (SDRAM_ORIG + STUBSIZE) | ||
16 | #define DRAMSIZE (MEMORYSIZE * 0x100000 - STUBSIZE) | ||
17 | |||
18 | /* End of the audio buffer, where the codec buffer starts */ | ||
19 | #define ENDAUDIOADDR (DRAMORIG + DRAMSIZE - PLUGIN_BUFFER_SIZE - CODEC_SIZE) | ||
20 | |||
21 | /* Where the codec buffer ends, and the plugin buffer starts */ | ||
22 | #define ENDCODECADDR (ENDAUDIOADDR + CODEC_SIZE) | ||
23 | |||
24 | MEMORY | ||
25 | { | ||
26 | IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE | ||
27 | DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE | ||
28 | } | ||
29 | |||
30 | SECTIONS | ||
31 | { | ||
32 | .text : | ||
33 | { | ||
34 | loadaddress = .; | ||
35 | _loadaddress = .; | ||
36 | *(.init.text); | ||
37 | *(.text*); | ||
38 | } > DRAM | ||
39 | |||
40 | . = ALIGN(4); | ||
41 | .rodata : | ||
42 | { | ||
43 | *(.rodata*); | ||
44 | } > DRAM | ||
45 | |||
46 | . = ALIGN(4); | ||
47 | .data : | ||
48 | { | ||
49 | *(.data*); | ||
50 | *(.sdata*); | ||
51 | } > DRAM | ||
52 | |||
53 | .iram IRAMORIG: AT (_bssbegin) | ||
54 | { | ||
55 | _iramstart = .; | ||
56 | . = 0x000; /* TLB refill */ | ||
57 | KEEP(*(.vectors.1)); | ||
58 | . = 0x100; /* Cache error */ | ||
59 | KEEP(*(.vectors.2)); | ||
60 | . = 0x180; /* General exception */ | ||
61 | KEEP(*(.vectors.3)); | ||
62 | . = 0x200; /* Interrupt */ | ||
63 | KEEP(*(.vectors.4)); | ||
64 | KEEP(*(.vectors)); | ||
65 | |||
66 | *(.icode); | ||
67 | *(.irodata); | ||
68 | *(.idata); | ||
69 | _iramend = .; | ||
70 | } > IRAM | ||
71 | _iramcopy = LOADADDR(.iram); | ||
72 | |||
73 | . = ALIGN(4); | ||
74 | .stack (NOLOAD) : | ||
75 | { | ||
76 | *(.stack); | ||
77 | stackbegin = .; | ||
78 | . += 0x1E00; | ||
79 | stackend = .; | ||
80 | _irqstackbegin = .; | ||
81 | . += 0x300; | ||
82 | _irqstackend = .; | ||
83 | } > IRAM | ||
84 | |||
85 | .bss (NOLOAD) : | ||
86 | { | ||
87 | _bssbegin = .; | ||
88 | *(.sbss*); | ||
89 | *(.bss*); | ||
90 | *(COMMON); | ||
91 | *(.scommon*); | ||
92 | _bssend = .; | ||
93 | _end = .; | ||
94 | } > DRAM | ||
95 | |||
96 | #ifdef BOOTLOADER | ||
97 | . = ALIGN(4); | ||
98 | loadbuffer = .; | ||
99 | . += 0x100000 * 4; /* Allow 4 MiB for the rockbox binary */ | ||
100 | loadbufferend = .; | ||
101 | #else | ||
102 | |||
103 | .audiobuf : | ||
104 | { | ||
105 | . = ALIGN(4); /* XXX might need more alignment here */ | ||
106 | audiobuffer = .; | ||
107 | } > DRAM | ||
108 | |||
109 | audiobufend = ENDAUDIOADDR; | ||
110 | codecbuf = ENDAUDIOADDR; | ||
111 | pluginbuf = ENDCODECADDR; | ||
112 | #endif | ||
113 | |||
114 | /DISCARD/ : | ||
115 | { | ||
116 | *(.eh_frame); | ||
117 | *(.rel.dyn); | ||
118 | } | ||
119 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/boot.lds b/firmware/target/mips/ingenic_x1000/boot.lds new file mode 100644 index 0000000000..81468a95fc --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/boot.lds | |||
@@ -0,0 +1,5 @@ | |||
1 | #ifdef BOOTLOADER_SPL | ||
2 | # include "spl.lds" | ||
3 | #else | ||
4 | # include "app.lds" | ||
5 | #endif | ||
diff --git a/firmware/target/mips/ingenic_x1000/clk-x1000.c b/firmware/target/mips/ingenic_x1000/clk-x1000.c new file mode 100644 index 0000000000..390d9722ac --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/clk-x1000.c | |||
@@ -0,0 +1,258 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "system.h" | ||
23 | #include "clk-x1000.h" | ||
24 | #include "x1000/cpm.h" | ||
25 | #include "x1000/msc.h" | ||
26 | #include "x1000/aic.h" | ||
27 | |||
28 | static uint32_t pll_get(uint32_t pllreg, uint32_t onbit) | ||
29 | { | ||
30 | if((pllreg & (1 << onbit)) == 0) | ||
31 | return 0; | ||
32 | |||
33 | /* Both PLL registers share the same layout of N/M/OD bits. | ||
34 | * The max multiplier is 128 and max EXCLK is 26 MHz, so the | ||
35 | * multiplication should fit within 32 bits without overflow. | ||
36 | */ | ||
37 | uint32_t rate = X1000_EXCLK_FREQ; | ||
38 | rate *= jz_vreadf(pllreg, CPM_APCR, PLLM) + 1; | ||
39 | rate /= jz_vreadf(pllreg, CPM_APCR, PLLN) + 1; | ||
40 | rate >>= jz_vreadf(pllreg, CPM_APCR, PLLOD); | ||
41 | return rate; | ||
42 | } | ||
43 | |||
44 | static uint32_t sclk_a_get(void) | ||
45 | { | ||
46 | switch(jz_readf(CPM_CCR, SEL_SRC)) { | ||
47 | case 1: return X1000_EXCLK_FREQ; | ||
48 | case 2: return clk_get(X1000_CLK_APLL); | ||
49 | default: return 0; | ||
50 | } | ||
51 | } | ||
52 | |||
53 | static uint32_t ccr_get(uint32_t selbit, uint32_t divbit) | ||
54 | { | ||
55 | uint32_t reg = REG_CPM_CCR; | ||
56 | uint32_t sel = (reg >> selbit) & 0x3; | ||
57 | uint32_t div = (reg >> divbit) & 0xf; | ||
58 | |||
59 | switch(sel) { | ||
60 | case 1: return clk_get(X1000_CLK_SCLK_A) / (div + 1); | ||
61 | case 2: return clk_get(X1000_CLK_MPLL) / (div + 1); | ||
62 | default: return 0; | ||
63 | } | ||
64 | } | ||
65 | |||
66 | static uint32_t ddr_get(void) | ||
67 | { | ||
68 | uint32_t reg = REG_CPM_DDRCDR; | ||
69 | uint32_t div = jz_vreadf(reg, CPM_DDRCDR, CLKDIV); | ||
70 | |||
71 | switch(jz_vreadf(reg, CPM_DDRCDR, CLKSRC)) { | ||
72 | case 1: return clk_get(X1000_CLK_SCLK_A) / (div + 1); | ||
73 | case 2: return clk_get(X1000_CLK_MPLL) / (div + 1); | ||
74 | default: return 0; | ||
75 | } | ||
76 | } | ||
77 | |||
78 | static uint32_t lcd_get(void) | ||
79 | { | ||
80 | if(jz_readf(CPM_CLKGR, LCD)) | ||
81 | return 0; | ||
82 | |||
83 | uint32_t reg = REG_CPM_LPCDR; | ||
84 | uint32_t rate; | ||
85 | switch(jz_vreadf(reg, CPM_LPCDR, CLKSRC)) { | ||
86 | case 0: rate = clk_get(X1000_CLK_SCLK_A); break; | ||
87 | case 1: rate = clk_get(X1000_CLK_MPLL); break; | ||
88 | default: return 0; | ||
89 | } | ||
90 | |||
91 | rate /= jz_vreadf(reg, CPM_LPCDR, CLKDIV) + 1; | ||
92 | return rate; | ||
93 | } | ||
94 | |||
95 | static uint32_t msc_get(int msc) | ||
96 | { | ||
97 | if((msc == 0 && jz_readf(CPM_CLKGR, MSC0)) || | ||
98 | (msc == 1 && jz_readf(CPM_CLKGR, MSC1))) | ||
99 | return 0; | ||
100 | |||
101 | uint32_t reg = REG_CPM_MSC0CDR; | ||
102 | uint32_t rate; | ||
103 | switch(jz_vreadf(reg, CPM_MSC0CDR, CLKSRC)) { | ||
104 | case 0: rate = clk_get(X1000_CLK_SCLK_A); break; | ||
105 | case 1: rate = clk_get(X1000_CLK_MPLL); break; | ||
106 | default: return 0; | ||
107 | } | ||
108 | |||
109 | uint32_t div; | ||
110 | if(msc == 0) | ||
111 | div = jz_readf(CPM_MSC0CDR, CLKDIV); | ||
112 | else | ||
113 | div = jz_readf(CPM_MSC1CDR, CLKDIV); | ||
114 | |||
115 | rate /= 2 * (div + 1); | ||
116 | rate >>= REG_MSC_CLKRT(msc); | ||
117 | return rate; | ||
118 | } | ||
119 | |||
120 | static uint32_t i2s_mclk_get(void) | ||
121 | { | ||
122 | if(jz_readf(CPM_CLKGR, AIC)) | ||
123 | return 0; | ||
124 | |||
125 | uint32_t reg = REG_CPM_I2SCDR; | ||
126 | unsigned long long rate; | ||
127 | if(jz_vreadf(reg, CPM_I2SCDR, CS) == 0) | ||
128 | rate = X1000_EXCLK_FREQ; | ||
129 | else { | ||
130 | if(jz_vreadf(reg, CPM_I2SCDR, PCS) == 0) | ||
131 | rate = clk_get(X1000_CLK_SCLK_A); | ||
132 | else | ||
133 | rate = clk_get(X1000_CLK_MPLL); | ||
134 | |||
135 | rate *= jz_vreadf(reg, CPM_I2SCDR, DIV_M); | ||
136 | rate /= jz_vreadf(reg, CPM_I2SCDR, DIV_N); | ||
137 | } | ||
138 | |||
139 | /* Clamp invalid setting to 32 bits */ | ||
140 | if(rate > 0xffffffffull) | ||
141 | rate = 0xffffffff; | ||
142 | |||
143 | return rate; | ||
144 | } | ||
145 | |||
146 | static uint32_t i2s_bclk_get(void) | ||
147 | { | ||
148 | return i2s_mclk_get() / (REG_AIC_I2SDIV + 1); | ||
149 | } | ||
150 | |||
151 | static uint32_t sfc_get(void) | ||
152 | { | ||
153 | if(jz_readf(CPM_CLKGR, SFC)) | ||
154 | return 0; | ||
155 | |||
156 | uint32_t reg = REG_CPM_SSICDR; | ||
157 | uint32_t rate; | ||
158 | if(jz_vreadf(reg, CPM_SSICDR, SFC_CS) == 0) | ||
159 | rate = clk_get(X1000_CLK_SCLK_A); | ||
160 | else | ||
161 | rate = clk_get(X1000_CLK_MPLL); | ||
162 | |||
163 | rate /= jz_vreadf(reg, CPM_SSICDR, CLKDIV) + 1; | ||
164 | return rate; | ||
165 | } | ||
166 | |||
167 | uint32_t clk_get(x1000_clk_t clk) | ||
168 | { | ||
169 | switch(clk) { | ||
170 | case X1000_CLK_EXCLK: return X1000_EXCLK_FREQ; | ||
171 | case X1000_CLK_APLL: return pll_get(REG_CPM_APCR, BP_CPM_APCR_ON); | ||
172 | case X1000_CLK_MPLL: return pll_get(REG_CPM_MPCR, BP_CPM_MPCR_ON); | ||
173 | case X1000_CLK_SCLK_A: return sclk_a_get(); | ||
174 | case X1000_CLK_CPU: return ccr_get(BP_CPM_CCR_SEL_CPLL, BP_CPM_CCR_CDIV); | ||
175 | case X1000_CLK_L2CACHE: return ccr_get(BP_CPM_CCR_SEL_CPLL, BP_CPM_CCR_L2DIV); | ||
176 | case X1000_CLK_AHB0: return ccr_get(BP_CPM_CCR_SEL_H0PLL, BP_CPM_CCR_H0DIV); | ||
177 | case X1000_CLK_AHB2: return ccr_get(BP_CPM_CCR_SEL_H2PLL, BP_CPM_CCR_H2DIV); | ||
178 | case X1000_CLK_PCLK: return ccr_get(BP_CPM_CCR_SEL_H2PLL, BP_CPM_CCR_PDIV); | ||
179 | case X1000_CLK_DDR: return ddr_get(); | ||
180 | case X1000_CLK_LCD: return lcd_get(); | ||
181 | case X1000_CLK_MSC0: return msc_get(0); | ||
182 | case X1000_CLK_MSC1: return msc_get(1); | ||
183 | case X1000_CLK_I2S_MCLK: return i2s_mclk_get(); | ||
184 | case X1000_CLK_I2S_BCLK: return i2s_bclk_get(); | ||
185 | case X1000_CLK_SFC: return sfc_get(); | ||
186 | default: return 0; | ||
187 | } | ||
188 | } | ||
189 | |||
190 | const char* clk_get_name(x1000_clk_t clk) | ||
191 | { | ||
192 | switch(clk) { | ||
193 | #define CASE(x) case X1000_CLK_##x: return #x | ||
194 | CASE(EXCLK); | ||
195 | CASE(APLL); | ||
196 | CASE(MPLL); | ||
197 | CASE(SCLK_A); | ||
198 | CASE(CPU); | ||
199 | CASE(L2CACHE); | ||
200 | CASE(AHB0); | ||
201 | CASE(AHB2); | ||
202 | CASE(PCLK); | ||
203 | CASE(DDR); | ||
204 | CASE(LCD); | ||
205 | CASE(MSC0); | ||
206 | CASE(MSC1); | ||
207 | CASE(I2S_MCLK); | ||
208 | CASE(I2S_BCLK); | ||
209 | CASE(SFC); | ||
210 | #undef CASE | ||
211 | default: | ||
212 | return "NONE"; | ||
213 | } | ||
214 | } | ||
215 | |||
216 | #define CCR_MUX_BITS jz_orm(CPM_CCR, SEL_SRC, SEL_CPLL, SEL_H0PLL, SEL_H2PLL) | ||
217 | #define CSR_MUX_BITS jz_orm(CPM_CSR, SRC_MUX, CPU_MUX, AHB0_MUX, AHB2_MUX) | ||
218 | #define CSR_DIV_BITS jz_orm(CPM_CSR, H2DIV_BUSY, H0DIV_BUSY, CDIV_BUSY) | ||
219 | |||
220 | void clk_set_ccr_mux(uint32_t muxbits) | ||
221 | { | ||
222 | /* Set new mux configuration */ | ||
223 | uint32_t reg = REG_CPM_CCR; | ||
224 | reg &= ~CCR_MUX_BITS; | ||
225 | reg |= muxbits & CCR_MUX_BITS; | ||
226 | REG_CPM_CCR = reg; | ||
227 | |||
228 | /* Wait for mux change to complete */ | ||
229 | while((REG_CPM_CSR & CSR_MUX_BITS) != CSR_MUX_BITS); | ||
230 | } | ||
231 | |||
232 | void clk_set_ccr_div(int cpu, int l2, int ahb0, int ahb2, int pclk) | ||
233 | { | ||
234 | /* Set new divider configuration */ | ||
235 | jz_writef(CPM_CCR, CDIV(cpu - 1), L2DIV(l2 - 1), | ||
236 | H0DIV(ahb0 - 1), H2DIV(ahb2 - 1), PDIV(pclk - 1), | ||
237 | CE_CPU(1), CE_AHB0(1), CE_AHB2(1)); | ||
238 | |||
239 | /* Wait until divider change completes */ | ||
240 | while(REG_CPM_CSR & CSR_DIV_BITS); | ||
241 | |||
242 | /* Disable CE bits after change */ | ||
243 | jz_writef(CPM_CCR, CE_CPU(0), CE_AHB0(0), CE_AHB2(0)); | ||
244 | } | ||
245 | |||
246 | void clk_set_ddr(x1000_clk_t src, uint32_t div) | ||
247 | { | ||
248 | /* Write new configuration */ | ||
249 | jz_writef(CPM_DDRCDR, CE(1), CLKDIV(div - 1), | ||
250 | CLKSRC(src == X1000_CLK_MPLL ? 2 : 1)); | ||
251 | |||
252 | /* Wait until mux and divider change are complete */ | ||
253 | while(jz_readf(CPM_CSR, DDR_MUX) == 0); | ||
254 | while(jz_readf(CPM_DDRCDR, BUSY)); | ||
255 | |||
256 | /* Disable CE bit after change */ | ||
257 | jz_writef(CPM_DDRCDR, CE(0)); | ||
258 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/clk-x1000.h b/firmware/target/mips/ingenic_x1000/clk-x1000.h new file mode 100644 index 0000000000..76413b90d2 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/clk-x1000.h | |||
@@ -0,0 +1,82 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef __CLK_X1000_H__ | ||
23 | #define __CLK_X1000_H__ | ||
24 | |||
25 | #include <stdint.h> | ||
26 | #include "x1000/cpm.h" | ||
27 | |||
28 | /* Used as arguments to clk_set_ccr_mux() */ | ||
29 | #define CLKMUX_SCLK_A(x) jz_orf(CPM_CCR, SEL_SRC_V(x)) | ||
30 | #define CLKMUX_CPU(x) jz_orf(CPM_CCR, SEL_CPLL_V(x)) | ||
31 | #define CLKMUX_AHB0(x) jz_orf(CPM_CCR, SEL_H0PLL_V(x)) | ||
32 | #define CLKMUX_AHB2(x) jz_orf(CPM_CCR, SEL_H2PLL_V(x)) | ||
33 | |||
34 | typedef enum x1000_clk_t { | ||
35 | X1000_CLK_EXCLK, | ||
36 | X1000_CLK_APLL, | ||
37 | X1000_CLK_MPLL, | ||
38 | X1000_CLK_SCLK_A, | ||
39 | X1000_CLK_CPU, | ||
40 | X1000_CLK_L2CACHE, | ||
41 | X1000_CLK_AHB0, | ||
42 | X1000_CLK_AHB2, | ||
43 | X1000_CLK_PCLK, | ||
44 | X1000_CLK_DDR, | ||
45 | X1000_CLK_LCD, | ||
46 | X1000_CLK_MSC0, | ||
47 | X1000_CLK_MSC1, | ||
48 | X1000_CLK_I2S_MCLK, | ||
49 | X1000_CLK_I2S_BCLK, | ||
50 | X1000_CLK_SFC, | ||
51 | X1000_CLK_COUNT, | ||
52 | } x1000_clk_t; | ||
53 | |||
54 | /* Calculate the current frequency of a clock */ | ||
55 | extern uint32_t clk_get(x1000_clk_t clk); | ||
56 | |||
57 | /* Get the name of a clock for debug purposes */ | ||
58 | extern const char* clk_get_name(x1000_clk_t clk); | ||
59 | |||
60 | /* Sets system clock multiplexers */ | ||
61 | extern void clk_set_ccr_mux(uint32_t muxbits); | ||
62 | |||
63 | /* Sets system clock dividers */ | ||
64 | extern void clk_set_ccr_div(int cpu, int l2, int ahb0, int ahb2, int pclk); | ||
65 | |||
66 | /* Sets DDR clock source and divider */ | ||
67 | extern void clk_set_ddr(x1000_clk_t src, uint32_t div); | ||
68 | |||
69 | /* Returns the smallest n such that infreq/n <= outfreq */ | ||
70 | inline uint32_t clk_calc_div(uint32_t infreq, uint32_t outfreq) | ||
71 | { | ||
72 | return (infreq + (outfreq - 1)) / outfreq; | ||
73 | } | ||
74 | |||
75 | /* Returns the smallest n such that (infreq >> n) <= outfreq */ | ||
76 | inline uint32_t clk_calc_shift(uint32_t infreq, uint32_t outfreq) | ||
77 | { | ||
78 | uint32_t div = clk_calc_div(infreq, outfreq); | ||
79 | return __builtin_clz(div) ^ 31; | ||
80 | } | ||
81 | |||
82 | #endif /* __CLK_X1000_H__ */ | ||
diff --git a/firmware/target/mips/ingenic_x1000/crt0.S b/firmware/target/mips/ingenic_x1000/crt0.S new file mode 100644 index 0000000000..b717f96692 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/crt0.S | |||
@@ -0,0 +1,265 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "config.h" | ||
23 | #include "mips.h" | ||
24 | |||
25 | .text | ||
26 | .extern main | ||
27 | .global _start | ||
28 | |||
29 | .set push | ||
30 | .set mips32 | ||
31 | .set noreorder | ||
32 | .set noat | ||
33 | |||
34 | .section .init.text | ||
35 | |||
36 | _start: | ||
37 | /* Clear data watchpoint */ | ||
38 | mtc0 zero, C0_WATCHLO | ||
39 | mtc0 zero, C0_WATCHHI | ||
40 | |||
41 | /* Set BEV, ERL, mask interrupts */ | ||
42 | li v0, 0x40fc04 | ||
43 | mtc0 v0, C0_Status | ||
44 | |||
45 | /* Set Cause_IV to 1 (use special interrupt vector) */ | ||
46 | li v0, M_CauseIV | ||
47 | mtc0 v0, C0_Cause | ||
48 | |||
49 | /* Set CPU_MODE and BUS_MODE to 1 in CPM_OPCR (Ingenic does this) */ | ||
50 | lui v0, 0xb000 | ||
51 | lw v1, 0x24(v0) | ||
52 | ori v1, v1, 0x22 | ||
53 | sw v1, 0x24(v0) | ||
54 | |||
55 | /* Enable kseg0 cacheability */ | ||
56 | li v0, 3 | ||
57 | mtc0 v0, C0_Config | ||
58 | nop | ||
59 | |||
60 | /* According to ingenic: "enable idx-store-data cache insn" */ | ||
61 | li v0, 0x20000000 | ||
62 | mtc0 v0, C0_ErrCtl | ||
63 | |||
64 | /* Cache init */ | ||
65 | li v0, 0x80000000 | ||
66 | ori v1, v0, 0x4000 | ||
67 | mtc0 zero, C0_TAGLO | ||
68 | mtc0 zero, C0_TAGHI | ||
69 | _cache_loop: | ||
70 | cache ICIndexStTag, 0(v0) | ||
71 | cache DCIndexStTag, 0(v0) | ||
72 | addiu v0, v0, 32 | ||
73 | bne v0, v1, _cache_loop | ||
74 | nop | ||
75 | |||
76 | /* Invalidate BTB */ | ||
77 | mfc0 v0, C0_Config, 7 | ||
78 | nop | ||
79 | ori v0, v0, 2 | ||
80 | mtc0 v0, C0_Config, 7 | ||
81 | nop | ||
82 | |||
83 | #ifndef BOOTLOADER_SPL | ||
84 | /* Copy IRAM from BSS to low memory. */ | ||
85 | la t0, _iramcopy | ||
86 | la t1, _iramstart | ||
87 | la t2, _iramend | ||
88 | _iram_loop: | ||
89 | lw t3, 0(t0) | ||
90 | addiu t1, 4 | ||
91 | addiu t0, 4 | ||
92 | bne t1, t2, _iram_loop | ||
93 | sw t3, -4(t1) | ||
94 | #endif | ||
95 | |||
96 | /* Clear the BSS segment (needed to zero-initialize C static values) */ | ||
97 | la t0, _bssbegin | ||
98 | la t1, _bssend | ||
99 | beq t0, t1, _bss_done | ||
100 | _bss_loop: | ||
101 | addiu t0, 4 | ||
102 | bne t0, t1, _bss_loop | ||
103 | sw zero, -4(t0) | ||
104 | _bss_done: | ||
105 | |||
106 | #ifndef BOOTLOADER_SPL | ||
107 | /* Set stack pointer and clear the stack */ | ||
108 | la sp, stackend | ||
109 | la t0, stackbegin | ||
110 | li t1, 0xDEADBEEF | ||
111 | _stack_loop: | ||
112 | addiu t0, 4 | ||
113 | bne t0, sp, _stack_loop | ||
114 | sw t1, -4(t0) | ||
115 | |||
116 | /* Clear the IRQ stack */ | ||
117 | la k0, _irqstackend | ||
118 | la t0, _irqstackbegin | ||
119 | _irqstack_loop: | ||
120 | addiu t0, 4 | ||
121 | bne t0, k0, _irqstack_loop | ||
122 | sw t1, -4(t0) | ||
123 | #endif | ||
124 | |||
125 | /* Jump to C code */ | ||
126 | j main | ||
127 | nop | ||
128 | |||
129 | #ifndef BOOTLOADER_SPL | ||
130 | /* Exception entry points */ | ||
131 | .section .vectors.1, "ax", %progbits | ||
132 | j tlb_refill_handler | ||
133 | nop | ||
134 | |||
135 | .section .vectors.2, "ax", %progbits | ||
136 | j real_exception_handler | ||
137 | nop | ||
138 | |||
139 | .section .vectors.3, "ax", %progbits | ||
140 | j real_exception_handler | ||
141 | nop | ||
142 | |||
143 | .section .vectors.4, "ax", %progbits | ||
144 | j real_exception_handler | ||
145 | nop | ||
146 | |||
147 | .section .vectors, "ax", %progbits | ||
148 | real_exception_handler: | ||
149 | move k0, sp | ||
150 | la sp, _irqstackend | ||
151 | addiu sp, -0x84 | ||
152 | sw k0, 0x80(sp) | ||
153 | sw ra, 0x00(sp) | ||
154 | sw fp, 0x04(sp) | ||
155 | sw gp, 0x08(sp) | ||
156 | sw t9, 0x0c(sp) | ||
157 | sw t8, 0x10(sp) | ||
158 | sw s7, 0x14(sp) | ||
159 | sw s6, 0x18(sp) | ||
160 | sw s5, 0x1c(sp) | ||
161 | sw s4, 0x20(sp) | ||
162 | sw s3, 0x24(sp) | ||
163 | sw s2, 0x28(sp) | ||
164 | sw s1, 0x2c(sp) | ||
165 | sw s0, 0x30(sp) | ||
166 | sw t7, 0x34(sp) | ||
167 | sw t6, 0x38(sp) | ||
168 | sw t5, 0x3c(sp) | ||
169 | sw t4, 0x40(sp) | ||
170 | sw t3, 0x44(sp) | ||
171 | sw t2, 0x48(sp) | ||
172 | sw t1, 0x4c(sp) | ||
173 | sw t0, 0x50(sp) | ||
174 | sw a3, 0x54(sp) | ||
175 | sw a2, 0x58(sp) | ||
176 | sw a1, 0x5c(sp) | ||
177 | sw a0, 0x60(sp) | ||
178 | sw v1, 0x64(sp) | ||
179 | sw v0, 0x68(sp) | ||
180 | sw $1, 0x6c(sp) | ||
181 | mflo k0 | ||
182 | nop | ||
183 | sw k0, 0x70(sp) | ||
184 | mfhi k0 | ||
185 | nop | ||
186 | sw k0, 0x74(sp) | ||
187 | mfc0 k0, C0_STATUS | ||
188 | nop | ||
189 | nop | ||
190 | nop | ||
191 | sw k0, 0x78(sp) | ||
192 | mfc0 k0, C0_EPC | ||
193 | nop | ||
194 | nop | ||
195 | nop | ||
196 | sw k0, 0x7c(sp) | ||
197 | |||
198 | li k1, M_CauseExcCode | ||
199 | mfc0 a0, C0_CAUSE | ||
200 | and k0, a0, k1 | ||
201 | bnez k0, _exception | ||
202 | nop | ||
203 | jal intr_handler | ||
204 | nop | ||
205 | j _exception_return | ||
206 | |||
207 | _exception: | ||
208 | mfc0 a1, C0_EPC | ||
209 | nop | ||
210 | nop | ||
211 | nop | ||
212 | jal exception_handler | ||
213 | move a2, sp | ||
214 | |||
215 | _exception_return: | ||
216 | lw ra, 0x00(sp) | ||
217 | lw fp, 0x04(sp) | ||
218 | lw gp, 0x08(sp) | ||
219 | lw t9, 0x0c(sp) | ||
220 | lw t8, 0x10(sp) | ||
221 | lw s7, 0x14(sp) | ||
222 | lw s6, 0x18(sp) | ||
223 | lw s5, 0x1c(sp) | ||
224 | lw s4, 0x20(sp) | ||
225 | lw s3, 0x24(sp) | ||
226 | lw s2, 0x28(sp) | ||
227 | lw s1, 0x2c(sp) | ||
228 | lw s0, 0x30(sp) | ||
229 | lw t7, 0x34(sp) | ||
230 | lw t6, 0x38(sp) | ||
231 | lw t5, 0x3c(sp) | ||
232 | lw t4, 0x40(sp) | ||
233 | lw t3, 0x44(sp) | ||
234 | lw t2, 0x48(sp) | ||
235 | lw t1, 0x4c(sp) | ||
236 | lw t0, 0x50(sp) | ||
237 | lw a3, 0x54(sp) | ||
238 | lw a2, 0x58(sp) | ||
239 | lw a1, 0x5c(sp) | ||
240 | lw a0, 0x60(sp) | ||
241 | lw v1, 0x64(sp) | ||
242 | lw v0, 0x68(sp) | ||
243 | lw $1, 0x6c(sp) | ||
244 | lw k0, 0x70(sp) | ||
245 | mtlo k0 | ||
246 | nop | ||
247 | lw k0, 0x74(sp) | ||
248 | mthi k0 | ||
249 | nop | ||
250 | lw k0, 0x78(sp) | ||
251 | mtc0 k0, C0_STATUS | ||
252 | nop | ||
253 | nop | ||
254 | nop | ||
255 | lw k0, 0x7c(sp) | ||
256 | mtc0 k0, C0_EPC | ||
257 | nop | ||
258 | nop | ||
259 | nop | ||
260 | lw sp, 0x80(sp) | ||
261 | eret | ||
262 | nop | ||
263 | #endif | ||
264 | |||
265 | .set pop | ||
diff --git a/firmware/target/mips/ingenic_x1000/debug-x1000.c b/firmware/target/mips/ingenic_x1000/debug-x1000.c new file mode 100644 index 0000000000..fed586691c --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/debug-x1000.c | |||
@@ -0,0 +1,215 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef BOOTLOADER | ||
23 | #include "system.h" | ||
24 | #include "kernel.h" | ||
25 | #include "button.h" | ||
26 | #include "lcd.h" | ||
27 | #include "font.h" | ||
28 | #include "action.h" | ||
29 | #include "list.h" | ||
30 | |||
31 | #include "clk-x1000.h" | ||
32 | #include "gpio-x1000.h" | ||
33 | |||
34 | static bool dbg_clocks(void) | ||
35 | { | ||
36 | do { | ||
37 | lcd_clear_display(); | ||
38 | int line = 0; | ||
39 | for(int i = 0; i < X1000_CLK_COUNT; ++i) { | ||
40 | uint32_t hz = clk_get(i); | ||
41 | uint32_t khz = hz / 1000; | ||
42 | uint32_t mhz = khz / 1000; | ||
43 | lcd_putsf(2, line++, "%8s %4u,%03u,%03u Hz", clk_get_name(i), | ||
44 | mhz, (khz - mhz*1000), (hz - khz*1000)); | ||
45 | } | ||
46 | |||
47 | lcd_update(); | ||
48 | } while(get_action(CONTEXT_STD, HZ) != ACTION_STD_CANCEL); | ||
49 | |||
50 | return false; | ||
51 | } | ||
52 | |||
53 | static void dbg_gpios_show_state(void) | ||
54 | { | ||
55 | const char portname[] = "ABCD"; | ||
56 | for(int i = 0; i < 4; ++i) | ||
57 | lcd_putsf(0, i, "GPIO %c: %08x", portname[i], REG_GPIO_PIN(i)); | ||
58 | } | ||
59 | |||
60 | static void dbg_gpios_show_config(void) | ||
61 | { | ||
62 | const char portname[] = "ABCD"; | ||
63 | int line = 0; | ||
64 | for(int i = 0; i < 4; ++i) { | ||
65 | uint32_t intr = REG_GPIO_INT(i); | ||
66 | uint32_t mask = REG_GPIO_MSK(i); | ||
67 | uint32_t pat0 = REG_GPIO_PAT0(i); | ||
68 | uint32_t pat1 = REG_GPIO_PAT1(i); | ||
69 | lcd_putsf(0, line++, "GPIO %c", portname[i]); | ||
70 | lcd_putsf(2, line++, " int %08lx", intr); | ||
71 | lcd_putsf(2, line++, " msk %08lx", mask); | ||
72 | lcd_putsf(2, line++, "pat0 %08lx", pat0); | ||
73 | lcd_putsf(2, line++, "pat1 %08lx", pat1); | ||
74 | line++; | ||
75 | } | ||
76 | } | ||
77 | |||
78 | static bool dbg_gpios(void) | ||
79 | { | ||
80 | enum { STATE, CONFIG, NUM_SCREENS }; | ||
81 | const int timeouts[NUM_SCREENS] = { 1, HZ }; | ||
82 | int screen = STATE; | ||
83 | |||
84 | while(1) { | ||
85 | lcd_clear_display(); | ||
86 | switch(screen) { | ||
87 | case CONFIG: | ||
88 | dbg_gpios_show_config(); | ||
89 | break; | ||
90 | case STATE: | ||
91 | dbg_gpios_show_state(); | ||
92 | break; | ||
93 | } | ||
94 | |||
95 | lcd_update(); | ||
96 | |||
97 | switch(get_action(CONTEXT_STD, timeouts[screen])) { | ||
98 | case ACTION_STD_CANCEL: | ||
99 | return false; | ||
100 | case ACTION_STD_PREV: | ||
101 | case ACTION_STD_PREVREPEAT: | ||
102 | screen -= 1; | ||
103 | if(screen < 0) | ||
104 | screen = NUM_SCREENS - 1; | ||
105 | break; | ||
106 | case ACTION_STD_NEXT: | ||
107 | case ACTION_STD_NEXTREPEAT: | ||
108 | screen += 1; | ||
109 | if(screen >= NUM_SCREENS) | ||
110 | screen = 0; | ||
111 | break; | ||
112 | default: | ||
113 | break; | ||
114 | } | ||
115 | } | ||
116 | |||
117 | return false; | ||
118 | } | ||
119 | |||
120 | extern volatile unsigned aic_tx_underruns; | ||
121 | |||
122 | static bool dbg_audio(void) | ||
123 | { | ||
124 | do { | ||
125 | lcd_clear_display(); | ||
126 | lcd_putsf(0, 0, "TX underruns: %u", aic_tx_underruns); | ||
127 | lcd_update(); | ||
128 | } while(get_action(CONTEXT_STD, HZ) != ACTION_STD_CANCEL); | ||
129 | |||
130 | return false; | ||
131 | } | ||
132 | |||
133 | static bool dbg_cpuidle(void) | ||
134 | { | ||
135 | do { | ||
136 | lcd_clear_display(); | ||
137 | lcd_putsf(0, 0, "CPU idle time: %d.%01d%%", | ||
138 | __cpu_idle_cur/10, __cpu_idle_cur%10); | ||
139 | lcd_putsf(0, 1, "CPU frequency: %d.%03d MHz", | ||
140 | FREQ/1000000, (FREQ%1000000)/1000); | ||
141 | lcd_update(); | ||
142 | } while(get_action(CONTEXT_STD, HZ) != ACTION_STD_CANCEL); | ||
143 | |||
144 | return false; | ||
145 | } | ||
146 | |||
147 | #ifdef FIIO_M3K | ||
148 | extern bool dbg_fiiom3k_touchpad(void); | ||
149 | extern bool axp173_debug_menu(void); | ||
150 | #endif | ||
151 | |||
152 | /* Menu definition */ | ||
153 | static const struct { | ||
154 | const char* name; | ||
155 | bool(*function)(void); | ||
156 | } menuitems[] = { | ||
157 | {"Clocks", &dbg_clocks}, | ||
158 | {"GPIOs", &dbg_gpios}, | ||
159 | {"CPU idle", &dbg_cpuidle}, | ||
160 | {"Audio", &dbg_audio}, | ||
161 | #ifdef FIIO_M3K | ||
162 | {"Touchpad", &dbg_fiiom3k_touchpad}, | ||
163 | {"Power stats", &axp173_debug_menu}, | ||
164 | #endif | ||
165 | }; | ||
166 | |||
167 | static int hw_info_menu_action_cb(int btn, struct gui_synclist* lists) | ||
168 | { | ||
169 | if(btn == ACTION_STD_OK) { | ||
170 | int sel = gui_synclist_get_sel_pos(lists); | ||
171 | FOR_NB_SCREENS(i) | ||
172 | viewportmanager_theme_enable(i, false, NULL); | ||
173 | |||
174 | lcd_setfont(FONT_SYSFIXED); | ||
175 | lcd_set_foreground(LCD_WHITE); | ||
176 | lcd_set_background(LCD_BLACK); | ||
177 | |||
178 | if(menuitems[sel].function()) | ||
179 | btn = SYS_USB_CONNECTED; | ||
180 | else | ||
181 | btn = ACTION_REDRAW; | ||
182 | |||
183 | lcd_setfont(FONT_UI); | ||
184 | |||
185 | FOR_NB_SCREENS(i) | ||
186 | viewportmanager_theme_undo(i, false); | ||
187 | } | ||
188 | |||
189 | return btn; | ||
190 | } | ||
191 | |||
192 | static const char* hw_info_menu_get_name(int item, void* data, | ||
193 | char* buffer, size_t buffer_len) | ||
194 | { | ||
195 | (void)buffer; | ||
196 | (void)buffer_len; | ||
197 | (void)data; | ||
198 | return menuitems[item].name; | ||
199 | } | ||
200 | |||
201 | bool dbg_hw_info(void) | ||
202 | { | ||
203 | struct simplelist_info info; | ||
204 | simplelist_info_init(&info, MODEL_NAME " debug menu", | ||
205 | ARRAYLEN(menuitems), NULL); | ||
206 | info.action_callback = hw_info_menu_action_cb; | ||
207 | info.get_name = hw_info_menu_get_name; | ||
208 | return simplelist_show_list(&info); | ||
209 | } | ||
210 | |||
211 | bool dbg_ports(void) | ||
212 | { | ||
213 | return false; | ||
214 | } | ||
215 | #endif | ||
diff --git a/firmware/target/mips/ingenic_x1000/dma-x1000.c b/firmware/target/mips/ingenic_x1000/dma-x1000.c new file mode 100644 index 0000000000..28fd328a85 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/dma-x1000.c | |||
@@ -0,0 +1,91 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "system.h" | ||
23 | #include "dma-x1000.h" | ||
24 | #include "irq-x1000.h" | ||
25 | #include "x1000/cpm.h" | ||
26 | #include "panic.h" | ||
27 | |||
28 | static dma_cb_func dma_callbacks[DMA_NUM_USED_CHANNELS]; | ||
29 | |||
30 | static void dma_no_cb(int event) | ||
31 | { | ||
32 | (void)event; | ||
33 | panicf("Unhandled DMA channel interrupt"); | ||
34 | } | ||
35 | |||
36 | void dma_init(void) | ||
37 | { | ||
38 | for(int i = 0; i < DMA_NUM_USED_CHANNELS; ++i) | ||
39 | dma_callbacks[i] = dma_no_cb; | ||
40 | |||
41 | jz_writef(CPM_CLKGR, PDMA(0)); | ||
42 | jz_writef(DMA_CTRL, ENABLE(1), HALT(0), AR(0)); | ||
43 | jz_writef(DMA_CTRL, FMSC(1), FSSI(1), FTSSI(1), FUART(1), FAIC(1)); | ||
44 | system_enable_irq(IRQ_PDMA); | ||
45 | system_enable_irq(IRQ_PDMAD); | ||
46 | } | ||
47 | |||
48 | void dma_set_callback(int chn, dma_cb_func cb) | ||
49 | { | ||
50 | dma_callbacks[chn] = cb != NULL ? cb : dma_no_cb; | ||
51 | } | ||
52 | |||
53 | void PDMA(void) | ||
54 | { | ||
55 | /* This is called when the last descriptor completes, or if the | ||
56 | * channel hits an error. | ||
57 | */ | ||
58 | unsigned pending = REG_DMA_IRQP; | ||
59 | for(int i = 0; i < DMA_NUM_USED_CHANNELS; ++i) { | ||
60 | if((pending & (1 << i)) == 0) | ||
61 | continue; | ||
62 | |||
63 | int evt; | ||
64 | if(REG_DMA_CHN_CS(i) & jz_orm(DMA_CHN_CS, AR, HLT)) | ||
65 | evt = DMA_EVENT_ERROR; | ||
66 | else | ||
67 | evt = DMA_EVENT_COMPLETE; | ||
68 | |||
69 | REG_DMA_CHN_CS(i) = 0; | ||
70 | dma_callbacks[i](evt); | ||
71 | } | ||
72 | |||
73 | /* Clear any errors and clear interrupts */ | ||
74 | jz_writef(DMA_CTRL, HALT(0), AR(0)); | ||
75 | REG_DMA_IRQP = 0; | ||
76 | } | ||
77 | |||
78 | void PDMAD(void) | ||
79 | { | ||
80 | /* Called when TIE is set on a non-final descriptor */ | ||
81 | unsigned pending = REG_DMA_DIP; | ||
82 | for(int i = 0; i < DMA_NUM_USED_CHANNELS; ++i) { | ||
83 | if((pending & (1 << i)) == 0) | ||
84 | continue; | ||
85 | |||
86 | dma_callbacks[i](DMA_EVENT_INTERRUPT); | ||
87 | } | ||
88 | |||
89 | /* This does not operate like other clear registers */ | ||
90 | REG_DMA_DIC &= ~pending; | ||
91 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/dma-x1000.h b/firmware/target/mips/ingenic_x1000/dma-x1000.h new file mode 100644 index 0000000000..d836a0cf54 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/dma-x1000.h | |||
@@ -0,0 +1,69 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef __DMA_X1000_H__ | ||
23 | #define __DMA_X1000_H__ | ||
24 | |||
25 | #include "x1000/dma.h" | ||
26 | #include "x1000/dma_chn.h" | ||
27 | #include <stdint.h> | ||
28 | |||
29 | /* Events passed to DMA callbacks */ | ||
30 | #define DMA_EVENT_NONE 0 /* Not used by DMA code but can be used as | ||
31 | * a sentinel value to indicate "no event" */ | ||
32 | #define DMA_EVENT_INTERRUPT 1 /* Interrupt on a non-final descriptor */ | ||
33 | #define DMA_EVENT_COMPLETE 2 /* Completed the final descriptor */ | ||
34 | #define DMA_EVENT_ERROR 3 /* Some kind of error occurred */ | ||
35 | |||
36 | /* All DMA channels which use interrupts must be statically defined here. | ||
37 | * The channel numbering should be contiguous, and lower channel numbers | ||
38 | * will have lower interrupt latency because they're serviced first. | ||
39 | * | ||
40 | * Channels >= DMA_NUM_USED_CHANNELS will NOT have interrupts serviced! | ||
41 | * Due to the possibility of address error interrupts that can occur even | ||
42 | * if no interrupts are requested on the channel, the unallocated channels | ||
43 | * cannot be used safely. | ||
44 | */ | ||
45 | #define DMA_CHANNEL_AUDIO 0 | ||
46 | #define DMA_CHANNEL_FBCOPY 1 | ||
47 | #define DMA_NUM_USED_CHANNELS 2 | ||
48 | |||
49 | struct dma_desc { | ||
50 | uint32_t cm; /* meaning and layout same as DMA_CHN_CM */ | ||
51 | uint32_t sa; /* source address */ | ||
52 | uint32_t ta; /* target address */ | ||
53 | uint32_t tc; /* low 24 bits: transfer count | ||
54 | * upper 8 bits: offset to next descriptor | ||
55 | */ | ||
56 | uint32_t sd; /* same as DMA_CHN_SD */ | ||
57 | uint32_t rt; /* request type, same as DMA_CHN_RT */ | ||
58 | uint32_t pad0; | ||
59 | uint32_t pad1; | ||
60 | } __attribute__((aligned(32))); | ||
61 | |||
62 | typedef struct dma_desc dma_desc; | ||
63 | |||
64 | typedef void(*dma_cb_func)(int event); | ||
65 | |||
66 | extern void dma_init(void); | ||
67 | extern void dma_set_callback(int chn, dma_cb_func cb); | ||
68 | |||
69 | #endif /* __DMA_X1000_H__ */ | ||
diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/adc-target.h b/firmware/target/mips/ingenic_x1000/fiiom3k/adc-target.h new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/fiiom3k/adc-target.h | |||
diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/audiohw-fiiom3k.c b/firmware/target/mips/ingenic_x1000/fiiom3k/audiohw-fiiom3k.c new file mode 100644 index 0000000000..2f43809523 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/fiiom3k/audiohw-fiiom3k.c | |||
@@ -0,0 +1,81 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "audiohw.h" | ||
23 | #include "system.h" | ||
24 | #include "pcm_sampr.h" | ||
25 | #include "logf.h" | ||
26 | #include "aic-x1000.h" | ||
27 | #include "i2c-x1000.h" | ||
28 | #include "gpio-x1000.h" | ||
29 | #include "x1000/aic.h" | ||
30 | #include "x1000/cpm.h" | ||
31 | |||
32 | void audiohw_init(void) | ||
33 | { | ||
34 | /* Configure AIC for I2S operation */ | ||
35 | jz_writef(CPM_CLKGR, AIC(0)); | ||
36 | gpio_config(GPIO_B, 0x1f, GPIO_DEVICE(1)); | ||
37 | jz_writef(AIC_I2SCR, STPBK(1)); | ||
38 | |||
39 | /* Operate as I2S master, use external codec */ | ||
40 | jz_writef(AIC_CFG, AUSEL(1), ICDC(0), BCKD(1), SYNCD(1), LSMP(1)); | ||
41 | jz_writef(AIC_I2SCR, ESCLK(1), AMSL(0)); | ||
42 | |||
43 | /* Stereo audio, packed 16 bit samples */ | ||
44 | jz_writef(AIC_CCR, PACK16(1), CHANNEL(1), OSS(1)); | ||
45 | |||
46 | /* Initialize DAC */ | ||
47 | i2c_x1000_set_freq(AK4376_BUS, I2C_FREQ_400K); | ||
48 | ak4376_init(); | ||
49 | } | ||
50 | |||
51 | void audiohw_postinit(void) | ||
52 | { | ||
53 | } | ||
54 | |||
55 | void audiohw_close(void) | ||
56 | { | ||
57 | ak4376_close(); | ||
58 | } | ||
59 | |||
60 | void ak4376_set_pdn_pin(int level) | ||
61 | { | ||
62 | gpio_config(GPIO_A, 1 << 16, GPIO_OUTPUT(level ? 1 : 0)); | ||
63 | } | ||
64 | |||
65 | int ak4376_set_mclk_freq(int hw_freq, bool enabled) | ||
66 | { | ||
67 | /* Get the multiplier */ | ||
68 | int freq = hw_freq_sampr[hw_freq]; | ||
69 | int mult = freq >= SAMPR_176 ? 128 : 256; | ||
70 | |||
71 | if(enabled) { | ||
72 | /* Set the new frequency; clock is enabled afterward */ | ||
73 | if(aic_i2s_set_mclk(X1000_CLK_SCLK_A, freq, mult)) | ||
74 | logf("WARNING: unachievable audio rate %d x %d!?", freq, mult); | ||
75 | } else { | ||
76 | /* Shut off the clock */ | ||
77 | jz_writef(AIC_I2SCR, STPBK(1)); | ||
78 | } | ||
79 | |||
80 | return mult; | ||
81 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/backlight-fiiom3k.c b/firmware/target/mips/ingenic_x1000/fiiom3k/backlight-fiiom3k.c new file mode 100644 index 0000000000..f02fcaaee8 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/fiiom3k/backlight-fiiom3k.c | |||
@@ -0,0 +1,88 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "backlight.h" | ||
23 | #include "backlight-target.h" | ||
24 | #include "lcd.h" | ||
25 | #include "pwm-x1000.h" | ||
26 | |||
27 | #define BL_LCD_CHN 0 | ||
28 | #define BL_LCD_PERIOD 33000 | ||
29 | |||
30 | #define BL_BTN_CHN 4 | ||
31 | #define BL_BTN_PERIOD 100000 | ||
32 | |||
33 | static int backlight_calc_duty(int period, int min_duty, int brightness) | ||
34 | { | ||
35 | return min_duty + (period - min_duty) * brightness / MAX_BRIGHTNESS_SETTING; | ||
36 | } | ||
37 | |||
38 | bool backlight_hw_init(void) | ||
39 | { | ||
40 | pwm_init(BL_LCD_CHN); | ||
41 | pwm_init(BL_BTN_CHN); | ||
42 | pwm_enable(BL_LCD_CHN); | ||
43 | pwm_enable(BL_BTN_CHN); | ||
44 | backlight_hw_brightness(MAX_BRIGHTNESS_SETTING); | ||
45 | buttonlight_hw_brightness(MAX_BRIGHTNESS_SETTING); | ||
46 | /* TODO: avoid buttonlight flicker when powering up the machine */ | ||
47 | return true; | ||
48 | } | ||
49 | |||
50 | void backlight_hw_on(void) | ||
51 | { | ||
52 | pwm_enable(BL_LCD_CHN); | ||
53 | #ifdef HAVE_LCD_ENABLE | ||
54 | lcd_enable(true); | ||
55 | #endif | ||
56 | } | ||
57 | |||
58 | void backlight_hw_off(void) | ||
59 | { | ||
60 | pwm_disable(BL_LCD_CHN); | ||
61 | #ifdef HAVE_LCD_ENABLE | ||
62 | lcd_enable(false); | ||
63 | #endif | ||
64 | } | ||
65 | |||
66 | void backlight_hw_brightness(int brightness) | ||
67 | { | ||
68 | int duty_ns = backlight_calc_duty(BL_LCD_PERIOD, 0, brightness); | ||
69 | pwm_set_period(BL_LCD_CHN, BL_LCD_PERIOD, duty_ns); | ||
70 | } | ||
71 | |||
72 | void buttonlight_hw_on(void) | ||
73 | { | ||
74 | pwm_enable(BL_BTN_CHN); | ||
75 | } | ||
76 | |||
77 | void buttonlight_hw_off(void) | ||
78 | { | ||
79 | pwm_disable(BL_BTN_CHN); | ||
80 | } | ||
81 | |||
82 | void buttonlight_hw_brightness(int brightness) | ||
83 | { | ||
84 | /* Duty cycle below 11% seems to turn the buttonlight off entirely, | ||
85 | * so we need to rescale the range */ | ||
86 | int duty_ns = backlight_calc_duty(BL_BTN_PERIOD, BL_BTN_PERIOD*11/100, brightness); | ||
87 | pwm_set_period(BL_BTN_CHN, BL_BTN_PERIOD, duty_ns); | ||
88 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/backlight-target.h b/firmware/target/mips/ingenic_x1000/fiiom3k/backlight-target.h new file mode 100644 index 0000000000..791a013c32 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/fiiom3k/backlight-target.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef __BACKLIGHT_TARGET_H__ | ||
23 | #define __BACKLIGHT_TARGET_H__ | ||
24 | |||
25 | #include <stdbool.h> | ||
26 | |||
27 | extern bool backlight_hw_init(void); | ||
28 | |||
29 | extern void backlight_hw_on(void); | ||
30 | extern void backlight_hw_off(void); | ||
31 | extern void backlight_hw_brightness(int brightness); | ||
32 | |||
33 | extern void buttonlight_hw_on(void); | ||
34 | extern void buttonlight_hw_off(void); | ||
35 | extern void buttonlight_hw_brightness(int brightness); | ||
36 | |||
37 | #endif /* __BACKLIGHT_TARGET_H__ */ | ||
diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/button-fiiom3k.c b/firmware/target/mips/ingenic_x1000/fiiom3k/button-fiiom3k.c new file mode 100644 index 0000000000..db5ece10b0 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/fiiom3k/button-fiiom3k.c | |||
@@ -0,0 +1,503 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "button.h" | ||
23 | #include "kernel.h" | ||
24 | #include "backlight.h" | ||
25 | #include "panic.h" | ||
26 | #include "lcd.h" | ||
27 | #include "gpio-x1000.h" | ||
28 | #include "i2c-x1000.h" | ||
29 | #include <string.h> | ||
30 | #include <stdbool.h> | ||
31 | |||
32 | #ifndef BOOTLOADER | ||
33 | # include "font.h" | ||
34 | #endif | ||
35 | |||
36 | #define FT_RST_PIN (1 << 15) | ||
37 | #define FT_INT_PIN (1 << 12) | ||
38 | #define ft_interrupt GPIOB12 | ||
39 | |||
40 | /* Touch event types */ | ||
41 | #define EVENT_NONE (-1) | ||
42 | #define EVENT_PRESS 0 | ||
43 | #define EVENT_RELEASE 1 | ||
44 | #define EVENT_CONTACT 2 | ||
45 | |||
46 | /* FSM states */ | ||
47 | #define STATE_IDLE 0 | ||
48 | #define STATE_PRESS 1 | ||
49 | #define STATE_REPORT 2 | ||
50 | #define STATE_SCROLL_PRESS 3 | ||
51 | #define STATE_SCROLLING 4 | ||
52 | |||
53 | /* Assume there's no active touch if no event is reported in this time */ | ||
54 | #define AUTORELEASE_TIME (10000 * OST_TICKS_PER_US) | ||
55 | |||
56 | /* If there's no significant motion on the scrollbar for this time, | ||
57 | * then report it as a button press instead */ | ||
58 | #define SCROLL_PRESS_TIME (100000 * OST_TICKS_PER_US) | ||
59 | |||
60 | /* If a press on the scrollbar moves more than this during SCROLL_PRESS_TIME, | ||
61 | * then we enter scrolling mode. */ | ||
62 | #define MIN_SCROLL_THRESH 15 | ||
63 | |||
64 | /* If OST tick a is after OST tick b, then returns the number of ticks | ||
65 | * in the interval between a and b; otherwise undefined. */ | ||
66 | #define TICKS_SINCE(a, b) ((a) - (b)) | ||
67 | |||
68 | /* Number of touch samples to smooth before reading */ | ||
69 | #define TOUCH_SAMPLES 3 | ||
70 | |||
71 | static struct ft_driver { | ||
72 | int i2c_cookie; | ||
73 | i2c_descriptor i2c_desc; | ||
74 | uint8_t raw_data[6]; | ||
75 | bool active; | ||
76 | |||
77 | /* Number of pixels squared which must be moved before | ||
78 | * a scrollbar pulse is generated */ | ||
79 | int scroll_thresh_sqr; | ||
80 | } ftd; | ||
81 | |||
82 | static struct ft_state_machine { | ||
83 | /* Current button state, used by button_read_device() */ | ||
84 | int buttons; | ||
85 | |||
86 | /* FSM state */ | ||
87 | int state; | ||
88 | |||
89 | /* Time of the last touch event, as 32-bit OST timestamp. The kernel | ||
90 | * tick is simply too low-resolution to work reliably, especially as | ||
91 | * we handle touchpad events asynchronously. */ | ||
92 | uint32_t last_event_t; | ||
93 | |||
94 | /* Time of entering the SCROLL_PRESS state, used to differentiate | ||
95 | * between a press, hold, or scrolling motion */ | ||
96 | uint32_t scroll_press_t; | ||
97 | |||
98 | /* Number of CONTACT events sampled in the PRESS state. | ||
99 | * Must reach TOUCH_SAMPLES before we move forward. */ | ||
100 | int samples; | ||
101 | |||
102 | /* Filter for smoothing touch points */ | ||
103 | int sum_x, sum_y; | ||
104 | |||
105 | /* Position of the original touch */ | ||
106 | int orig_x, orig_y; | ||
107 | |||
108 | /* Current touch position */ | ||
109 | int cur_x, cur_y; | ||
110 | } fsm; | ||
111 | |||
112 | static int touch_to_button(int x, int y) | ||
113 | { | ||
114 | if(x == 900) { | ||
115 | /* Right strip */ | ||
116 | if(y == 80) | ||
117 | return BUTTON_BACK; | ||
118 | else if(y == 240) | ||
119 | return BUTTON_RIGHT; | ||
120 | else | ||
121 | return 0; | ||
122 | } else if(x < 80) { | ||
123 | /* Left strip */ | ||
124 | if(y < 80) | ||
125 | return BUTTON_MENU; | ||
126 | else if(y > 190) | ||
127 | return BUTTON_LEFT; | ||
128 | else | ||
129 | return 0; | ||
130 | } else { | ||
131 | /* Middle strip */ | ||
132 | if(y < 100) | ||
133 | return BUTTON_UP; | ||
134 | else if(y > 220) | ||
135 | return BUTTON_DOWN; | ||
136 | else | ||
137 | return BUTTON_SELECT; | ||
138 | } | ||
139 | } | ||
140 | |||
141 | static bool ft_accum_touch(uint32_t t, int tx, int ty) | ||
142 | { | ||
143 | /* Record event time */ | ||
144 | fsm.last_event_t = t; | ||
145 | |||
146 | if(fsm.samples < TOUCH_SAMPLES) { | ||
147 | /* Continue "priming" the filter */ | ||
148 | fsm.sum_x += tx; | ||
149 | fsm.sum_y += ty; | ||
150 | fsm.samples += 1; | ||
151 | |||
152 | /* Return if filter is not ready */ | ||
153 | if(fsm.samples < TOUCH_SAMPLES) | ||
154 | return false; | ||
155 | } else { | ||
156 | /* Update filter */ | ||
157 | fsm.sum_x += tx - fsm.sum_x / TOUCH_SAMPLES; | ||
158 | fsm.sum_y += ty - fsm.sum_y / TOUCH_SAMPLES; | ||
159 | } | ||
160 | |||
161 | /* Filter is ready, so read the point */ | ||
162 | fsm.cur_x = fsm.sum_x / TOUCH_SAMPLES; | ||
163 | fsm.cur_y = fsm.sum_y / TOUCH_SAMPLES; | ||
164 | return true; | ||
165 | } | ||
166 | |||
167 | static void ft_go_idle(void) | ||
168 | { | ||
169 | /* Null out the touch state */ | ||
170 | fsm.buttons = 0; | ||
171 | fsm.samples = 0; | ||
172 | fsm.sum_x = fsm.sum_y = 0; | ||
173 | fsm.state = STATE_IDLE; | ||
174 | } | ||
175 | |||
176 | static void ft_start_report(void) | ||
177 | { | ||
178 | /* Report the button bit */ | ||
179 | fsm.buttons = touch_to_button(fsm.cur_x, fsm.cur_y); | ||
180 | fsm.orig_x = fsm.cur_x; | ||
181 | fsm.orig_y = fsm.cur_y; | ||
182 | fsm.state = STATE_REPORT; | ||
183 | } | ||
184 | |||
185 | static void ft_start_report_or_scroll(void) | ||
186 | { | ||
187 | ft_start_report(); | ||
188 | |||
189 | /* If the press occurs on the scrollbar, then we need to | ||
190 | * wait an additional delay before reporting it in case | ||
191 | * this is the beginning of a scrolling motion */ | ||
192 | if(fsm.buttons & (BUTTON_UP|BUTTON_DOWN|BUTTON_SELECT)) { | ||
193 | fsm.buttons = 0; | ||
194 | fsm.scroll_press_t = __ost_read32(); | ||
195 | fsm.state = STATE_SCROLL_PRESS; | ||
196 | } | ||
197 | } | ||
198 | |||
199 | static void ft_step_state(uint32_t t, int evt, int tx, int ty) | ||
200 | { | ||
201 | /* Generate a release event automatically in case we missed it */ | ||
202 | if(evt == EVENT_NONE) { | ||
203 | if(TICKS_SINCE(t, fsm.last_event_t) >= AUTORELEASE_TIME) { | ||
204 | evt = EVENT_RELEASE; | ||
205 | tx = fsm.cur_x; | ||
206 | ty = fsm.cur_y; | ||
207 | } | ||
208 | } | ||
209 | |||
210 | switch(fsm.state) { | ||
211 | case STATE_IDLE: { | ||
212 | if(evt == EVENT_PRESS || evt == EVENT_CONTACT) { | ||
213 | /* Move to REPORT or PRESS state */ | ||
214 | if(ft_accum_touch(t, tx, ty)) | ||
215 | ft_start_report_or_scroll(); | ||
216 | else | ||
217 | fsm.state = STATE_PRESS; | ||
218 | } | ||
219 | } break; | ||
220 | |||
221 | case STATE_PRESS: { | ||
222 | if(evt == EVENT_RELEASE) { | ||
223 | /* Ignore if the number of samples is too low */ | ||
224 | ft_go_idle(); | ||
225 | } else if(evt == EVENT_PRESS || evt == EVENT_CONTACT) { | ||
226 | /* Accumulate the touch position in the filter */ | ||
227 | if(ft_accum_touch(t, tx, ty)) | ||
228 | ft_start_report_or_scroll(); | ||
229 | } | ||
230 | } break; | ||
231 | |||
232 | case STATE_REPORT: { | ||
233 | if(evt == EVENT_RELEASE) | ||
234 | ft_go_idle(); | ||
235 | else if(evt == EVENT_PRESS || evt == EVENT_CONTACT) | ||
236 | ft_accum_touch(t, tx, ty); | ||
237 | } break; | ||
238 | |||
239 | case STATE_SCROLL_PRESS: { | ||
240 | if(evt == EVENT_RELEASE) { | ||
241 | /* This _should_ synthesize a button press. | ||
242 | * | ||
243 | * - ft_start_report() will set the button bit based on the | ||
244 | * current touch position and enter the REPORT state, which | ||
245 | * will automatically hold the bit high | ||
246 | * | ||
247 | * - The next button_read_device() will see the button bit | ||
248 | * and report it back to Rockbox, then step the FSM with | ||
249 | * EVENT_NONE. | ||
250 | * | ||
251 | * - The EVENT_NONE stepping will eventually autogenerate a | ||
252 | * RELEASE event and restore the button state back to 0 | ||
253 | * | ||
254 | * - There's a small logic hole in the REPORT state which | ||
255 | * could cause it to miss an immediately repeated PRESS | ||
256 | * that occurs before the autorelease timeout kicks in. | ||
257 | * FIXME: We might want to special-case that. | ||
258 | */ | ||
259 | ft_start_report(); | ||
260 | break; | ||
261 | } | ||
262 | |||
263 | if(evt == EVENT_PRESS || evt == EVENT_CONTACT) | ||
264 | ft_accum_touch(t, tx, ty); | ||
265 | |||
266 | int dx = fsm.cur_x - fsm.orig_x; | ||
267 | int dy = fsm.cur_y - fsm.orig_y; | ||
268 | int dp = (dx*dx) + (dy*dy); | ||
269 | if(dp >= MIN_SCROLL_THRESH*MIN_SCROLL_THRESH) { | ||
270 | /* Significant motion: enter SCROLLING state */ | ||
271 | fsm.state = STATE_SCROLLING; | ||
272 | } else if(TICKS_SINCE(t, fsm.scroll_press_t) >= SCROLL_PRESS_TIME) { | ||
273 | /* No significant motion: report it as a press */ | ||
274 | fsm.cur_x = fsm.orig_x; | ||
275 | fsm.cur_y = fsm.orig_y; | ||
276 | ft_start_report(); | ||
277 | } | ||
278 | } break; | ||
279 | |||
280 | case STATE_SCROLLING: { | ||
281 | if(evt == EVENT_RELEASE) { | ||
282 | ft_go_idle(); | ||
283 | break; | ||
284 | } | ||
285 | |||
286 | if(evt == EVENT_PRESS || evt == EVENT_CONTACT) | ||
287 | ft_accum_touch(t, tx, ty); | ||
288 | |||
289 | int dx = fsm.cur_x - fsm.orig_x; | ||
290 | int dy = fsm.cur_y - fsm.orig_y; | ||
291 | int dp = (dx*dx) + (dy*dy); | ||
292 | if(dp >= ftd.scroll_thresh_sqr) { | ||
293 | if(dy < 0) { | ||
294 | queue_post(&button_queue, BUTTON_SCROLL_BACK, 0); | ||
295 | } else { | ||
296 | queue_post(&button_queue, BUTTON_SCROLL_FWD, 0); | ||
297 | } | ||
298 | |||
299 | /* Poke the backlight */ | ||
300 | backlight_on(); | ||
301 | buttonlight_on(); | ||
302 | |||
303 | fsm.orig_x = fsm.cur_x; | ||
304 | fsm.orig_y = fsm.cur_y; | ||
305 | } | ||
306 | } break; | ||
307 | |||
308 | default: | ||
309 | panicf("ft6x06: unhandled state"); | ||
310 | break; | ||
311 | } | ||
312 | } | ||
313 | |||
314 | static void ft_i2c_callback(int status, i2c_descriptor* desc) | ||
315 | { | ||
316 | (void)desc; | ||
317 | if(status != I2C_STATUS_OK) | ||
318 | return; | ||
319 | |||
320 | /* The panel is oriented such that its X axis is vertical, | ||
321 | * so swap the axes for reporting */ | ||
322 | int evt = ftd.raw_data[1] >> 6; | ||
323 | int ty = ftd.raw_data[2] | ((ftd.raw_data[1] & 0xf) << 8); | ||
324 | int tx = ftd.raw_data[4] | ((ftd.raw_data[3] & 0xf) << 8); | ||
325 | |||
326 | /* TODO: convert the touch positions to linear positions. | ||
327 | * | ||
328 | * Points reported by the touch controller are distorted and non-linear, | ||
329 | * ideally we'd like to correct these values. There's more precision in | ||
330 | * the middle of the touchpad than on the edges, so scrolling feels slow | ||
331 | * in the middle and faster near the edge. | ||
332 | */ | ||
333 | |||
334 | ft_step_state(__ost_read32(), evt, tx, ty); | ||
335 | } | ||
336 | |||
337 | void ft_interrupt(void) | ||
338 | { | ||
339 | /* We don't care if this fails */ | ||
340 | i2c_async_queue(FT6x06_BUS, TIMEOUT_NOBLOCK, I2C_Q_ONCE, | ||
341 | ftd.i2c_cookie, &ftd.i2c_desc); | ||
342 | } | ||
343 | |||
344 | static void ft_init(void) | ||
345 | { | ||
346 | /* Initialize the driver state */ | ||
347 | ftd.i2c_cookie = i2c_async_reserve_cookies(FT6x06_BUS, 1); | ||
348 | ftd.i2c_desc.slave_addr = FT6x06_ADDR; | ||
349 | ftd.i2c_desc.bus_cond = I2C_START | I2C_STOP; | ||
350 | ftd.i2c_desc.tran_mode = I2C_READ; | ||
351 | ftd.i2c_desc.buffer[0] = &ftd.raw_data[5]; | ||
352 | ftd.i2c_desc.count[0] = 1; | ||
353 | ftd.i2c_desc.buffer[1] = &ftd.raw_data[0]; | ||
354 | ftd.i2c_desc.count[1] = 5; | ||
355 | ftd.i2c_desc.callback = ft_i2c_callback; | ||
356 | ftd.i2c_desc.arg = 0; | ||
357 | ftd.i2c_desc.next = NULL; | ||
358 | ftd.raw_data[5] = 0x02; | ||
359 | ftd.active = true; | ||
360 | touchpad_set_sensitivity(DEFAULT_TOUCHPAD_SENSITIVITY_SETTING); | ||
361 | |||
362 | /* Initialize the state machine */ | ||
363 | fsm.buttons = 0; | ||
364 | fsm.state = STATE_IDLE; | ||
365 | fsm.last_event_t = 0; | ||
366 | fsm.scroll_press_t = 0; | ||
367 | fsm.samples = 0; | ||
368 | fsm.sum_x = fsm.sum_y = 0; | ||
369 | fsm.orig_x = fsm.orig_y = 0; | ||
370 | fsm.cur_x = fsm.cur_y = 0; | ||
371 | |||
372 | /* Bring up I2C bus */ | ||
373 | i2c_x1000_set_freq(FT6x06_BUS, I2C_FREQ_400K); | ||
374 | |||
375 | /* Reset chip */ | ||
376 | gpio_config(GPIO_B, FT_RST_PIN|FT_INT_PIN, GPIO_OUTPUT(0)); | ||
377 | mdelay(5); | ||
378 | gpio_out_level(GPIO_B, FT_RST_PIN, 1); | ||
379 | gpio_config(GPIO_B, FT_INT_PIN, GPIO_IRQ_EDGE(0)); | ||
380 | gpio_enable_irq(GPIO_B, FT_INT_PIN); | ||
381 | } | ||
382 | |||
383 | void touchpad_set_sensitivity(int level) | ||
384 | { | ||
385 | int pixels = 40; | ||
386 | pixels -= level; | ||
387 | ftd.scroll_thresh_sqr = pixels * pixels; | ||
388 | } | ||
389 | |||
390 | void touchpad_enable_device(bool en) | ||
391 | { | ||
392 | i2c_reg_write1(FT6x06_BUS, FT6x06_ADDR, 0xa5, en ? 0 : 3); | ||
393 | ftd.active = en; | ||
394 | } | ||
395 | |||
396 | /* Value of headphone detect register */ | ||
397 | static uint8_t hp_detect_reg = 0x00; | ||
398 | |||
399 | /* Interval to poll the register */ | ||
400 | #define HPD_POLL_TIME (HZ/2) | ||
401 | |||
402 | static int hp_detect_tmo_cb(struct timeout* tmo) | ||
403 | { | ||
404 | i2c_descriptor* d = (i2c_descriptor*)tmo->data; | ||
405 | i2c_async_queue(AXP173_BUS, TIMEOUT_NOBLOCK, I2C_Q_ADD, 0, d); | ||
406 | return HPD_POLL_TIME; | ||
407 | } | ||
408 | |||
409 | static void hp_detect_init(void) | ||
410 | { | ||
411 | static struct timeout tmo; | ||
412 | static const uint8_t gpio_reg = 0x94; | ||
413 | static i2c_descriptor desc = { | ||
414 | .slave_addr = AXP173_ADDR, | ||
415 | .bus_cond = I2C_START | I2C_STOP, | ||
416 | .tran_mode = I2C_READ, | ||
417 | .buffer[0] = (void*)&gpio_reg, | ||
418 | .count[0] = 1, | ||
419 | .buffer[1] = &hp_detect_reg, | ||
420 | .count[1] = 1, | ||
421 | .callback = NULL, | ||
422 | .arg = 0, | ||
423 | .next = NULL, | ||
424 | }; | ||
425 | |||
426 | /* Headphone detect is wired to an undocumented GPIO on the AXP173. | ||
427 | * This sets it to input mode so we can see the pin state. */ | ||
428 | i2c_reg_write1(AXP173_BUS, AXP173_ADDR, 0x93, 0x01); | ||
429 | |||
430 | /* Get an initial reading before startup */ | ||
431 | int r = i2c_reg_read1(AXP173_BUS, AXP173_ADDR, gpio_reg); | ||
432 | if(r >= 0) | ||
433 | hp_detect_reg = r; | ||
434 | |||
435 | /* Poll the register every second */ | ||
436 | timeout_register(&tmo, &hp_detect_tmo_cb, HPD_POLL_TIME, (intptr_t)&desc); | ||
437 | } | ||
438 | |||
439 | /* Rockbox interface */ | ||
440 | void button_init_device(void) | ||
441 | { | ||
442 | /* Configure physical button GPIOs */ | ||
443 | gpio_config(GPIO_A, (1 << 17) | (1 << 19), GPIO_INPUT); | ||
444 | gpio_config(GPIO_B, (1 << 28) | (1 << 31), GPIO_INPUT); | ||
445 | |||
446 | /* Initialize touchpad */ | ||
447 | ft_init(); | ||
448 | |||
449 | /* Set up headphone detect polling */ | ||
450 | hp_detect_init(); | ||
451 | } | ||
452 | |||
453 | int button_read_device(void) | ||
454 | { | ||
455 | int r = fsm.buttons; | ||
456 | ft_step_state(__ost_read32(), EVENT_NONE, 0, 0); | ||
457 | |||
458 | /* Read GPIOs for physical buttons */ | ||
459 | uint32_t a = REG_GPIO_PIN(GPIO_A); | ||
460 | uint32_t b = REG_GPIO_PIN(GPIO_B); | ||
461 | |||
462 | /* All buttons are active low */ | ||
463 | if((a & (1 << 17)) == 0) r |= BUTTON_PLAY; | ||
464 | if((a & (1 << 19)) == 0) r |= BUTTON_VOL_UP; | ||
465 | if((b & (1 << 28)) == 0) r |= BUTTON_VOL_DOWN; | ||
466 | if((b & (1 << 31)) == 0) r |= BUTTON_POWER; | ||
467 | |||
468 | return r; | ||
469 | } | ||
470 | |||
471 | bool headphones_inserted() | ||
472 | { | ||
473 | return hp_detect_reg & 0x40 ? true : false; | ||
474 | } | ||
475 | |||
476 | #ifndef BOOTLOADER | ||
477 | static int getbtn(void) | ||
478 | { | ||
479 | int btn; | ||
480 | do { | ||
481 | btn = button_get_w_tmo(1); | ||
482 | } while(btn & (BUTTON_REL|BUTTON_REPEAT)); | ||
483 | return btn; | ||
484 | } | ||
485 | |||
486 | bool dbg_fiiom3k_touchpad(void) | ||
487 | { | ||
488 | static const char* fsm_statenames[] = { | ||
489 | "IDLE", "PRESS", "REPORT", "SCROLL_PRESS", "SCROLLING" | ||
490 | }; | ||
491 | |||
492 | do { | ||
493 | int line = 0; | ||
494 | lcd_clear_display(); | ||
495 | lcd_putsf(0, line++, "state: %s", fsm_statenames[fsm.state]); | ||
496 | lcd_putsf(0, line++, "button: %08x", fsm.buttons); | ||
497 | lcd_putsf(0, line++, "pos x: %4d orig x: %4d", fsm.cur_x, fsm.orig_x); | ||
498 | lcd_putsf(0, line++, "pos y: %4d orig y: %4d", fsm.cur_y, fsm.orig_y); | ||
499 | lcd_update(); | ||
500 | } while(getbtn() != BUTTON_POWER); | ||
501 | return false; | ||
502 | } | ||
503 | #endif | ||
diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/button-target.h b/firmware/target/mips/ingenic_x1000/fiiom3k/button-target.h new file mode 100644 index 0000000000..f75a43242d --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/fiiom3k/button-target.h | |||
@@ -0,0 +1,54 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef __BUTTON_TARGET_H__ | ||
23 | #define __BUTTON_TARGET_H__ | ||
24 | |||
25 | #include <stdbool.h> | ||
26 | |||
27 | #define BUTTON_POWER 0x00000001 | ||
28 | #define BUTTON_PLAY 0x00000002 | ||
29 | #define BUTTON_VOL_UP 0x00000004 | ||
30 | #define BUTTON_VOL_DOWN 0x00000008 | ||
31 | #define BUTTON_UP 0x00000010 | ||
32 | #define BUTTON_DOWN 0x00000020 | ||
33 | #define BUTTON_LEFT 0x00000040 | ||
34 | #define BUTTON_RIGHT 0x00000080 | ||
35 | #define BUTTON_SELECT 0x00000100 | ||
36 | #define BUTTON_BACK 0x00000200 | ||
37 | #define BUTTON_MENU 0x00000400 | ||
38 | #define BUTTON_SCROLL_FWD 0x00000800 | ||
39 | #define BUTTON_SCROLL_BACK 0x00001000 | ||
40 | |||
41 | #define BUTTON_MAIN (BUTTON_POWER|BUTTON_VOL_UP|BUTTON_VOL_DOWN|\ | ||
42 | BUTTON_PLAY|BUTTON_TOUCHPAD) | ||
43 | |||
44 | #define BUTTON_TOUCHPAD (BUTTON_UP|BUTTON_DOWN|BUTTON_LEFT|BUTTON_RIGHT|\ | ||
45 | BUTTON_SELECT|BUTTON_BACK|BUTTON_MENU|\ | ||
46 | BUTTON_SCROLL_FWD|BUTTON_SCROLL_BACK) | ||
47 | |||
48 | #define POWEROFF_BUTTON BUTTON_POWER | ||
49 | #define POWEROFF_COUNT 30 | ||
50 | |||
51 | extern void touchpad_set_sensitivity(int level); | ||
52 | extern void touchpad_enable_device(bool en); | ||
53 | |||
54 | #endif /* __BUTTON_TARGET_H__ */ | ||
diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/i2c-target.h b/firmware/target/mips/ingenic_x1000/fiiom3k/i2c-target.h new file mode 100644 index 0000000000..a389d2af42 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/fiiom3k/i2c-target.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef __I2C_TARGET_H__ | ||
23 | #define __I2C_TARGET_H__ | ||
24 | |||
25 | #define I2C_ASYNC_BUS_COUNT 3 | ||
26 | #define I2C_ASYNC_QUEUE_SIZE 4 | ||
27 | |||
28 | #define AK4376_BUS 0 | ||
29 | #define AK4376_ADDR 0x10 | ||
30 | |||
31 | #define FT6x06_BUS 1 | ||
32 | #define FT6x06_ADDR 0x38 | ||
33 | |||
34 | #define AXP173_BUS 2 | ||
35 | #define AXP173_ADDR 0x34 | ||
36 | |||
37 | #endif /* __I2C_TARGET_H__ */ | ||
diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/installer-fiiom3k.c b/firmware/target/mips/ingenic_x1000/fiiom3k/installer-fiiom3k.c new file mode 100644 index 0000000000..c794da4000 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/fiiom3k/installer-fiiom3k.c | |||
@@ -0,0 +1,195 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "installer.h" | ||
23 | #include "nand-x1000.h" | ||
24 | #include "core_alloc.h" | ||
25 | #include "file.h" | ||
26 | |||
27 | #define INSTALL_SUCCESS 0 | ||
28 | #define ERR_FLASH_OPEN_FAILED (-1) | ||
29 | #define ERR_FLASH_ENABLE_WP_FAILED (-2) | ||
30 | #define ERR_FLASH_DISABLE_WP_FAILED (-3) | ||
31 | #define ERR_FLASH_ERASE_FAILED (-4) | ||
32 | #define ERR_FLASH_WRITE_FAILED (-5) | ||
33 | #define ERR_FLASH_READ_FAILED (-6) | ||
34 | #define ERR_OUT_OF_MEMORY (-7) | ||
35 | #define ERR_CANNOT_READ_FILE (-8) | ||
36 | #define ERR_CANNOT_WRITE_FILE (-9) | ||
37 | #define ERR_WRONG_SIZE (-10) | ||
38 | |||
39 | #define BOOT_IMAGE_SIZE (128 * 1024) | ||
40 | |||
41 | static int install_from_buffer(const void* buf) | ||
42 | { | ||
43 | if(nand_open()) | ||
44 | return ERR_FLASH_OPEN_FAILED; | ||
45 | |||
46 | int status = INSTALL_SUCCESS; | ||
47 | |||
48 | if(nand_enable_writes(true)) { | ||
49 | status = ERR_FLASH_DISABLE_WP_FAILED; | ||
50 | goto _exit; | ||
51 | } | ||
52 | |||
53 | if(nand_erase_block(0)) { | ||
54 | status = ERR_FLASH_ERASE_FAILED; | ||
55 | goto _exit; | ||
56 | } | ||
57 | |||
58 | if(nand_write_bytes(0, BOOT_IMAGE_SIZE, buf)) { | ||
59 | status = ERR_FLASH_WRITE_FAILED; | ||
60 | goto _exit; | ||
61 | } | ||
62 | |||
63 | if(nand_enable_writes(false)) { | ||
64 | status = ERR_FLASH_ENABLE_WP_FAILED; | ||
65 | goto _exit; | ||
66 | } | ||
67 | |||
68 | _exit: | ||
69 | nand_close(); | ||
70 | return status; | ||
71 | } | ||
72 | |||
73 | static int dump_to_buffer(void* buf) | ||
74 | { | ||
75 | if(nand_open()) | ||
76 | return ERR_FLASH_OPEN_FAILED; | ||
77 | |||
78 | int status = INSTALL_SUCCESS; | ||
79 | |||
80 | if(nand_read_bytes(0, BOOT_IMAGE_SIZE, buf)) { | ||
81 | status = ERR_FLASH_READ_FAILED; | ||
82 | goto _exit; | ||
83 | } | ||
84 | |||
85 | _exit: | ||
86 | nand_close(); | ||
87 | return status; | ||
88 | } | ||
89 | |||
90 | int install_bootloader(const char* path) | ||
91 | { | ||
92 | /* Allocate memory to hold image */ | ||
93 | int handle = core_alloc("boot_image", BOOT_IMAGE_SIZE); | ||
94 | if(handle < 0) | ||
95 | return ERR_OUT_OF_MEMORY; | ||
96 | |||
97 | int status = INSTALL_SUCCESS; | ||
98 | void* buffer = core_get_data(handle); | ||
99 | |||
100 | /* Open the boot image */ | ||
101 | int fd = open(path, O_RDONLY); | ||
102 | if(fd < 0) { | ||
103 | status = ERR_CANNOT_READ_FILE; | ||
104 | goto _exit; | ||
105 | } | ||
106 | |||
107 | /* Check file size */ | ||
108 | off_t fsize = filesize(fd); | ||
109 | if(fsize != BOOT_IMAGE_SIZE) { | ||
110 | status = ERR_WRONG_SIZE; | ||
111 | goto _exit; | ||
112 | } | ||
113 | |||
114 | /* Read the file into the buffer */ | ||
115 | ssize_t cnt = read(fd, buffer, BOOT_IMAGE_SIZE); | ||
116 | if(cnt != BOOT_IMAGE_SIZE) { | ||
117 | status = ERR_CANNOT_READ_FILE; | ||
118 | goto _exit; | ||
119 | } | ||
120 | |||
121 | /* Perform the installation */ | ||
122 | status = install_from_buffer(buffer); | ||
123 | |||
124 | _exit: | ||
125 | if(fd >= 0) | ||
126 | close(fd); | ||
127 | core_free(handle); | ||
128 | return status; | ||
129 | } | ||
130 | |||
131 | /* Dump the current bootloader to a file */ | ||
132 | int dump_bootloader(const char* path) | ||
133 | { | ||
134 | /* Allocate memory to hold image */ | ||
135 | int handle = core_alloc("boot_image", BOOT_IMAGE_SIZE); | ||
136 | if(handle < 0) | ||
137 | return -1; | ||
138 | |||
139 | /* Read data from flash */ | ||
140 | int fd = -1; | ||
141 | void* buffer = core_get_data(handle); | ||
142 | int status = dump_to_buffer(buffer); | ||
143 | if(status) | ||
144 | goto _exit; | ||
145 | |||
146 | /* Open file */ | ||
147 | fd = open(path, O_CREAT|O_TRUNC|O_WRONLY); | ||
148 | if(fd < 0) { | ||
149 | status = ERR_CANNOT_WRITE_FILE; | ||
150 | goto _exit; | ||
151 | } | ||
152 | |||
153 | /* Write data to file */ | ||
154 | ssize_t cnt = write(fd, buffer, BOOT_IMAGE_SIZE); | ||
155 | if(cnt != BOOT_IMAGE_SIZE) { | ||
156 | status = ERR_CANNOT_WRITE_FILE; | ||
157 | goto _exit; | ||
158 | } | ||
159 | |||
160 | _exit: | ||
161 | if(fd >= 0) | ||
162 | close(fd); | ||
163 | core_free(handle); | ||
164 | return status; | ||
165 | } | ||
166 | |||
167 | const char* installer_strerror(int rc) | ||
168 | { | ||
169 | switch(rc) { | ||
170 | case INSTALL_SUCCESS: | ||
171 | return "Success"; | ||
172 | case ERR_FLASH_OPEN_FAILED: | ||
173 | return "Can't open flash device"; | ||
174 | case ERR_FLASH_ENABLE_WP_FAILED: | ||
175 | return "Couldn't re-enable write protect"; | ||
176 | case ERR_FLASH_DISABLE_WP_FAILED: | ||
177 | return "Can't disable write protect"; | ||
178 | case ERR_FLASH_ERASE_FAILED: | ||
179 | return "Flash erase failed"; | ||
180 | case ERR_FLASH_WRITE_FAILED: | ||
181 | return "Flash write error"; | ||
182 | case ERR_FLASH_READ_FAILED: | ||
183 | return "Flash read error"; | ||
184 | case ERR_OUT_OF_MEMORY: | ||
185 | return "Out of memory"; | ||
186 | case ERR_CANNOT_READ_FILE: | ||
187 | return "Error reading file"; | ||
188 | case ERR_CANNOT_WRITE_FILE: | ||
189 | return "Error writing file"; | ||
190 | case ERR_WRONG_SIZE: | ||
191 | return "Wrong file size"; | ||
192 | default: | ||
193 | return "Unknown error"; | ||
194 | } | ||
195 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/lcd-fiiom3k.c b/firmware/target/mips/ingenic_x1000/fiiom3k/lcd-fiiom3k.c new file mode 100644 index 0000000000..96f794d7df --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/fiiom3k/lcd-fiiom3k.c | |||
@@ -0,0 +1,192 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "lcd.h" | ||
23 | #include "kernel.h" | ||
24 | #include "lcd-x1000.h" | ||
25 | #include "gpio-x1000.h" | ||
26 | #include "system.h" | ||
27 | |||
28 | #define CS_PIN (1 << 18) | ||
29 | #define RD_PIN (1 << 16) | ||
30 | |||
31 | static const uint32_t fiio_lcd_cmd_enable[] = { | ||
32 | /* Software reset */ | ||
33 | LCD_INSTR_CMD, 0x01, | ||
34 | LCD_INSTR_UDELAY, 120000, | ||
35 | /* Sleep out */ | ||
36 | LCD_INSTR_CMD, 0x11, | ||
37 | LCD_INSTR_UDELAY, 5000, | ||
38 | /* Memory access order */ | ||
39 | LCD_INSTR_CMD, 0x36, | ||
40 | LCD_INSTR_DAT, 0x00, | ||
41 | /* Row and column address set */ | ||
42 | LCD_INSTR_CMD, 0x2a, | ||
43 | LCD_INSTR_DAT, 0x00, | ||
44 | LCD_INSTR_DAT, 0x00, | ||
45 | LCD_INSTR_DAT, (LCD_WIDTH >> 8) & 0xff, | ||
46 | LCD_INSTR_DAT, (LCD_WIDTH & 0xff), | ||
47 | LCD_INSTR_CMD, 0x2b, | ||
48 | LCD_INSTR_DAT, 0x00, | ||
49 | LCD_INSTR_DAT, 0x00, | ||
50 | LCD_INSTR_DAT, (LCD_HEIGHT >> 8) & 0xff, | ||
51 | LCD_INSTR_DAT, (LCD_HEIGHT & 0xff), | ||
52 | /* Interface pixel format */ | ||
53 | LCD_INSTR_CMD, 0x3a, | ||
54 | LCD_INSTR_DAT, 0x05, | ||
55 | /* Enable display inversion */ | ||
56 | LCD_INSTR_CMD, 0x21, | ||
57 | /* Porch setting */ | ||
58 | LCD_INSTR_CMD, 0xb2, | ||
59 | LCD_INSTR_DAT, 0x0c, | ||
60 | LCD_INSTR_DAT, 0x0c, | ||
61 | LCD_INSTR_DAT, 0x00, | ||
62 | LCD_INSTR_DAT, 0x33, | ||
63 | LCD_INSTR_DAT, 0x33, | ||
64 | /* Gate control */ | ||
65 | LCD_INSTR_CMD, 0xb7, | ||
66 | LCD_INSTR_DAT, 0x35, | ||
67 | /* VCOM setting */ | ||
68 | LCD_INSTR_CMD, 0xbb, | ||
69 | LCD_INSTR_DAT, 0x1f, | ||
70 | /* Backlight control 5 */ | ||
71 | LCD_INSTR_CMD, 0xbc, | ||
72 | LCD_INSTR_DAT, 0xec, | ||
73 | /* Backlight control 6 */ | ||
74 | LCD_INSTR_CMD, 0xbd, | ||
75 | LCD_INSTR_DAT, 0xfe, | ||
76 | /* Voltage settings */ | ||
77 | LCD_INSTR_CMD, 0xc2, | ||
78 | LCD_INSTR_DAT, 0x01, | ||
79 | LCD_INSTR_CMD, 0xc3, | ||
80 | LCD_INSTR_DAT, 0x19, | ||
81 | LCD_INSTR_CMD, 0xc4, | ||
82 | LCD_INSTR_DAT, 0x20, | ||
83 | /* Frame rate control */ | ||
84 | LCD_INSTR_CMD, 0xc6, | ||
85 | LCD_INSTR_DAT, 0x0f, /* = 60 fps */ | ||
86 | /* Power control 1 */ | ||
87 | LCD_INSTR_CMD, 0xd0, | ||
88 | LCD_INSTR_DAT, 0xa4, | ||
89 | LCD_INSTR_DAT, 0xa1, | ||
90 | /* d6 Unknown */ | ||
91 | LCD_INSTR_CMD, 0xd6, | ||
92 | LCD_INSTR_DAT, 0xa1, | ||
93 | /* Positive gamma correction */ | ||
94 | LCD_INSTR_CMD, 0xe0, | ||
95 | LCD_INSTR_DAT, 0xd0, | ||
96 | LCD_INSTR_DAT, 0x06, | ||
97 | LCD_INSTR_DAT, 0x0c, | ||
98 | LCD_INSTR_DAT, 0x0a, | ||
99 | LCD_INSTR_DAT, 0x09, | ||
100 | LCD_INSTR_DAT, 0x0a, | ||
101 | LCD_INSTR_DAT, 0x32, | ||
102 | LCD_INSTR_DAT, 0x33, | ||
103 | LCD_INSTR_DAT, 0x49, | ||
104 | LCD_INSTR_DAT, 0x19, | ||
105 | LCD_INSTR_DAT, 0x14, | ||
106 | LCD_INSTR_DAT, 0x15, | ||
107 | LCD_INSTR_DAT, 0x2b, | ||
108 | LCD_INSTR_DAT, 0x34, | ||
109 | /* Negative gamma correction */ | ||
110 | LCD_INSTR_CMD, 0xe1, | ||
111 | LCD_INSTR_DAT, 0xd0, | ||
112 | LCD_INSTR_DAT, 0x06, | ||
113 | LCD_INSTR_DAT, 0x0c, | ||
114 | LCD_INSTR_DAT, 0x0a, | ||
115 | LCD_INSTR_DAT, 0x09, | ||
116 | LCD_INSTR_DAT, 0x11, | ||
117 | LCD_INSTR_DAT, 0x37, | ||
118 | LCD_INSTR_DAT, 0x33, | ||
119 | LCD_INSTR_DAT, 0x49, | ||
120 | LCD_INSTR_DAT, 0x19, | ||
121 | LCD_INSTR_DAT, 0x14, | ||
122 | LCD_INSTR_DAT, 0x15, | ||
123 | LCD_INSTR_DAT, 0x2d, | ||
124 | LCD_INSTR_DAT, 0x34, | ||
125 | /* Tearing effect line ON, mode=0 (vsync signal) */ | ||
126 | LCD_INSTR_CMD, 0x35, | ||
127 | LCD_INSTR_DAT, 0x00, | ||
128 | /* Display ON */ | ||
129 | LCD_INSTR_CMD, 0x29, | ||
130 | LCD_INSTR_END, | ||
131 | }; | ||
132 | |||
133 | static const uint32_t fiio_lcd_cmd_sleep[] = { | ||
134 | /* Display OFF */ | ||
135 | LCD_INSTR_CMD, 0x28, | ||
136 | /* Sleep IN */ | ||
137 | LCD_INSTR_CMD, 0x10, | ||
138 | LCD_INSTR_UDELAY, 5000, | ||
139 | LCD_INSTR_END, | ||
140 | }; | ||
141 | |||
142 | static const uint32_t fiio_lcd_cmd_wake[] = { | ||
143 | /* Sleep OUT */ | ||
144 | LCD_INSTR_CMD, 0x11, | ||
145 | LCD_INSTR_UDELAY, 5000, | ||
146 | /* Display ON */ | ||
147 | LCD_INSTR_CMD, 0x29, | ||
148 | LCD_INSTR_END, | ||
149 | }; | ||
150 | |||
151 | static const uint8_t __attribute__((aligned(64))) | ||
152 | fiio_lcd_dma_wr_cmd[] = {0x00, 0x00, 0x00, 0x2c}; | ||
153 | |||
154 | const struct lcd_tgt_config lcd_tgt_config = { | ||
155 | .bus_width = 16, | ||
156 | .cmd_width = 8, | ||
157 | .use_6800_mode = 0, | ||
158 | .use_serial = 0, | ||
159 | .clk_polarity = 0, | ||
160 | .dc_polarity = 0, | ||
161 | .wr_polarity = 1, | ||
162 | .te_enable = 1, | ||
163 | .te_polarity = 1, | ||
164 | .te_narrow = 0, | ||
165 | .dma_wr_cmd_buf = &fiio_lcd_dma_wr_cmd, | ||
166 | .dma_wr_cmd_size = sizeof(fiio_lcd_dma_wr_cmd), | ||
167 | }; | ||
168 | |||
169 | void lcd_tgt_enable(bool enable) | ||
170 | { | ||
171 | if(enable) { | ||
172 | gpio_config(GPIO_A, 0xffff, GPIO_DEVICE(1)); | ||
173 | gpio_config(GPIO_B, 0x1f << 16, GPIO_DEVICE(1)); | ||
174 | gpio_config(GPIO_B, CS_PIN|RD_PIN, GPIO_OUTPUT(1)); | ||
175 | mdelay(5); | ||
176 | gpio_out_level(GPIO_B, CS_PIN, 0); | ||
177 | lcd_set_clock(X1000_CLK_SCLK_A, 30000000); | ||
178 | lcd_exec_commands(&fiio_lcd_cmd_enable[0]); | ||
179 | } else { | ||
180 | lcd_exec_commands(&fiio_lcd_cmd_sleep[0]); | ||
181 | mdelay(115); /* ensure we wait a total of 120ms before power off */ | ||
182 | gpio_config(GPIO_B, CS_PIN|RD_PIN, 0); | ||
183 | } | ||
184 | } | ||
185 | |||
186 | void lcd_tgt_sleep(bool sleep) | ||
187 | { | ||
188 | if(sleep) | ||
189 | lcd_exec_commands(&fiio_lcd_cmd_sleep[0]); | ||
190 | else | ||
191 | lcd_exec_commands(&fiio_lcd_cmd_wake[0]); | ||
192 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/nand-fiiom3k.c b/firmware/target/mips/ingenic_x1000/fiiom3k/nand-fiiom3k.c new file mode 100644 index 0000000000..7c8a306bae --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/fiiom3k/nand-fiiom3k.c | |||
@@ -0,0 +1,53 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "nand-x1000.h" | ||
23 | #include "nand-target.h" | ||
24 | #include "sfc-x1000.h" | ||
25 | |||
26 | /* Unbelievably FiiO has completely disabled the use of ECC for this chip | ||
27 | * in their Linux kernel, even though it has perfectly good spare areas. | ||
28 | * There's no internal ECC either. | ||
29 | * | ||
30 | * Using nanddump to read the spare areas reveals they're filled with 0xff, | ||
31 | * and the publicly released Linux source has the ecc_strength set to 0. | ||
32 | */ | ||
33 | static const nand_chip_data ato25d1ga = { | ||
34 | .name = "ATO25D1GA", | ||
35 | .mf_id = 0x9b, | ||
36 | .dev_id = 0x12, | ||
37 | .dev_conf = NAND_INIT_SFC_DEV_CONF, | ||
38 | /* XXX: datasheet says 104 MHz but FiiO seems to run this at 150 MHz. | ||
39 | * Didn't find any issues doing this so might as well keep the behavior. | ||
40 | */ | ||
41 | .clock_freq = NAND_INIT_CLOCK_SPEED, | ||
42 | .block_size = 64, | ||
43 | .page_size = 2048, | ||
44 | .spare_size = 64, | ||
45 | .rowaddr_width = 3, | ||
46 | .coladdr_width = 2, | ||
47 | .flags = NANDCHIP_FLAG_QUAD, | ||
48 | }; | ||
49 | |||
50 | const nand_chip_desc target_nand_chip_descs[] = { | ||
51 | {&ato25d1ga, &nand_chip_ops_std}, | ||
52 | {NULL, NULL}, | ||
53 | }; | ||
diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/nand-target.h b/firmware/target/mips/ingenic_x1000/fiiom3k/nand-target.h new file mode 100644 index 0000000000..26a8b840c9 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/fiiom3k/nand-target.h | |||
@@ -0,0 +1,42 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef __NAND_TARGET_H__ | ||
23 | #define __NAND_TARGET_H__ | ||
24 | |||
25 | /* The max page size (main + spare) of all NAND chips used by this target */ | ||
26 | #define NAND_MAX_PAGE_SIZE (2048 + 64) | ||
27 | |||
28 | /* The clock source to use for the SFC controller. Note the SPL has special | ||
29 | * handling which ignores this choice, so it only applies to bootloader & app. | ||
30 | */ | ||
31 | #define NAND_CLOCK_SOURCE X1000_CLK_SCLK_A | ||
32 | |||
33 | /* The clock speed to use for the SFC controller during chip identification */ | ||
34 | #define NAND_INIT_CLOCK_SPEED 150000000 | ||
35 | |||
36 | /* Initial value to program SFC_DEV_CONF register with */ | ||
37 | #define NAND_INIT_SFC_DEV_CONF \ | ||
38 | jz_orf(SFC_DEV_CONF, CE_DL(1), HOLD_DL(1), WP_DL(1), \ | ||
39 | CPHA(0), CPOL(0), TSH(7), TSETUP(0), THOLD(0), \ | ||
40 | STA_TYPE_V(1BYTE), CMD_TYPE_V(8BITS), SMP_DELAY(1)) | ||
41 | |||
42 | #endif /* __NAND_TARGET_H__ */ | ||
diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/power-fiiom3k.c b/firmware/target/mips/ingenic_x1000/fiiom3k/power-fiiom3k.c new file mode 100644 index 0000000000..3eb3146d97 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/fiiom3k/power-fiiom3k.c | |||
@@ -0,0 +1,97 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "power.h" | ||
23 | #include "adc.h" | ||
24 | #include "system.h" | ||
25 | #include "kernel.h" | ||
26 | #include "axp173.h" | ||
27 | #include "i2c-x1000.h" | ||
28 | #include "gpio-x1000.h" | ||
29 | |||
30 | const unsigned short battery_level_dangerous[BATTERY_TYPES_COUNT] = | ||
31 | { | ||
32 | 3470 | ||
33 | }; | ||
34 | |||
35 | /* the OF shuts down at this voltage */ | ||
36 | const unsigned short battery_level_shutoff[BATTERY_TYPES_COUNT] = | ||
37 | { | ||
38 | 3400 | ||
39 | }; | ||
40 | |||
41 | /* voltages (millivolt) of 0%, 10%, ... 100% when charging disabled */ | ||
42 | const unsigned short percent_to_volt_discharge[BATTERY_TYPES_COUNT][11] = | ||
43 | { | ||
44 | { 3400, 3639, 3697, 3723, 3757, 3786, 3836, 3906, 3980, 4050, 4159 } | ||
45 | }; | ||
46 | |||
47 | /* voltages (millivolt) of 0%, 10%, ... 100% when charging enabled */ | ||
48 | const unsigned short const percent_to_volt_charge[11] = | ||
49 | { | ||
50 | 3485, 3780, 3836, 3857, 3890, 3930, 3986, 4062, 4158, 4185, 4196 | ||
51 | }; | ||
52 | |||
53 | #define AXP173_IRQ_PORT GPIO_B | ||
54 | #define AXP173_IRQ_PIN (1 << 10) | ||
55 | |||
56 | void power_init(void) | ||
57 | { | ||
58 | /* Initialize driver */ | ||
59 | i2c_x1000_set_freq(2, I2C_FREQ_400K); | ||
60 | axp173_init(); | ||
61 | |||
62 | /* Set lowest sample rate */ | ||
63 | axp173_adc_set_rate(AXP173_ADC_RATE_25HZ); | ||
64 | |||
65 | /* Ensure battery voltage ADC is enabled */ | ||
66 | int bits = axp173_adc_get_enabled(); | ||
67 | bits |= (1 << ADC_BATTERY_VOLTAGE); | ||
68 | axp173_adc_set_enabled(bits); | ||
69 | |||
70 | /* Turn on all power outputs */ | ||
71 | i2c_reg_modify1(AXP173_BUS, AXP173_ADDR, 0x12, 0, 0x5f, NULL); | ||
72 | i2c_reg_modify1(AXP173_BUS, AXP173_ADDR, 0x80, 0, 0xc0, NULL); | ||
73 | |||
74 | /* Short delay to give power outputs time to stabilize */ | ||
75 | mdelay(5); | ||
76 | } | ||
77 | |||
78 | void adc_init(void) | ||
79 | { | ||
80 | } | ||
81 | |||
82 | void power_off(void) | ||
83 | { | ||
84 | /* Set the shutdown bit */ | ||
85 | i2c_reg_setbit1(AXP173_BUS, AXP173_ADDR, 0x32, 7, 1, NULL); | ||
86 | while(1); | ||
87 | } | ||
88 | |||
89 | bool charging_state(void) | ||
90 | { | ||
91 | return axp173_battery_status() == AXP173_BATT_CHARGING; | ||
92 | } | ||
93 | |||
94 | int _battery_voltage(void) | ||
95 | { | ||
96 | return axp173_adc_read(ADC_BATTERY_VOLTAGE); | ||
97 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/powermgmt-target.h b/firmware/target/mips/ingenic_x1000/fiiom3k/powermgmt-target.h new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/fiiom3k/powermgmt-target.h | |||
diff --git a/firmware/target/mips/ingenic_x1000/gpio-x1000.c b/firmware/target/mips/ingenic_x1000/gpio-x1000.c new file mode 100644 index 0000000000..a47865e397 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/gpio-x1000.c | |||
@@ -0,0 +1,84 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "gpio-x1000.h" | ||
23 | #include "kernel.h" | ||
24 | |||
25 | #ifndef BOOTLOADER_SPL | ||
26 | struct mutex gpio_z_mutex; | ||
27 | #endif | ||
28 | |||
29 | void gpio_init(void) | ||
30 | { | ||
31 | #ifndef BOOTLOADER_SPL | ||
32 | mutex_init(&gpio_z_mutex); | ||
33 | #endif | ||
34 | |||
35 | /* Set all pins to input state */ | ||
36 | for(int i = 0; i < 4; ++i) { | ||
37 | jz_clr(GPIO_INT(GPIO_Z), 0xffffffff); | ||
38 | jz_set(GPIO_MSK(GPIO_Z), 0xffffffff); | ||
39 | jz_set(GPIO_PAT1(GPIO_Z), 0xffffffff); | ||
40 | jz_clr(GPIO_PAT0(GPIO_Z), 0xffffffff); | ||
41 | REG_GPIO_Z_GID2LD = i; | ||
42 | } | ||
43 | |||
44 | /* Clear flag and disable pull resistor */ | ||
45 | for(int i = 0; i < 4; ++i) { | ||
46 | jz_clr(GPIO_FLAG(i), 0xffffffff); | ||
47 | jz_set(GPIO_PULL(i), 0xffffffff); | ||
48 | } | ||
49 | } | ||
50 | |||
51 | void gpio_lock(void) | ||
52 | { | ||
53 | #ifndef BOOTLOADER_SPL | ||
54 | mutex_lock(&gpio_z_mutex); | ||
55 | #endif | ||
56 | } | ||
57 | |||
58 | void gpio_unlock(void) | ||
59 | { | ||
60 | #ifndef BOOTLOADER_SPL | ||
61 | mutex_unlock(&gpio_z_mutex); | ||
62 | #endif | ||
63 | } | ||
64 | |||
65 | void gpio_config(int port, unsigned pinmask, int func) | ||
66 | { | ||
67 | unsigned intr = REG_GPIO_INT(port); | ||
68 | unsigned mask = REG_GPIO_MSK(port); | ||
69 | unsigned pat1 = REG_GPIO_PAT1(port); | ||
70 | unsigned pat0 = REG_GPIO_PAT0(port); | ||
71 | |||
72 | gpio_lock(); | ||
73 | if(func & 8) jz_set(GPIO_INT(GPIO_Z), (intr & pinmask) ^ pinmask); | ||
74 | else jz_clr(GPIO_INT(GPIO_Z), (~intr & pinmask) ^ pinmask); | ||
75 | if(func & 4) jz_set(GPIO_MSK(GPIO_Z), (mask & pinmask) ^ pinmask); | ||
76 | else jz_clr(GPIO_MSK(GPIO_Z), (~mask & pinmask) ^ pinmask); | ||
77 | if(func & 2) jz_set(GPIO_PAT1(GPIO_Z), (pat1 & pinmask) ^ pinmask); | ||
78 | else jz_clr(GPIO_PAT1(GPIO_Z), (~pat1 & pinmask) ^ pinmask); | ||
79 | if(func & 1) jz_set(GPIO_PAT0(GPIO_Z), (pat0 & pinmask) ^ pinmask); | ||
80 | else jz_clr(GPIO_PAT0(GPIO_Z), (~pat0 & pinmask) ^ pinmask); | ||
81 | REG_GPIO_Z_GID2LD = port; | ||
82 | gpio_unlock(); | ||
83 | gpio_set_pull(port, pinmask, func & 16); | ||
84 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/gpio-x1000.h b/firmware/target/mips/ingenic_x1000/gpio-x1000.h new file mode 100644 index 0000000000..f1a65b37b5 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/gpio-x1000.h | |||
@@ -0,0 +1,110 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef __GPIO_X1000_H__ | ||
23 | #define __GPIO_X1000_H__ | ||
24 | |||
25 | /* GPIO API | ||
26 | * -------- | ||
27 | * | ||
28 | * To assign a new function to a GPIO, call gpio_config(). This uses the | ||
29 | * hardware's GPIO Z facility to atomically most GPIO registers at once, | ||
30 | * so it can be used to make any state transition safely. Since GPIO Z is | ||
31 | * protected by a mutex, you can't call gpio_config() from interrupt context. | ||
32 | * | ||
33 | * If you need to use GPIO Z directly, then use gpio_lock() and gpio_unlock() | ||
34 | * to acquire the mutex. | ||
35 | * | ||
36 | * Depending on the current GPIO state, certain state transitions are safe to | ||
37 | * perform without locking, as they only change one register: | ||
38 | * | ||
39 | * - for pins in GPIO_OUTPUT state: | ||
40 | * - use gpio_out_level() to change the output level | ||
41 | * | ||
42 | * - for pins in GPIO_IRQ_LEVEL or GPIO_IRQ_EDGE state: | ||
43 | * - use gpio_irq_level() to change the trigger level | ||
44 | * - use gpio_irq_mask() to mask/unmask the IRQ | ||
45 | * | ||
46 | * - for pins in GPIO_DEVICE or GPIO_INPUT state: | ||
47 | * - no special transitions allowed | ||
48 | * | ||
49 | * - in all states: | ||
50 | * - use gpio_set_pull() to change the pull-up/pull-down state | ||
51 | */ | ||
52 | |||
53 | #include "x1000/gpio.h" | ||
54 | |||
55 | /* GPIO port numbers */ | ||
56 | #define GPIO_A 0 | ||
57 | #define GPIO_B 1 | ||
58 | #define GPIO_C 2 | ||
59 | #define GPIO_D 3 | ||
60 | #define GPIO_Z 7 | ||
61 | |||
62 | /* GPIO function bits */ | ||
63 | #define GPIO_F_PULL 16 | ||
64 | #define GPIO_F_INT 8 | ||
65 | #define GPIO_F_MASK 4 | ||
66 | #define GPIO_F_PAT1 2 | ||
67 | #define GPIO_F_PAT0 1 | ||
68 | |||
69 | /* GPIO function numbers */ | ||
70 | #define GPIO_DEVICE(i) ((i)&3) | ||
71 | #define GPIO_OUTPUT(i) (0x4|((i)&1)) | ||
72 | #define GPIO_INPUT 0x16 | ||
73 | #define GPIO_IRQ_LEVEL(i) (0x1c|((i)&1)) | ||
74 | #define GPIO_IRQ_EDGE(i) (0x1e|((i)&1)) | ||
75 | |||
76 | extern void gpio_init(void); | ||
77 | extern void gpio_lock(void); | ||
78 | extern void gpio_unlock(void); | ||
79 | extern void gpio_config(int port, unsigned pinmask, int func); | ||
80 | |||
81 | static inline void gpio_out_level(int port, unsigned pinmask, int level) | ||
82 | { | ||
83 | if(level) | ||
84 | jz_set(GPIO_PAT0(port), pinmask); | ||
85 | else | ||
86 | jz_clr(GPIO_PAT0(port), pinmask); | ||
87 | } | ||
88 | |||
89 | #define gpio_irq_level gpio_out_level | ||
90 | |||
91 | static inline void gpio_irq_mask(int port, unsigned pinmask, int masked) | ||
92 | { | ||
93 | if(masked) | ||
94 | jz_set(GPIO_MSK(port), pinmask); | ||
95 | else | ||
96 | jz_clr(GPIO_MSK(port), pinmask); | ||
97 | } | ||
98 | |||
99 | #define gpio_enable_irq(port, pinmask) gpio_irq_mask((port), (pinmask), 0) | ||
100 | #define gpio_disable_irq(port, pinmask) gpio_irq_mask((port), (pinmask), 1) | ||
101 | |||
102 | static inline void gpio_set_pull(int port, unsigned pinmask, int state) | ||
103 | { | ||
104 | if(state) | ||
105 | jz_set(GPIO_PULL(port), pinmask); | ||
106 | else | ||
107 | jz_clr(GPIO_PULL(port), pinmask); | ||
108 | } | ||
109 | |||
110 | #endif /* __GPIO_X1000_H__ */ | ||
diff --git a/firmware/target/mips/ingenic_x1000/i2c-x1000.c b/firmware/target/mips/ingenic_x1000/i2c-x1000.c new file mode 100644 index 0000000000..8bf606227b --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/i2c-x1000.c | |||
@@ -0,0 +1,478 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | /* #define LOGF_ENABLE */ | ||
23 | #include "i2c-x1000.h" | ||
24 | #include "system.h" | ||
25 | #include "kernel.h" | ||
26 | #include "panic.h" | ||
27 | #include "logf.h" | ||
28 | #include "gpio-x1000.h" | ||
29 | #include "clk-x1000.h" | ||
30 | #include "irq-x1000.h" | ||
31 | #include "x1000/i2c.h" | ||
32 | #include "x1000/cpm.h" | ||
33 | |||
34 | #if I2C_ASYNC_BUS_COUNT != 3 | ||
35 | # error "Wrong I2C_ASYNC_BUS_COUNT (should be 3)" | ||
36 | #endif | ||
37 | |||
38 | #define FIFO_SIZE 64 /* Size of data FIFOs */ | ||
39 | #define FIFO_TX_THRESH 16 /* Wake up when TX FIFO gets to this level */ | ||
40 | #define FIFO_RX_SLACK 2 /* Slack space to leave, avoids RX FIFO overflow */ | ||
41 | |||
42 | typedef struct i2c_x1000_bus { | ||
43 | /* Hardware channel, this is just equal to i2c-async bus number. */ | ||
44 | int chn; | ||
45 | |||
46 | /* Buffer/count usage depends on what phase the bus is processing: | ||
47 | * | ||
48 | * - Phase1: writing out descriptor's buffer[0] for both READs and WRITEs. | ||
49 | * - Phase2: writing out descriptor's buffer[1] for WRITEs, or issuing a | ||
50 | * series of read requests for READs. | ||
51 | * | ||
52 | * In phase1, buffer[1] and count[1] are equal to the descriptor's copy. | ||
53 | * buffer[0] and count[0] get incremented/decremented as we send bytes. | ||
54 | * Phase1 is only visited if we actually need to send bytes; if there | ||
55 | * would be no data in this phase then __i2c_async_submit() sets up the | ||
56 | * driver to go directly to phase2. | ||
57 | * | ||
58 | * Phase2 begins after phase1 writes out its last byte, or if phase1 was | ||
59 | * skipped at submit time. For WRITEs phase2 is identical to phase1 so we | ||
60 | * copy over buffer[1] and count[1] to buffer[0] and count[0], and zero | ||
61 | * out buffer[1] and count[1]. | ||
62 | * | ||
63 | * For READs phase2 sets buffer[0] to NULL and count[0] equal to count[1]. | ||
64 | * Now count[0] counts the number of bytes left to request, and count[1] | ||
65 | * counts the number of bytes left to receive. i2c_x1000_fifo_write() sees | ||
66 | * that buffer[0] is NULL and sends read requests instead of data bytes. | ||
67 | * buffer[1] is advanced by i2c_x1000_fifo_read() we receive bytes. | ||
68 | */ | ||
69 | unsigned char* buffer[2]; | ||
70 | int count[2]; | ||
71 | bool phase1; | ||
72 | |||
73 | /* Copied fields from descriptor */ | ||
74 | uint8_t bus_cond; | ||
75 | uint8_t tran_mode; | ||
76 | |||
77 | /* Counter to keep track of when to send end conditions */ | ||
78 | int byte_cnt; | ||
79 | int byte_cnt_end; | ||
80 | |||
81 | /* Current bus frequency, used to calculate timeout durations */ | ||
82 | long freq; | ||
83 | |||
84 | /* Timeout to reset the bus in case of buggy devices */ | ||
85 | struct timeout tmo; | ||
86 | |||
87 | /* Flag used to indicate a reset is processing */ | ||
88 | int resetting; | ||
89 | } i2c_x1000_bus; | ||
90 | |||
91 | static i2c_x1000_bus i2c_x1000_busses[3]; | ||
92 | |||
93 | static void i2c_x1000_fifo_write(i2c_x1000_bus* bus) | ||
94 | { | ||
95 | int tx_free, tx_n; | ||
96 | |||
97 | /* Get free space in FIFO */ | ||
98 | tx_free = FIFO_SIZE - REG_I2C_TXFLR(bus->chn); | ||
99 | |||
100 | _again: | ||
101 | /* Leave some slack space when reading. If we submit a full FIFO's worth | ||
102 | * of read requests, there's a small chance that a byte "on the wire" is | ||
103 | * unaccounted for and causes an RX FIFO overrun. Slack space is meant to | ||
104 | * avoid this situation. | ||
105 | */ | ||
106 | if(bus->tran_mode == I2C_READ) { | ||
107 | tx_free -= FIFO_RX_SLACK; | ||
108 | if(tx_free <= 0) | ||
109 | goto _end; | ||
110 | } | ||
111 | |||
112 | /* Calculate number of bytes needed to send/request */ | ||
113 | tx_n = MIN(tx_free, bus->count[0]); | ||
114 | |||
115 | /* Account for bytes we're about to send/request */ | ||
116 | bus->count[0] -= tx_n; | ||
117 | tx_free -= tx_n; | ||
118 | |||
119 | for(; tx_n > 0; --tx_n) { | ||
120 | bus->byte_cnt += 1; | ||
121 | |||
122 | /* Read data byte or set read request bit */ | ||
123 | uint32_t dc = bus->buffer[0] ? *bus->buffer[0]++ : jz_orm(I2C_DC, CMD); | ||
124 | |||
125 | /* Check for first byte & apply RESTART. | ||
126 | * Note the HW handles RESTART automatically when changing the | ||
127 | * direction of the transfer, so we don't need to check for that. | ||
128 | */ | ||
129 | if(bus->byte_cnt == 1 && (bus->bus_cond & I2C_RESTART)) | ||
130 | dc |= jz_orm(I2C_DC, RESTART); | ||
131 | |||
132 | /* Check for last byte & apply STOP */ | ||
133 | if(bus->byte_cnt == bus->byte_cnt_end && (bus->bus_cond & I2C_STOP)) | ||
134 | dc |= jz_orm(I2C_DC, STOP); | ||
135 | |||
136 | /* Add entry to FIFO */ | ||
137 | REG_I2C_DC(bus->chn) = dc; | ||
138 | } | ||
139 | |||
140 | /* FIFO full and current phase still has data to send. | ||
141 | * Configure interrupt to fire when there's a good amount of free space. | ||
142 | */ | ||
143 | if(bus->count[0] > 0) { | ||
144 | _end: | ||
145 | REG_I2C_TXTL(bus->chn) = FIFO_TX_THRESH; | ||
146 | jz_writef(I2C_INTMSK(bus->chn), TXEMP(1), RXFL(0)); | ||
147 | return; | ||
148 | } | ||
149 | |||
150 | /* Advance to second phase if needed */ | ||
151 | if(bus->phase1 && bus->count[1] > 0) { | ||
152 | bus->buffer[0] = bus->tran_mode == I2C_WRITE ? bus->buffer[1] : NULL; | ||
153 | bus->count[0] = bus->count[1]; | ||
154 | bus->phase1 = false; | ||
155 | |||
156 | /* Submit further data if possible; else wait for TX space */ | ||
157 | if(tx_free > 0) | ||
158 | goto _again; | ||
159 | else | ||
160 | goto _end; | ||
161 | } | ||
162 | |||
163 | /* All phases are done. Now we just need to wake up when the whole | ||
164 | * operation is complete, either by waiting for TX to drain or RX to | ||
165 | * fill to the appropriate level. */ | ||
166 | if(bus->tran_mode == I2C_WRITE) { | ||
167 | REG_I2C_TXTL(bus->chn) = 0; | ||
168 | jz_writef(I2C_INTMSK(bus->chn), TXEMP(1), RXFL(0)); | ||
169 | } else { | ||
170 | REG_I2C_RXTL(bus->chn) = bus->count[1] - 1; | ||
171 | jz_writef(I2C_INTMSK(bus->chn), TXEMP(0), RXFL(1)); | ||
172 | } | ||
173 | } | ||
174 | |||
175 | static void i2c_x1000_fifo_read(i2c_x1000_bus* bus) | ||
176 | { | ||
177 | /* Get number of bytes in the RX FIFO */ | ||
178 | int rx_n = REG_I2C_RXFLR(bus->chn); | ||
179 | |||
180 | /* Shouldn't happen, but check just in case */ | ||
181 | if(rx_n > bus->count[1]) { | ||
182 | panicf("i2c_x1000(%d): expected %d bytes in RX fifo, got %d", | ||
183 | bus->chn, bus->count[1], rx_n); | ||
184 | } | ||
185 | |||
186 | /* Fill buffer with data from FIFO */ | ||
187 | bus->count[1] -= rx_n; | ||
188 | for(; rx_n != 0; --rx_n) { | ||
189 | *bus->buffer[1]++ = jz_readf(I2C_DC(bus->chn), DAT); | ||
190 | } | ||
191 | } | ||
192 | |||
193 | static void i2c_x1000_interrupt(i2c_x1000_bus* bus) | ||
194 | { | ||
195 | int intr = REG_I2C_INTST(bus->chn); | ||
196 | int status = I2C_STATUS_OK; | ||
197 | |||
198 | /* Bus error; we can't prevent this from happening. As I understand | ||
199 | * it, we cannot get a TXABT when the bus is idle, so it should be | ||
200 | * safe to leave this interrupt unmasked all the time. | ||
201 | */ | ||
202 | if(intr & jz_orm(I2C_INTST, TXABT)) { | ||
203 | logf("i2c_x1000(%d): got TXABT (%08lx)", | ||
204 | bus->chn, REG_I2C_ABTSRC(bus->chn)); | ||
205 | |||
206 | REG_I2C_CTXABT(bus->chn); | ||
207 | status = I2C_STATUS_ERROR; | ||
208 | goto _done; | ||
209 | } | ||
210 | |||
211 | /* FIFO errors shouldn't occur unless driver did something dumb */ | ||
212 | if(intr & jz_orm(I2C_INTST, RXUF, TXOF, RXOF)) { | ||
213 | #if 1 | ||
214 | panicf("i2c_x1000(%d): fifo error (%08x)", bus->chn, intr); | ||
215 | #else | ||
216 | /* This is how the error condition would be cleared */ | ||
217 | REG_I2C_CTXOF(bus->chn); | ||
218 | REG_I2C_CRXOF(bus->chn); | ||
219 | REG_I2C_CRXUF(bus->chn); | ||
220 | status = I2C_STATUS_ERROR; | ||
221 | goto _done; | ||
222 | #endif | ||
223 | } | ||
224 | |||
225 | /* Read from FIFO on reads, and check if we have sent/received | ||
226 | * the expected amount of data. If so, complete the descriptor. */ | ||
227 | if(bus->tran_mode == I2C_READ) { | ||
228 | i2c_x1000_fifo_read(bus); | ||
229 | if(bus->count[1] == 0) | ||
230 | goto _done; | ||
231 | } else if(bus->count[0] == 0) { | ||
232 | goto _done; | ||
233 | } | ||
234 | |||
235 | /* Still need to send or request data -- issue commands to FIFO */ | ||
236 | i2c_x1000_fifo_write(bus); | ||
237 | return; | ||
238 | |||
239 | _done: | ||
240 | jz_writef(I2C_INTMSK(bus->chn), TXEMP(0), RXFL(0)); | ||
241 | timeout_cancel(&bus->tmo); | ||
242 | __i2c_async_complete_callback(bus->chn, status); | ||
243 | } | ||
244 | |||
245 | void I2C0(void) | ||
246 | { | ||
247 | i2c_x1000_interrupt(&i2c_x1000_busses[0]); | ||
248 | } | ||
249 | |||
250 | void I2C1(void) | ||
251 | { | ||
252 | i2c_x1000_interrupt(&i2c_x1000_busses[1]); | ||
253 | } | ||
254 | |||
255 | void I2C2(void) | ||
256 | { | ||
257 | i2c_x1000_interrupt(&i2c_x1000_busses[2]); | ||
258 | } | ||
259 | |||
260 | static int i2c_x1000_bus_timeout(struct timeout* tmo) | ||
261 | { | ||
262 | /* Buggy device is preventing the operation from completing, so we | ||
263 | * can't do much except reset the bus and hope for the best. Device | ||
264 | * drivers can aid us by detecting the TIMEOUT status we return and | ||
265 | * resetting the device to get it out of a bugged state. */ | ||
266 | |||
267 | i2c_x1000_bus* bus = (i2c_x1000_bus*)tmo->data; | ||
268 | switch(bus->resetting) { | ||
269 | default: | ||
270 | /* Start of reset. Disable the controller */ | ||
271 | REG_I2C_INTMSK(bus->chn) = 0; | ||
272 | bus->resetting = 1; | ||
273 | jz_writef(I2C_ENABLE(bus->chn), ACTIVE(0)); | ||
274 | return 1; | ||
275 | case 1: | ||
276 | /* Check if controller is disabled yet */ | ||
277 | if(jz_readf(I2C_ENBST(bus->chn), ACTIVE)) | ||
278 | return 1; | ||
279 | |||
280 | /* Wait 10 ms after disabling to give time for bus to clear */ | ||
281 | bus->resetting = 2; | ||
282 | return HZ/100; | ||
283 | case 2: | ||
284 | /* Re-enable the controller */ | ||
285 | bus->resetting = 3; | ||
286 | jz_writef(I2C_ENABLE(bus->chn), ACTIVE(1)); | ||
287 | return 1; | ||
288 | case 3: | ||
289 | /* Check that controller is enabled */ | ||
290 | if(jz_readf(I2C_ENBST(bus->chn), ACTIVE) == 0) | ||
291 | return 1; | ||
292 | |||
293 | /* Reset complete */ | ||
294 | bus->resetting = 0; | ||
295 | jz_overwritef(I2C_INTMSK(bus->chn), RXFL(0), TXEMP(0), | ||
296 | TXABT(1), TXOF(1), RXOF(1), RXUF(1)); | ||
297 | __i2c_async_complete_callback(bus->chn, I2C_STATUS_TIMEOUT); | ||
298 | return 0; | ||
299 | } | ||
300 | } | ||
301 | |||
302 | void __i2c_async_submit(int busnr, i2c_descriptor* desc) | ||
303 | { | ||
304 | i2c_x1000_bus* bus = &i2c_x1000_busses[busnr]; | ||
305 | |||
306 | if(desc->tran_mode == I2C_READ) { | ||
307 | if(desc->count[0] > 0) { | ||
308 | /* Handle initial write as phase1 */ | ||
309 | bus->buffer[0] = desc->buffer[0]; | ||
310 | bus->count[0] = desc->count[0]; | ||
311 | bus->phase1 = true; | ||
312 | } else { | ||
313 | /* No initial write, skip directly to phase2 */ | ||
314 | bus->buffer[0] = NULL; | ||
315 | bus->count[0] = desc->count[1]; | ||
316 | bus->phase1 = false; | ||
317 | } | ||
318 | |||
319 | /* Set buffer/count for phase2 read */ | ||
320 | bus->buffer[1] = desc->buffer[1]; | ||
321 | bus->count[1] = desc->count[1]; | ||
322 | } else { | ||
323 | /* Writes always have to have buffer[0] populated; buffer[1] is | ||
324 | * allowed to be NULL (and thus count[1] = 0). This matches our | ||
325 | * phase logic so no need for anything special | ||
326 | */ | ||
327 | bus->buffer[0] = desc->buffer[0]; | ||
328 | bus->count[0] = desc->count[0]; | ||
329 | bus->buffer[1] = desc->buffer[1]; | ||
330 | bus->count[1] = desc->count[1]; | ||
331 | bus->phase1 = true; | ||
332 | } | ||
333 | |||
334 | /* Save bus condition and transfer mode */ | ||
335 | bus->bus_cond = desc->bus_cond; | ||
336 | bus->tran_mode = desc->tran_mode; | ||
337 | |||
338 | /* Byte counter is used to check for first and last byte and apply | ||
339 | * the requested end mode */ | ||
340 | bus->byte_cnt = 0; | ||
341 | bus->byte_cnt_end = desc->count[0] + desc->count[1]; | ||
342 | |||
343 | /* Ensure interrupts are cleared */ | ||
344 | REG_I2C_CINT(busnr); | ||
345 | |||
346 | /* Program target address */ | ||
347 | jz_overwritef(I2C_TAR(busnr), ADDR(desc->slave_addr & ~I2C_10BIT_ADDR), | ||
348 | 10BITS(desc->slave_addr & I2C_10BIT_ADDR ? 1 : 0)); | ||
349 | |||
350 | /* Do the initial FIFO fill; this sets up the needed interrupts. */ | ||
351 | i2c_x1000_fifo_write(bus); | ||
352 | |||
353 | /* Software timeout to deal with buggy slave devices that pull the bus | ||
354 | * high forever and leave us hanging. Use 100ms + whatever time should | ||
355 | * be needed to handle data transmission. Account for 9 bits per byte | ||
356 | * because of the ACKs necessary after each byte. | ||
357 | */ | ||
358 | long ticks = (HZ/10) + (HZ * 9 * bus->byte_cnt_end / bus->freq); | ||
359 | timeout_register(&bus->tmo, i2c_x1000_bus_timeout, ticks, (intptr_t)bus); | ||
360 | } | ||
361 | |||
362 | void i2c_init(void) | ||
363 | { | ||
364 | /* Initialize core */ | ||
365 | __i2c_async_init(); | ||
366 | |||
367 | /* Initialize our bus data structures */ | ||
368 | for(int i = 0; i < 3; ++i) { | ||
369 | i2c_x1000_busses[i].chn = i; | ||
370 | i2c_x1000_busses[i].freq = 0; | ||
371 | i2c_x1000_busses[i].resetting = 0; | ||
372 | } | ||
373 | } | ||
374 | |||
375 | /* Stuff only required during initialization is below, basically the same as | ||
376 | * the old driver except for how the IRQs are initially set up. */ | ||
377 | |||
378 | static const struct { | ||
379 | int port; | ||
380 | unsigned pins; | ||
381 | int func; | ||
382 | } i2c_x1000_gpio_data[] = { | ||
383 | {GPIO_B, 3 << 23, GPIO_DEVICE(0)}, | ||
384 | {GPIO_C, 3 << 26, GPIO_DEVICE(0)}, | ||
385 | /* Note: I2C1 is also on the following pins (normally used by LCD) */ | ||
386 | /* {GPIO_A, 3 << 0, GPIO_DEVICE(2)}, */ | ||
387 | {GPIO_D, 3 << 0, GPIO_DEVICE(1)}, | ||
388 | }; | ||
389 | |||
390 | static void i2c_x1000_gate(int chn, int gate) | ||
391 | { | ||
392 | switch(chn) { | ||
393 | case 0: jz_writef(CPM_CLKGR, I2C0(gate)); break; | ||
394 | case 1: jz_writef(CPM_CLKGR, I2C1(gate)); break; | ||
395 | case 2: jz_writef(CPM_CLKGR, I2C2(gate)); break; | ||
396 | default: break; | ||
397 | } | ||
398 | } | ||
399 | |||
400 | static void i2c_x1000_enable(int chn) | ||
401 | { | ||
402 | /* Enable controller */ | ||
403 | jz_writef(I2C_ENABLE(chn), ACTIVE(1)); | ||
404 | while(jz_readf(I2C_ENBST(chn), ACTIVE) == 0); | ||
405 | |||
406 | /* Set up interrutpts */ | ||
407 | jz_overwritef(I2C_INTMSK(chn), RXFL(0), TXEMP(0), | ||
408 | TXABT(1), TXOF(1), RXOF(1), RXUF(1)); | ||
409 | system_enable_irq(IRQ_I2C(chn)); | ||
410 | } | ||
411 | |||
412 | static void i2c_x1000_disable(int chn) | ||
413 | { | ||
414 | /* Disable interrupts */ | ||
415 | system_disable_irq(IRQ_I2C(chn)); | ||
416 | REG_I2C_INTMSK(chn) = 0; | ||
417 | |||
418 | /* Disable controller */ | ||
419 | jz_writef(I2C_ENABLE(chn), ACTIVE(0)); | ||
420 | while(jz_readf(I2C_ENBST(chn), ACTIVE)); | ||
421 | } | ||
422 | |||
423 | void i2c_x1000_set_freq(int chn, int freq) | ||
424 | { | ||
425 | /* Store frequency */ | ||
426 | i2c_x1000_busses[chn].freq = freq; | ||
427 | |||
428 | /* Disable the channel if previously active */ | ||
429 | i2c_x1000_gate(chn, 0); | ||
430 | if(jz_readf(I2C_ENBST(chn), ACTIVE) == 1) | ||
431 | i2c_x1000_disable(chn); | ||
432 | |||
433 | /* Request to shut down the channel */ | ||
434 | if(freq == 0) { | ||
435 | i2c_x1000_gate(chn, 1); | ||
436 | return; | ||
437 | } | ||
438 | |||
439 | /* Calculate timing parameters */ | ||
440 | unsigned pclk = clk_get(X1000_CLK_PCLK); | ||
441 | unsigned t_SU_DAT = pclk / (freq * 8); | ||
442 | unsigned t_HD_DAT = pclk / (freq * 12); | ||
443 | unsigned t_LOW = pclk / (freq * 2); | ||
444 | unsigned t_HIGH = pclk / (freq * 2); | ||
445 | if(t_SU_DAT > 1) t_SU_DAT -= 1; | ||
446 | if(t_SU_DAT > 255) t_SU_DAT = 255; | ||
447 | if(t_SU_DAT == 0) t_SU_DAT = 0; | ||
448 | if(t_HD_DAT > 0xffff) t_HD_DAT = 0xfff; | ||
449 | if(t_LOW < 8) t_LOW = 8; | ||
450 | if(t_HIGH < 6) t_HIGH = 6; | ||
451 | |||
452 | /* Control register setting */ | ||
453 | unsigned reg = jz_orf(I2C_CON, SLVDIS(1), RESTART(1), MD(1)); | ||
454 | if(freq <= I2C_FREQ_100K) | ||
455 | reg |= jz_orf(I2C_CON, SPEED_V(100K)); | ||
456 | else | ||
457 | reg |= jz_orf(I2C_CON, SPEED_V(400K)); | ||
458 | |||
459 | /* Write the new controller settings */ | ||
460 | jz_write(I2C_CON(chn), reg); | ||
461 | jz_write(I2C_SDASU(chn), t_SU_DAT); | ||
462 | jz_write(I2C_SDAHD(chn), t_HD_DAT); | ||
463 | if(freq <= I2C_FREQ_100K) { | ||
464 | jz_write(I2C_SLCNT(chn), t_LOW); | ||
465 | jz_write(I2C_SHCNT(chn), t_HIGH); | ||
466 | } else { | ||
467 | jz_write(I2C_FLCNT(chn), t_LOW); | ||
468 | jz_write(I2C_FHCNT(chn), t_HIGH); | ||
469 | } | ||
470 | |||
471 | /* Claim pins */ | ||
472 | gpio_config(i2c_x1000_gpio_data[chn].port, | ||
473 | i2c_x1000_gpio_data[chn].pins, | ||
474 | i2c_x1000_gpio_data[chn].func); | ||
475 | |||
476 | /* Enable the controller */ | ||
477 | i2c_x1000_enable(chn); | ||
478 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/i2c-x1000.h b/firmware/target/mips/ingenic_x1000/i2c-x1000.h new file mode 100644 index 0000000000..e76624d511 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/i2c-x1000.h | |||
@@ -0,0 +1,44 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef __I2C_X1000_H__ | ||
23 | #define __I2C_X1000_H__ | ||
24 | |||
25 | #include "i2c-async.h" | ||
26 | |||
27 | #define I2C_FREQ_100K 100000 | ||
28 | #define I2C_FREQ_400K 400000 | ||
29 | |||
30 | extern void i2c_init(void); | ||
31 | |||
32 | /* Configure the I2C controller prior to use. | ||
33 | * | ||
34 | * - freq: frequency of SCL, should be <= 400 KHz and >= 25 KHz | ||
35 | * - use I2C_FREQ_100K for 100 KHz | ||
36 | * - use I2C_FREQ_400K for 400 Khz | ||
37 | * - use 0 to disable the controller completely | ||
38 | * - frequencies below 25 KHz will violate timing constraints | ||
39 | * | ||
40 | * TODO: move this to the i2c-async API, it's simple enough | ||
41 | */ | ||
42 | extern void i2c_x1000_set_freq(int chn, int freq); | ||
43 | |||
44 | #endif /* __I2C_X1000_H__ */ | ||
diff --git a/firmware/target/mips/ingenic_x1000/irq-x1000.h b/firmware/target/mips/ingenic_x1000/irq-x1000.h new file mode 100644 index 0000000000..849e436dcf --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/irq-x1000.h | |||
@@ -0,0 +1,115 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef __IRQ_X1000_H__ | ||
23 | #define __IRQ_X1000_H__ | ||
24 | |||
25 | /* INTC(0) interrupts */ | ||
26 | #define IRQ0_DMIC 0 | ||
27 | #define IRQ0_AIC 1 | ||
28 | #define IRQ0_SFC 7 | ||
29 | #define IRQ0_SSI 8 | ||
30 | #define IRQ0_PDMA 10 | ||
31 | #define IRQ0_PDMAD 11 | ||
32 | #define IRQ0_GPIO3 14 | ||
33 | #define IRQ0_GPIO2 15 | ||
34 | #define IRQ0_GPIO1 16 | ||
35 | #define IRQ0_GPIO0 17 | ||
36 | #define IRQ0_OTG 21 | ||
37 | #define IRQ0_AES 23 | ||
38 | #define IRQ0_TCU2 25 | ||
39 | #define IRQ0_TCU1 26 | ||
40 | #define IRQ0_TCU0 27 | ||
41 | #define IRQ0_CIM 30 | ||
42 | #define IRQ0_LCD 31 | ||
43 | |||
44 | /* INTC(1) interrupts */ | ||
45 | #define IRQ1_RTC 0 | ||
46 | #define IRQ1_MSC1 4 | ||
47 | #define IRQ1_MSC0 5 | ||
48 | #define IRQ1_SCC 6 | ||
49 | #define IRQ1_PCM 8 | ||
50 | #define IRQ1_HARB2 12 | ||
51 | #define IRQ1_HARB0 14 | ||
52 | #define IRQ1_CPM 15 | ||
53 | #define IRQ1_UART2 17 | ||
54 | #define IRQ1_UART1 18 | ||
55 | #define IRQ1_UART0 19 | ||
56 | #define IRQ1_DDR 20 | ||
57 | #define IRQ1_EFUSE 22 | ||
58 | #define IRQ1_MAC 23 | ||
59 | #define IRQ1_I2C2 26 | ||
60 | #define IRQ1_I2C1 27 | ||
61 | #define IRQ1_I2C0 28 | ||
62 | #define IRQ1_I2C(c) (28 - (c)) | ||
63 | #define IRQ1_PDMAM 29 | ||
64 | #define IRQ1_JPEG 30 | ||
65 | |||
66 | /* Unified IRQ numbers */ | ||
67 | #define IRQ_DMIC IRQ0_DMIC | ||
68 | #define IRQ_AIC IRQ0_AIC | ||
69 | #define IRQ_SFC IRQ0_SFC | ||
70 | #define IRQ_SSI IRQ0_SSI | ||
71 | #define IRQ_PDMA IRQ0_PDMA | ||
72 | #define IRQ_PDMAD IRQ0_PDMAD | ||
73 | #define IRQ_GPIO3 IRQ0_GPIO3 | ||
74 | #define IRQ_GPIO2 IRQ0_GPIO2 | ||
75 | #define IRQ_GPIO1 IRQ0_GPIO1 | ||
76 | #define IRQ_GPIO0 IRQ0_GPIO0 | ||
77 | #define IRQ_OTG IRQ0_OTG | ||
78 | #define IRQ_AES IRQ0_AES | ||
79 | #define IRQ_TCU2 IRQ0_TCU2 | ||
80 | #define IRQ_TCU1 IRQ0_TCU1 | ||
81 | #define IRQ_TCU0 IRQ0_TCU0 | ||
82 | #define IRQ_CIM IRQ0_CIM | ||
83 | #define IRQ_LCD IRQ0_LCD | ||
84 | #define IRQ_RTC (32+IRQ1_RTC) | ||
85 | #define IRQ_MSC1 (32+IRQ1_MSC1) | ||
86 | #define IRQ_MSC0 (32+IRQ1_MSC0) | ||
87 | #define IRQ_SCC (32+IRQ1_SCC) | ||
88 | #define IRQ_PCM (32+IRQ1_PCM) | ||
89 | #define IRQ_HARB2 (32+IRQ1_HARB2) | ||
90 | #define IRQ_HARB0 (32+IRQ1_HARB0) | ||
91 | #define IRQ_CPM (32+IRQ1_CPM) | ||
92 | #define IRQ_UART2 (32+IRQ1_UART2) | ||
93 | #define IRQ_UART1 (32+IRQ1_UART1) | ||
94 | #define IRQ_UART0 (32+IRQ1_UART0) | ||
95 | #define IRQ_DDR (32+IRQ1_DDR) | ||
96 | #define IRQ_EFUSE (32+IRQ1_EFUSE) | ||
97 | #define IRQ_MAC (32+IRQ1_MAC) | ||
98 | #define IRQ_I2C2 (32+IRQ1_I2C2) | ||
99 | #define IRQ_I2C1 (32+IRQ1_I2C1) | ||
100 | #define IRQ_I2C0 (32+IRQ1_I2C0) | ||
101 | #define IRQ_I2C(c) (32+IRQ1_I2C(c)) | ||
102 | #define IRQ_PDMAM (32+IRQ1_PDMAM) | ||
103 | #define IRQ_JPEG (32+IRQ1_JPEG) | ||
104 | #define IRQ_GPIO(port, pin) (64 + 32*(port) + (pin)) | ||
105 | |||
106 | #define IRQ_IS_GROUP0(irq) (((irq) & 0xffffff20) == 0x00) | ||
107 | #define IRQ_IS_GROUP1(irq) (((irq) & 0xffffff20) == 0x20) | ||
108 | #define IRQ_IS_GPIO(irq) ((irq) >= 64) | ||
109 | |||
110 | #define IRQ_TO_GROUP0(irq) (irq) | ||
111 | #define IRQ_TO_GROUP1(irq) ((irq) - 32) | ||
112 | #define IRQ_TO_GPIO_PORT(irq) (((irq) - 64) >> 5) | ||
113 | #define IRQ_TO_GPIO_PIN(irq) (((irq) - 64) & 0x1f) | ||
114 | |||
115 | #endif /* __IRQ_X1000_H__ */ | ||
diff --git a/firmware/target/mips/ingenic_x1000/kernel-x1000.c b/firmware/target/mips/ingenic_x1000/kernel-x1000.c new file mode 100644 index 0000000000..c8105a3446 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/kernel-x1000.c | |||
@@ -0,0 +1,74 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "kernel.h" | ||
23 | #include "system.h" | ||
24 | #include "x1000/ost.h" | ||
25 | |||
26 | /* TODO: implement a CPU frequency switching policy based on CPU utilization | ||
27 | * | ||
28 | * The basic assumption is that the workload consumes a fixed number of CPU | ||
29 | * cycles per second on average (= utilization), so we can set the frequency | ||
30 | * based on that value. Audio playback should fit this usage pattern well, so | ||
31 | * it's a good fit for Rockbox. | ||
32 | * | ||
33 | * It's easier to understand in terms of fluid flow -- we need to keep | ||
34 | * a reservoir of water topped up, CPU frequency is the inflow rate, and | ||
35 | * CPU utilization is the outflow rate. The goal is to avoid running dry | ||
36 | * and minimize the inflow rate. | ||
37 | * | ||
38 | * The only tricky part here is handing usage spikes -- CPU frequency has to | ||
39 | * increase faster than utilization or there's a risk of audio dropouts. | ||
40 | * | ||
41 | * Rockbox CPU boost could be used as a hint to scale up frequency faster. | ||
42 | * If that's not necessary to get good results, HAVE_ADJUSTABLE_CPU_FREQ can | ||
43 | * be disabled entirely. | ||
44 | */ | ||
45 | |||
46 | #define CPU_IDLE_SAMPLES 100 | ||
47 | |||
48 | void tick_start(unsigned interval_in_ms) | ||
49 | { | ||
50 | jz_writef(OST_CTRL, PRESCALE1_V(BY_16)); | ||
51 | jz_write(OST_1DFR, interval_in_ms*(X1000_EXCLK_FREQ/16000)); | ||
52 | jz_write(OST_1CNT, 0); | ||
53 | jz_write(OST_1FLG, 0); | ||
54 | jz_write(OST_1MSK, 0); | ||
55 | jz_setf(OST_ENABLE, OST1); | ||
56 | } | ||
57 | |||
58 | void OST(void) | ||
59 | { | ||
60 | /* CPU idle time accounting */ | ||
61 | uint32_t now = __ost_read32(); | ||
62 | uint32_t div = now - __cpu_idle_reftick; | ||
63 | if(div != 0) { | ||
64 | uint32_t fraction = 1000 * __cpu_idle_ticks / div; | ||
65 | __cpu_idle_avg += fraction - __cpu_idle_avg / CPU_IDLE_SAMPLES; | ||
66 | __cpu_idle_cur = __cpu_idle_avg / CPU_IDLE_SAMPLES; | ||
67 | __cpu_idle_ticks = 0; | ||
68 | __cpu_idle_reftick = now; | ||
69 | } | ||
70 | |||
71 | /* Call regular kernel tick */ | ||
72 | jz_write(OST_1FLG, 0); | ||
73 | call_tick_tasks(); | ||
74 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/lcd-x1000.c b/firmware/target/mips/ingenic_x1000/lcd-x1000.c new file mode 100644 index 0000000000..aadf93c8ff --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/lcd-x1000.c | |||
@@ -0,0 +1,477 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "lcd.h" | ||
23 | #include "system.h" | ||
24 | #include "kernel.h" | ||
25 | #include "lcd-x1000.h" | ||
26 | #include "dma-x1000.h" | ||
27 | #include "irq-x1000.h" | ||
28 | #include "x1000/lcd.h" | ||
29 | #include "x1000/cpm.h" | ||
30 | #include <stdint.h> | ||
31 | #include <string.h> | ||
32 | |||
33 | #define LCD_DMA_CMD_SOFINT (1 << 31) | ||
34 | #define LCD_DMA_CMD_EOFINT (1 << 30) | ||
35 | #define LCD_DMA_CMD_COMMAND (1 << 29) | ||
36 | #define LCD_DMA_CMD_FRM_EN (1 << 26) | ||
37 | |||
38 | #define LCD_DMA_CNT_BPP_15BIT ((4 << 27)|(1<<30)) | ||
39 | #define LCD_DMA_CNT_BPP_16BIT (4 << 27) | ||
40 | #define LCD_DMA_CNT_BPP_18BIT_OR_24BIT (5 << 27) | ||
41 | |||
42 | struct lcd_dma_desc { | ||
43 | uint32_t da; /* Next descriptor address */ | ||
44 | uint32_t sa; /* Source buffer address */ | ||
45 | uint32_t fid; /* Frame ID */ | ||
46 | uint32_t cmd; /* Command bits */ | ||
47 | uint32_t osz; /* OFFSIZE register */ | ||
48 | uint32_t pw; /* page width */ | ||
49 | uint32_t cnt; /* CNUM / CPOS, depending on LCD_DMA_CMD_COMMAND bit */ | ||
50 | uint32_t fsz; /* Frame size (set to 0 for commands) */ | ||
51 | } __attribute__((aligned(32))); | ||
52 | |||
53 | /* We need two descriptors, one for framebuffer write command and one for | ||
54 | * frame data. Even if no command is needed we need a dummy command descriptor | ||
55 | * with cnt=0, or the hardware will refuse to transfer the frame data. | ||
56 | * | ||
57 | * First descriptor always has to be a command (lcd_dma_desc[0] here) or | ||
58 | * the hardware will give up. | ||
59 | */ | ||
60 | static struct lcd_dma_desc lcd_dma_desc[2]; | ||
61 | |||
62 | /* Shadow copy of main framebuffer, needed to avoid tearing */ | ||
63 | static fb_data shadowfb[LCD_HEIGHT*LCD_WIDTH] __attribute__((aligned(64))); | ||
64 | |||
65 | /* Signals DMA copy to shadow FB is done */ | ||
66 | static volatile int fbcopy_done; | ||
67 | |||
68 | /* True if we're in sleep mode */ | ||
69 | static bool lcd_sleeping = false; | ||
70 | |||
71 | /* Check if running with interrupts disabled (eg: panic screen) */ | ||
72 | #define lcd_panic_mode \ | ||
73 | UNLIKELY((read_c0_status() & 1) == 0) | ||
74 | |||
75 | static void lcd_init_controller(const struct lcd_tgt_config* cfg) | ||
76 | { | ||
77 | /* Set MCFG/MCFG_NEW according to target interface settings */ | ||
78 | unsigned mcfg = 0, mcfg_new = 0; | ||
79 | |||
80 | switch(cfg->cmd_width) { | ||
81 | case 8: mcfg |= BF_LCD_MCFG_CWIDTH_V(8BIT); break; | ||
82 | case 9: mcfg |= BF_LCD_MCFG_CWIDTH_V(16BIT_OR_9BIT); break; | ||
83 | case 16: mcfg |= BF_LCD_MCFG_CWIDTH_V(16BIT_OR_9BIT); break; | ||
84 | case 18: mcfg |= BF_LCD_MCFG_CWIDTH_V(18BIT); break; | ||
85 | case 24: mcfg |= BF_LCD_MCFG_CWIDTH_V(24BIT); break; | ||
86 | default: break; | ||
87 | } | ||
88 | |||
89 | if(cfg->cmd_width == 9) | ||
90 | mcfg_new |= BM_LCD_MCFG_NEW_CMD_9BIT; | ||
91 | |||
92 | switch(cfg->bus_width) { | ||
93 | case 8: mcfg_new |= BF_LCD_MCFG_NEW_DWIDTH_V(8BIT); break; | ||
94 | case 9: mcfg_new |= BF_LCD_MCFG_NEW_DWIDTH_V(9BIT); break; | ||
95 | case 16: mcfg_new |= BF_LCD_MCFG_NEW_DWIDTH_V(16BIT); break; | ||
96 | case 18: mcfg_new |= BF_LCD_MCFG_NEW_DWIDTH_V(18BIT); break; | ||
97 | case 24: mcfg_new |= BF_LCD_MCFG_NEW_DWIDTH_V(24BIT); break; | ||
98 | default: break; | ||
99 | } | ||
100 | |||
101 | if(lcd_tgt_config.use_serial) | ||
102 | mcfg_new |= jz_orf(LCD_MCFG_NEW, DTYPE_V(SERIAL), CTYPE_V(SERIAL)); | ||
103 | else | ||
104 | mcfg_new |= jz_orf(LCD_MCFG_NEW, DTYPE_V(PARALLEL), CTYPE_V(PARALLEL)); | ||
105 | |||
106 | jz_vwritef(mcfg_new, LCD_MCFG_NEW, | ||
107 | 6800_MODE(lcd_tgt_config.use_6800_mode), | ||
108 | CSPLY(lcd_tgt_config.wr_polarity ? 0 : 1), | ||
109 | RSPLY(lcd_tgt_config.dc_polarity), | ||
110 | CLKPLY(lcd_tgt_config.clk_polarity)); | ||
111 | |||
112 | /* Program the configuration. Note we cannot enable TE signal at | ||
113 | * this stage, because the panel will need to be configured first. | ||
114 | */ | ||
115 | jz_write(LCD_MCFG, mcfg); | ||
116 | jz_write(LCD_MCFG_NEW, mcfg_new); | ||
117 | jz_writef(LCD_MCTRL, NARROW_TE(0), TE_INV(0), NOT_USE_TE(1), | ||
118 | DCSI_SEL(0), MIPI_SLCD(0), FAST_MODE(1), GATE_MASK(0), | ||
119 | DMA_MODE(1), DMA_START(0), DMA_TX_EN(0)); | ||
120 | jz_writef(LCD_WTIME, DHTIME(0), DLTIME(0), CHTIME(0), CLTIME(0)); | ||
121 | jz_writef(LCD_TASH, TAH(0), TAS(0)); | ||
122 | jz_write(LCD_SMWT, 0); | ||
123 | |||
124 | /* DMA settings */ | ||
125 | jz_writef(LCD_CTRL, BURST_V(64WORD), | ||
126 | EOFM(1), SOFM(0), IFUM(0), QDM(0), | ||
127 | BEDN(0), PEDN(0), ENABLE(0)); | ||
128 | jz_write(LCD_DAH, LCD_WIDTH); | ||
129 | jz_write(LCD_DAV, LCD_HEIGHT); | ||
130 | } | ||
131 | |||
132 | static void lcd_fbcopy_dma_cb(int evt); | ||
133 | |||
134 | static void lcd_init_descriptors(const struct lcd_tgt_config* cfg) | ||
135 | { | ||
136 | struct lcd_dma_desc* desc = &lcd_dma_desc[0]; | ||
137 | int cmdsize = cfg->dma_wr_cmd_size / 4; | ||
138 | |||
139 | /* Set up the command descriptor */ | ||
140 | desc[0].da = PHYSADDR(&desc[1]); | ||
141 | desc[0].sa = PHYSADDR(cfg->dma_wr_cmd_buf); | ||
142 | desc[0].fid = 0xc0; | ||
143 | desc[0].cmd = LCD_DMA_CMD_COMMAND | cmdsize; | ||
144 | desc[0].osz = 0; | ||
145 | desc[0].pw = 0; | ||
146 | desc[0].fsz = 0; | ||
147 | switch(cfg->cmd_width) { | ||
148 | case 8: desc[0].cnt = 4*cmdsize; break; | ||
149 | case 9: | ||
150 | case 16: desc[0].cnt = 2*cmdsize; break; | ||
151 | case 18: | ||
152 | case 24: desc[0].cnt = cmdsize; break; | ||
153 | default: break; | ||
154 | } | ||
155 | |||
156 | /* Set up the frame descriptor */ | ||
157 | desc[1].da = PHYSADDR(&desc[0]); | ||
158 | desc[1].sa = PHYSADDR(shadowfb); | ||
159 | desc[1].fid = 0xf0; | ||
160 | desc[1].cmd = LCD_DMA_CMD_EOFINT | LCD_DMA_CMD_FRM_EN | | ||
161 | (LCD_WIDTH * LCD_HEIGHT * sizeof(fb_data) / 4); | ||
162 | desc[1].osz = 0; | ||
163 | desc[1].pw = 0; | ||
164 | desc[1].fsz = (LCD_WIDTH - 1) | ((LCD_HEIGHT - 1) << 12); | ||
165 | #if LCD_DEPTH == 16 | ||
166 | desc[1].cnt = LCD_DMA_CNT_BPP_16BIT; | ||
167 | #elif LCD_DEPTH == 24 | ||
168 | desc[1].cnt = LCD_DMA_CNT_BPP_18BIT_OR_24BIT; | ||
169 | #else | ||
170 | # error "unsupported LCD bit depth" | ||
171 | #endif | ||
172 | |||
173 | /* Commit LCD DMA descriptors */ | ||
174 | commit_dcache_range(&desc[0], 2*sizeof(struct lcd_dma_desc)); | ||
175 | |||
176 | /* Set fbcopy channel callback */ | ||
177 | dma_set_callback(DMA_CHANNEL_FBCOPY, lcd_fbcopy_dma_cb); | ||
178 | } | ||
179 | |||
180 | static void lcd_fbcopy_dma_cb(int evt) | ||
181 | { | ||
182 | (void)evt; | ||
183 | fbcopy_done = 1; | ||
184 | } | ||
185 | |||
186 | static void lcd_fbcopy_dma_run(dma_desc* d) | ||
187 | { | ||
188 | if(lcd_panic_mode) { | ||
189 | /* Can't use DMA if interrupts are off, so just do a memcpy(). | ||
190 | * Doesn't need to be efficient, since AFAIK the panic screen is | ||
191 | * the only place that can update the LCD with interrupts disabled. */ | ||
192 | memcpy(shadowfb, FBADDR(0, 0), LCD_WIDTH*LCD_HEIGHT*sizeof(fb_data)); | ||
193 | commit_dcache(); | ||
194 | return; | ||
195 | } | ||
196 | |||
197 | commit_dcache_range(d, sizeof(struct dma_desc)); | ||
198 | |||
199 | /* Start the transfer */ | ||
200 | fbcopy_done = 0; | ||
201 | REG_DMA_CHN_DA(DMA_CHANNEL_FBCOPY) = PHYSADDR(d); | ||
202 | jz_writef(DMA_CHN_CS(DMA_CHANNEL_FBCOPY), DES8(1), NDES(0)); | ||
203 | jz_set(DMA_DB, 1 << DMA_CHANNEL_FBCOPY); | ||
204 | jz_writef(DMA_CHN_CS(DMA_CHANNEL_FBCOPY), CTE(1)); | ||
205 | |||
206 | while(!fbcopy_done); | ||
207 | } | ||
208 | |||
209 | static void lcd_fbcopy_dma_full(void) | ||
210 | { | ||
211 | dma_desc d; | ||
212 | d.cm = jz_orf(DMA_CHN_CM, SAI(1), DAI(1), RDIL(9), | ||
213 | SP_V(32BIT), DP_V(32BIT), TSZ_V(AUTO), | ||
214 | STDE(0), TIE(1), LINK(0)); | ||
215 | d.sa = PHYSADDR(FBADDR(0, 0)); | ||
216 | d.ta = PHYSADDR(shadowfb); | ||
217 | d.tc = LCD_WIDTH * LCD_HEIGHT * sizeof(fb_data); | ||
218 | d.sd = 0; | ||
219 | d.rt = jz_orf(DMA_CHN_RT, TYPE_V(AUTO)); | ||
220 | d.pad0 = 0; | ||
221 | d.pad1 = 0; | ||
222 | lcd_fbcopy_dma_run(&d); | ||
223 | } | ||
224 | |||
225 | /* NOTE: DMA stride mode can only transfer up to 255 blocks at once. | ||
226 | * | ||
227 | * - for LCD_STRIDEFORMAT == VERTICAL_STRIDE, keep width <= 255 | ||
228 | * - for LCD_STRIDEFORMAT == HORIZONTAL_STRIDE, keep height <= 255 | ||
229 | */ | ||
230 | static void lcd_fbcopy_dma_partial1(int x, int y, int width, int height) | ||
231 | { | ||
232 | int stride = STRIDE_MAIN(LCD_WIDTH - width, LCD_HEIGHT - height); | ||
233 | |||
234 | dma_desc d; | ||
235 | d.cm = jz_orf(DMA_CHN_CM, SAI(1), DAI(1), RDIL(9), | ||
236 | SP_V(32BIT), DP_V(32BIT), TSZ_V(AUTO), | ||
237 | STDE(stride ? 1 : 0), TIE(1), LINK(0)); | ||
238 | d.sa = PHYSADDR(FBADDR(x, y)); | ||
239 | d.ta = PHYSADDR(&shadowfb[STRIDE_MAIN(y * LCD_WIDTH + x, | ||
240 | x * LCD_HEIGHT + y)]); | ||
241 | d.rt = jz_orf(DMA_CHN_RT, TYPE_V(AUTO)); | ||
242 | d.pad0 = 0; | ||
243 | d.pad1 = 0; | ||
244 | |||
245 | if(stride) { | ||
246 | stride *= sizeof(fb_data); | ||
247 | d.sd = (stride << 16) | stride; | ||
248 | d.tc = (STRIDE_MAIN(height, width) << 16) | | ||
249 | (STRIDE_MAIN(width, height) * sizeof(fb_data)); | ||
250 | } else { | ||
251 | d.sd = 0; | ||
252 | d.tc = width * height * sizeof(fb_data); | ||
253 | } | ||
254 | |||
255 | lcd_fbcopy_dma_run(&d); | ||
256 | } | ||
257 | |||
258 | #if STRIDE_MAIN(LCD_HEIGHT, LCD_WIDTH) > 255 | ||
259 | static void lcd_fbcopy_dma_partial(int x, int y, int width, int height) | ||
260 | { | ||
261 | do { | ||
262 | int count = MIN(STRIDE_MAIN(height, width), 255); | ||
263 | |||
264 | lcd_fbcopy_dma_partial1(x, y, STRIDE_MAIN(width, count), | ||
265 | STRIDE_MAIN(count, height)); | ||
266 | |||
267 | STRIDE_MAIN(height, width) -= count; | ||
268 | STRIDE_MAIN(y, x) += count; | ||
269 | } while(STRIDE_MAIN(height, width) != 0); | ||
270 | } | ||
271 | #else | ||
272 | # define lcd_fbcopy_dma_partial lcd_fbcopy_dma_partial1 | ||
273 | #endif | ||
274 | |||
275 | static void lcd_dma_start(void) | ||
276 | { | ||
277 | /* Set format conversion bit, seems necessary for DMA mode */ | ||
278 | jz_writef(LCD_MCFG_NEW, FMT_CONV(1)); | ||
279 | |||
280 | /* Program vsync configuration */ | ||
281 | jz_writef(LCD_MCTRL, NARROW_TE(lcd_tgt_config.te_narrow), | ||
282 | TE_INV(lcd_tgt_config.te_polarity ? 0 : 1), | ||
283 | NOT_USE_TE(lcd_tgt_config.te_enable ? 0 : 1)); | ||
284 | |||
285 | /* Begin DMA transfer. Need to start a dummy frame or else we will | ||
286 | * not be able to pass lcd_wait_frame() at the first lcd_update(). */ | ||
287 | jz_write(LCD_STATE, 0); | ||
288 | jz_write(LCD_DA, PHYSADDR(&lcd_dma_desc[0])); | ||
289 | jz_writef(LCD_MCTRL, DMA_MODE(1), DMA_START(1), DMA_TX_EN(1)); | ||
290 | jz_writef(LCD_CTRL, ENABLE(1)); | ||
291 | } | ||
292 | |||
293 | static void lcd_dma_stop(void) | ||
294 | { | ||
295 | /* Stop the DMA transfer */ | ||
296 | jz_writef(LCD_CTRL, ENABLE(0)); | ||
297 | jz_writef(LCD_MCTRL, DMA_TX_EN(0)); | ||
298 | |||
299 | /* Wait for disable to take effect */ | ||
300 | while(jz_readf(LCD_STATE, QD) == 0); | ||
301 | jz_writef(LCD_STATE, QD(0)); | ||
302 | |||
303 | /* Clear format conversion bit, disable vsync */ | ||
304 | jz_writef(LCD_MCFG_NEW, FMT_CONV(0)); | ||
305 | jz_writef(LCD_MCTRL, NARROW_TE(0), TE_INV(0), NOT_USE_TE(1)); | ||
306 | } | ||
307 | |||
308 | static bool lcd_wait_frame(void) | ||
309 | { | ||
310 | /* Bail out if DMA is not enabled */ | ||
311 | int irq = disable_irq_save(); | ||
312 | int bit = jz_readf(LCD_CTRL, ENABLE); | ||
313 | restore_irq(irq); | ||
314 | if(!bit) | ||
315 | return false; | ||
316 | |||
317 | /* Usual case -- wait for EOF, wait for FIFO to drain, clear EOF */ | ||
318 | while(jz_readf(LCD_STATE, EOF) == 0); | ||
319 | while(jz_readf(LCD_MSTATE, BUSY)); | ||
320 | jz_writef(LCD_STATE, EOF(0)); | ||
321 | return true; | ||
322 | } | ||
323 | |||
324 | static void lcd_send(uint32_t d) | ||
325 | { | ||
326 | while(jz_readf(LCD_MSTATE, BUSY)); | ||
327 | REG_LCD_MDATA = d; | ||
328 | } | ||
329 | |||
330 | void lcd_set_clock(x1000_clk_t clk, uint32_t freq) | ||
331 | { | ||
332 | uint32_t in_freq = clk_get(clk); | ||
333 | uint32_t div = clk_calc_div(in_freq, freq); | ||
334 | |||
335 | jz_writef(CPM_LPCDR, CE(1), CLKDIV(div - 1), | ||
336 | CLKSRC(clk == X1000_CLK_MPLL ? 1 : 0)); | ||
337 | while(jz_readf(CPM_LPCDR, BUSY)); | ||
338 | jz_writef(CPM_LPCDR, CE(0)); | ||
339 | } | ||
340 | |||
341 | void lcd_exec_commands(const uint32_t* cmdseq) | ||
342 | { | ||
343 | while(*cmdseq != LCD_INSTR_END) { | ||
344 | uint32_t instr = *cmdseq++; | ||
345 | uint32_t d = 0; | ||
346 | switch(instr) { | ||
347 | case LCD_INSTR_CMD: | ||
348 | d = jz_orf(LCD_MDATA, TYPE_V(CMD)); | ||
349 | /* fallthrough */ | ||
350 | |||
351 | case LCD_INSTR_DAT: | ||
352 | d |= *cmdseq++; | ||
353 | lcd_send(d); | ||
354 | break; | ||
355 | |||
356 | case LCD_INSTR_UDELAY: | ||
357 | udelay(*cmdseq++); | ||
358 | break; | ||
359 | |||
360 | default: | ||
361 | break; | ||
362 | } | ||
363 | } | ||
364 | } | ||
365 | |||
366 | void lcd_init_device(void) | ||
367 | { | ||
368 | jz_writef(CPM_CLKGR, LCD(0)); | ||
369 | |||
370 | lcd_init_controller(&lcd_tgt_config); | ||
371 | lcd_init_descriptors(&lcd_tgt_config); | ||
372 | |||
373 | lcd_tgt_enable(true); | ||
374 | |||
375 | lcd_dma_start(); | ||
376 | } | ||
377 | |||
378 | #ifdef HAVE_LCD_SHUTDOWN | ||
379 | void lcd_shutdown(void) | ||
380 | { | ||
381 | if(lcd_sleeping) | ||
382 | lcd_tgt_sleep(false); | ||
383 | else if(jz_readf(LCD_CTRL, ENABLE)) | ||
384 | lcd_dma_stop(); | ||
385 | |||
386 | lcd_tgt_enable(false); | ||
387 | jz_writef(CPM_CLKGR, LCD(1)); | ||
388 | } | ||
389 | #endif | ||
390 | |||
391 | #if defined(HAVE_LCD_ENABLE) || defined(HAVE_LCD_SLEEP) | ||
392 | bool lcd_active(void) | ||
393 | { | ||
394 | return jz_readf(LCD_CTRL, ENABLE); | ||
395 | } | ||
396 | |||
397 | void lcd_enable(bool en) | ||
398 | { | ||
399 | /* Must disable IRQs to turn off the running LCD */ | ||
400 | int irq = disable_irq_save(); | ||
401 | int bit = jz_readf(LCD_CTRL, ENABLE); | ||
402 | if(bit && !en) | ||
403 | lcd_dma_stop(); | ||
404 | restore_irq(irq); | ||
405 | |||
406 | /* Deal with sleep mode */ | ||
407 | #ifdef LCD_X1000_FASTSLEEP | ||
408 | if(bit && !en) { | ||
409 | lcd_tgt_sleep(true); | ||
410 | lcd_sleeping = true; | ||
411 | } else | ||
412 | #endif | ||
413 | if(!bit && en && lcd_sleeping) { | ||
414 | lcd_tgt_sleep(false); | ||
415 | lcd_sleeping = false; | ||
416 | } | ||
417 | |||
418 | /* Handle turning the LCD back on */ | ||
419 | if(!bit && en) | ||
420 | lcd_dma_start(); | ||
421 | } | ||
422 | #endif | ||
423 | |||
424 | #if defined(HAVE_LCD_SLEEP) | ||
425 | #if defined(LCD_X1000_FASTSLEEP) | ||
426 | # error "Do not define HAVE_LCD_SLEEP if target has LCD_X1000_FASTSLEEP" | ||
427 | #endif | ||
428 | |||
429 | void lcd_sleep(void) | ||
430 | { | ||
431 | if(!lcd_sleeping) { | ||
432 | lcd_enable(false); | ||
433 | lcd_tgt_sleep(true); | ||
434 | lcd_sleeping = true; | ||
435 | } | ||
436 | } | ||
437 | #endif | ||
438 | |||
439 | void lcd_update(void) | ||
440 | { | ||
441 | if(!lcd_wait_frame()) | ||
442 | return; | ||
443 | |||
444 | commit_dcache(); | ||
445 | lcd_fbcopy_dma_full(); | ||
446 | jz_writef(LCD_MCTRL, DMA_START(1), DMA_MODE(1)); | ||
447 | } | ||
448 | |||
449 | void lcd_update_rect(int x, int y, int width, int height) | ||
450 | { | ||
451 | /* Clamp the coordinates */ | ||
452 | if(x < 0) { | ||
453 | width += x; | ||
454 | x = 0; | ||
455 | } | ||
456 | |||
457 | if(y < 0) { | ||
458 | height += y; | ||
459 | y = 0; | ||
460 | } | ||
461 | |||
462 | if(width > LCD_WIDTH - x) | ||
463 | width = LCD_WIDTH - x; | ||
464 | |||
465 | if(height > LCD_HEIGHT - y) | ||
466 | height = LCD_HEIGHT - y; | ||
467 | |||
468 | if(width < 0 || height < 0) | ||
469 | return; | ||
470 | |||
471 | if(!lcd_wait_frame()) | ||
472 | return; | ||
473 | |||
474 | commit_dcache(); | ||
475 | lcd_fbcopy_dma_partial(x, y, width, height); | ||
476 | jz_writef(LCD_MCTRL, DMA_START(1), DMA_MODE(1)); | ||
477 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/lcd-x1000.h b/firmware/target/mips/ingenic_x1000/lcd-x1000.h new file mode 100644 index 0000000000..96085ac207 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/lcd-x1000.h | |||
@@ -0,0 +1,110 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef __LCD_X1000_H__ | ||
23 | #define __LCD_X1000_H__ | ||
24 | |||
25 | /* NOTICE: if adding LCD support for a new X1000 target, please take a look | ||
26 | * at the implementation in case there's any difficulties; there may be some | ||
27 | * parts that need adjusting. The X1000 LCD interface is poorly documented | ||
28 | * and it might be necessary to change some settings by trial and error to | ||
29 | * match the panel. */ | ||
30 | |||
31 | #include "clk-x1000.h" | ||
32 | #include <stdbool.h> | ||
33 | |||
34 | #define LCD_INSTR_CMD 0 | ||
35 | #define LCD_INSTR_DAT 1 | ||
36 | #define LCD_INSTR_UDELAY 2 | ||
37 | #define LCD_INSTR_END 3 | ||
38 | |||
39 | struct lcd_tgt_config { | ||
40 | /* Data bus width, in bits */ | ||
41 | int bus_width: 8; | ||
42 | |||
43 | /* Command bus width, in bits */ | ||
44 | int cmd_width: 8; | ||
45 | |||
46 | /* 1 = use 6800 timings, 0 = use 8080 timings */ | ||
47 | int use_6800_mode: 1; | ||
48 | |||
49 | /* 1 = serial interface, 0 = parallel interface */ | ||
50 | int use_serial: 1; | ||
51 | |||
52 | /* Clock active edge: 0 = falling edge, 1 = rising edge */ | ||
53 | int clk_polarity: 1; | ||
54 | |||
55 | /* DC pin levels: 1 = data high, command low; 0 = data low, command high */ | ||
56 | int dc_polarity: 1; | ||
57 | |||
58 | /* WR pin level during idle: 1 = keep high; 0 = keep low */ | ||
59 | int wr_polarity: 1; | ||
60 | |||
61 | /* 1 to enable vsync, so DMA transfer is synchronized with TE signal */ | ||
62 | int te_enable: 1; | ||
63 | |||
64 | /* Active level of TE signal: 1 = high, 0 = low */ | ||
65 | int te_polarity: 1; | ||
66 | |||
67 | /* 1 = support narrow TE signal (<=3 pixel clocks); 0 = don't support */ | ||
68 | int te_narrow: 1; | ||
69 | |||
70 | /* Commands used to initiate a framebuffer write. Buffer must be | ||
71 | * aligned to 64-byte boundary and size must be a multiple of 4, | ||
72 | * regardless of the command bus width. */ | ||
73 | const void* dma_wr_cmd_buf; | ||
74 | size_t dma_wr_cmd_size; | ||
75 | }; | ||
76 | |||
77 | /* Static configuration for the target's LCD, must be defined by target. */ | ||
78 | extern const struct lcd_tgt_config lcd_tgt_config; | ||
79 | |||
80 | /* Set the pixel clock. Valid clock sources are SCLK_A and MPLL. */ | ||
81 | extern void lcd_set_clock(x1000_clk_t clksrc, uint32_t freq); | ||
82 | |||
83 | /* Execute a sequence of LCD commands. Should only be called from | ||
84 | * lcd_tgt_ctl_enable() and lcd_tgt_ctl_sleep(). | ||
85 | * | ||
86 | * The array should be a list of pairs (instr, arg), with LCD_INSTR_END | ||
87 | * as the last entry. | ||
88 | * | ||
89 | * - LCD_INSTR_CMD, cmd: issue command write of 'cmd' | ||
90 | * - LCD_INSTR_DAT, dat: issue data write of 'dat' | ||
91 | * - LCD_INSTR_UDELAY, us: call udelay(us) | ||
92 | */ | ||
93 | extern void lcd_exec_commands(const uint32_t* cmdseq); | ||
94 | |||
95 | /* Enable/disable the LCD controller. | ||
96 | * | ||
97 | * - On enabling: power on the LCD, set the pixel clock with lcd_set_clock(), | ||
98 | * and use lcd_exec_commands() to send any needed initialization commands. | ||
99 | * | ||
100 | * - On disabling: use lcd_exec_commands() to send shutdown commands to the | ||
101 | * controller and disable the LCD power supply. | ||
102 | */ | ||
103 | extern void lcd_tgt_enable(bool on); | ||
104 | |||
105 | /* Enter or exit sleep mode to save power, normally by sending the necessary | ||
106 | * commands with lcd_exec_commands(). | ||
107 | */ | ||
108 | extern void lcd_tgt_sleep(bool sleep); | ||
109 | |||
110 | #endif /* __LCD_X1000_H__ */ | ||
diff --git a/firmware/target/mips/ingenic_x1000/msc-x1000.c b/firmware/target/mips/ingenic_x1000/msc-x1000.c new file mode 100644 index 0000000000..62aa76988c --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/msc-x1000.c | |||
@@ -0,0 +1,904 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "system.h" | ||
23 | #include "panic.h" | ||
24 | #include "msc-x1000.h" | ||
25 | #include "gpio-x1000.h" | ||
26 | #include "irq-x1000.h" | ||
27 | #include "clk-x1000.h" | ||
28 | #include "x1000/msc.h" | ||
29 | #include "x1000/cpm.h" | ||
30 | #include <string.h> | ||
31 | #include <stddef.h> | ||
32 | |||
33 | /* #define LOGF_ENABLE */ | ||
34 | #include "logf.h" | ||
35 | |||
36 | /* TODO - this needs some auditing to better handle errors | ||
37 | * | ||
38 | * There should be a clearer code path involving errors. Especially we should | ||
39 | * ensure that removing the card always resets the driver to a sane state. | ||
40 | */ | ||
41 | |||
42 | static const msc_config msc_configs[] = { | ||
43 | #ifdef FIIO_M3K | ||
44 | #define MSC_CLOCK_SOURCE X1000_CLK_SCLK_A | ||
45 | #define msc0_cd_interrupt GPIOB06 | ||
46 | { | ||
47 | .msc_nr = 0, | ||
48 | .msc_type = MSC_TYPE_SD, | ||
49 | .bus_width = 4, | ||
50 | .label = "microSD", | ||
51 | .cd_gpio = {GPIO_B, 1 << 6, 0}, | ||
52 | }, | ||
53 | #else | ||
54 | # error "Please add X1000 MSC config" | ||
55 | #endif | ||
56 | {.msc_nr = -1}, | ||
57 | }; | ||
58 | |||
59 | static const msc_config* msc_lookup_config(int msc) | ||
60 | { | ||
61 | for(int i = 0; i < MSC_COUNT; ++i) | ||
62 | if(msc_configs[i].msc_nr == msc) | ||
63 | return &msc_configs[i]; | ||
64 | return NULL; | ||
65 | } | ||
66 | |||
67 | static msc_drv msc_drivers[MSC_COUNT]; | ||
68 | |||
69 | /* --------------------------------------------------------------------------- | ||
70 | * Initialization | ||
71 | */ | ||
72 | |||
73 | static void msc_gate_clock(int msc, bool gate) | ||
74 | { | ||
75 | int bit; | ||
76 | if(msc == 0) | ||
77 | bit = BM_CPM_CLKGR_MSC0; | ||
78 | else | ||
79 | bit = BM_CPM_CLKGR_MSC1; | ||
80 | |||
81 | if(gate) | ||
82 | REG_CPM_CLKGR |= bit; | ||
83 | else | ||
84 | REG_CPM_CLKGR &= ~bit; | ||
85 | } | ||
86 | |||
87 | static void msc_init_one(msc_drv* d, int msc) | ||
88 | { | ||
89 | /* Lookup config */ | ||
90 | d->drive_nr = -1; | ||
91 | d->config = msc_lookup_config(msc); | ||
92 | if(!d->config) { | ||
93 | d->msc_nr = -1; | ||
94 | return; | ||
95 | } | ||
96 | |||
97 | /* Initialize driver state */ | ||
98 | d->msc_nr = msc; | ||
99 | d->driver_flags = 0; | ||
100 | d->clk_status = 0; | ||
101 | d->cmdat_def = jz_orf(MSC_CMDAT, RTRG_V(GE32), TTRG_V(LE32)); | ||
102 | d->req = NULL; | ||
103 | d->iflag_done = 0; | ||
104 | d->card_present = 1; | ||
105 | d->req_running = 0; | ||
106 | mutex_init(&d->lock); | ||
107 | semaphore_init(&d->cmd_done, 1, 0); | ||
108 | |||
109 | /* Ensure correct clock source */ | ||
110 | jz_writef(CPM_MSC0CDR, CE(1), CLKDIV(0), | ||
111 | CLKSRC(MSC_CLOCK_SOURCE == X1000_CLK_MPLL ? 1 : 0)); | ||
112 | while(jz_readf(CPM_MSC0CDR, BUSY)); | ||
113 | jz_writef(CPM_MSC0CDR, CE(0)); | ||
114 | |||
115 | /* Initialize the hardware */ | ||
116 | msc_gate_clock(msc, false); | ||
117 | msc_full_reset(d); | ||
118 | system_enable_irq(msc == 0 ? IRQ_MSC0 : IRQ_MSC1); | ||
119 | |||
120 | /* Configure bus pins */ | ||
121 | int port, device; | ||
122 | unsigned pins; | ||
123 | if(msc == 0) { | ||
124 | port = GPIO_A; | ||
125 | device = 1; | ||
126 | switch(d->config->bus_width) { | ||
127 | case 8: pins = 0x3ff << 16; break; | ||
128 | case 4: pins = 0x03f << 20; break; | ||
129 | case 1: pins = 0x007 << 23; break; | ||
130 | default: pins = 0; break; | ||
131 | } | ||
132 | } else { | ||
133 | port = GPIO_C; | ||
134 | device = 0; | ||
135 | switch(d->config->bus_width) { | ||
136 | case 4: pins = 0x3f; break; | ||
137 | case 1: pins = 0x07; break; | ||
138 | default: pins = 0; break; | ||
139 | } | ||
140 | } | ||
141 | |||
142 | gpio_config(port, pins, GPIO_DEVICE(device)); | ||
143 | |||
144 | /* Setup the card detect IRQ */ | ||
145 | if(d->config->cd_gpio.pin) { | ||
146 | port = d->config->cd_gpio.port; | ||
147 | pins = d->config->cd_gpio.pin; | ||
148 | int level = (REG_GPIO_PIN(port) & pins) ? 1 : 0; | ||
149 | if(level != d->config->cd_gpio.active_level) | ||
150 | d->card_present = 0; | ||
151 | |||
152 | gpio_config(port, pins, GPIO_IRQ_EDGE(level ? 0 : 1)); | ||
153 | gpio_enable_irq(port, pins); | ||
154 | } | ||
155 | } | ||
156 | |||
157 | void msc_init(void) | ||
158 | { | ||
159 | /* Only do this once -- each storage subsystem calls us in its init */ | ||
160 | static bool done = false; | ||
161 | if(done) | ||
162 | return; | ||
163 | done = true; | ||
164 | |||
165 | /* Set up each MSC driver according to msc_configs */ | ||
166 | for(int i = 0; i < MSC_COUNT; ++i) | ||
167 | msc_init_one(&msc_drivers[i], i); | ||
168 | } | ||
169 | |||
170 | msc_drv* msc_get(int type, int index) | ||
171 | { | ||
172 | for(int i = 0, m = 0; i < MSC_COUNT; ++i) { | ||
173 | if(msc_drivers[i].config == NULL) | ||
174 | continue; | ||
175 | if(type == MSC_TYPE_ANY || msc_drivers[i].config->msc_type == type) | ||
176 | if(index == m++) | ||
177 | return &msc_drivers[i]; | ||
178 | } | ||
179 | |||
180 | return NULL; | ||
181 | } | ||
182 | |||
183 | msc_drv* msc_get_by_drive(int drive_nr) | ||
184 | { | ||
185 | for(int i = 0; i < MSC_COUNT; ++i) | ||
186 | if(msc_drivers[i].drive_nr == drive_nr) | ||
187 | return &msc_drivers[i]; | ||
188 | return NULL; | ||
189 | } | ||
190 | |||
191 | void msc_lock(msc_drv* d) | ||
192 | { | ||
193 | mutex_lock(&d->lock); | ||
194 | } | ||
195 | |||
196 | void msc_unlock(msc_drv* d) | ||
197 | { | ||
198 | mutex_unlock(&d->lock); | ||
199 | } | ||
200 | |||
201 | void msc_full_reset(msc_drv* d) | ||
202 | { | ||
203 | msc_lock(d); | ||
204 | msc_set_clock_mode(d, MSC_CLK_AUTOMATIC); | ||
205 | msc_set_speed(d, MSC_SPEED_INIT); | ||
206 | msc_set_width(d, 1); | ||
207 | msc_ctl_reset(d); | ||
208 | d->driver_flags = 0; | ||
209 | memset(&d->cardinfo, 0, sizeof(tCardInfo)); | ||
210 | msc_unlock(d); | ||
211 | } | ||
212 | |||
213 | bool msc_card_detect(msc_drv* d) | ||
214 | { | ||
215 | if(!d->config->cd_gpio.pin) | ||
216 | return true; | ||
217 | |||
218 | int l = REG_GPIO_PIN(d->config->cd_gpio.port) & d->config->cd_gpio.pin; | ||
219 | l = l ? 1 : 0; | ||
220 | return l == d->config->cd_gpio.active_level; | ||
221 | } | ||
222 | |||
223 | /* --------------------------------------------------------------------------- | ||
224 | * Controller API | ||
225 | */ | ||
226 | |||
227 | void msc_ctl_reset(msc_drv* d) | ||
228 | { | ||
229 | /* Ingenic code suggests a reset changes clkrt */ | ||
230 | int clkrt = REG_MSC_CLKRT(d->msc_nr); | ||
231 | |||
232 | /* Send reset -- bit is NOT self clearing */ | ||
233 | jz_overwritef(MSC_CTRL(d->msc_nr), RESET(1)); | ||
234 | udelay(100); | ||
235 | jz_writef(MSC_CTRL(d->msc_nr), RESET(0)); | ||
236 | |||
237 | /* Verify reset in the status register */ | ||
238 | long deadline = current_tick + HZ; | ||
239 | while(jz_readf(MSC_STAT(d->msc_nr), IS_RESETTING) && | ||
240 | current_tick < deadline) { | ||
241 | sleep(1); | ||
242 | } | ||
243 | |||
244 | /* Ensure the clock state is as expected */ | ||
245 | if(d->clk_status & MSC_CLKST_AUTO) | ||
246 | jz_writef(MSC_LPM(d->msc_nr), ENABLE(1)); | ||
247 | else if(d->clk_status & MSC_CLKST_ENABLE) | ||
248 | jz_overwritef(MSC_CTRL(d->msc_nr), CLOCK_V(START)); | ||
249 | else | ||
250 | jz_overwritef(MSC_CTRL(d->msc_nr), CLOCK_V(STOP)); | ||
251 | |||
252 | /* Clear and mask interrupts */ | ||
253 | REG_MSC_IMASK(d->msc_nr) = 0xffffffff; | ||
254 | REG_MSC_IFLAG(d->msc_nr) = 0xffffffff; | ||
255 | |||
256 | /* Restore clkrt */ | ||
257 | REG_MSC_CLKRT(d->msc_nr) = clkrt; | ||
258 | } | ||
259 | |||
260 | void msc_set_clock_mode(msc_drv* d, int mode) | ||
261 | { | ||
262 | int cur_mode = (d->clk_status & MSC_CLKST_AUTO) ? MSC_CLK_AUTOMATIC | ||
263 | : MSC_CLK_MANUAL; | ||
264 | if(mode == cur_mode) | ||
265 | return; | ||
266 | |||
267 | d->clk_status &= ~MSC_CLKST_ENABLE; | ||
268 | if(mode == MSC_CLK_AUTOMATIC) { | ||
269 | d->clk_status |= MSC_CLKST_AUTO; | ||
270 | jz_writef(MSC_CTRL(d->msc_nr), CLOCK_V(STOP)); | ||
271 | jz_writef(MSC_LPM(d->msc_nr), ENABLE(1)); | ||
272 | } else { | ||
273 | d->clk_status &= ~MSC_CLKST_AUTO; | ||
274 | jz_writef(MSC_LPM(d->msc_nr), ENABLE(0)); | ||
275 | jz_writef(MSC_CTRL(d->msc_nr), CLOCK_V(STOP)); | ||
276 | } | ||
277 | } | ||
278 | |||
279 | void msc_enable_clock(msc_drv* d, bool enable) | ||
280 | { | ||
281 | if(d->clk_status & MSC_CLKST_AUTO) | ||
282 | return; | ||
283 | |||
284 | bool is_enabled = (d->clk_status & MSC_CLKST_ENABLE); | ||
285 | if(enable == is_enabled) | ||
286 | return; | ||
287 | |||
288 | if(enable) { | ||
289 | jz_writef(MSC_CTRL(d->msc_nr), CLOCK_V(START)); | ||
290 | d->clk_status |= MSC_CLKST_ENABLE; | ||
291 | } else { | ||
292 | jz_writef(MSC_CTRL(d->msc_nr), CLOCK_V(STOP)); | ||
293 | d->clk_status &= ~MSC_CLKST_ENABLE; | ||
294 | } | ||
295 | } | ||
296 | |||
297 | void msc_set_speed(msc_drv* d, int rate) | ||
298 | { | ||
299 | /* Shut down clock while we change frequencies */ | ||
300 | if(d->clk_status & MSC_CLKST_ENABLE) | ||
301 | jz_writef(MSC_CTRL(d->msc_nr), CLOCK_V(STOP)); | ||
302 | |||
303 | /* Wait for clock to go idle */ | ||
304 | while(jz_readf(MSC_STAT(d->msc_nr), CLOCK_EN)) | ||
305 | sleep(1); | ||
306 | |||
307 | /* freq1 is output by MSCxDIV; freq2 is output by MSC_CLKRT */ | ||
308 | uint32_t freq1 = rate; | ||
309 | uint32_t freq2 = rate; | ||
310 | if(freq1 < MSC_SPEED_FAST) | ||
311 | freq1 = MSC_SPEED_FAST; | ||
312 | |||
313 | /* Handle MSCxDIV */ | ||
314 | uint32_t src_freq = clk_get(MSC_CLOCK_SOURCE) / 2; | ||
315 | uint32_t div = clk_calc_div(src_freq, freq1); | ||
316 | if(d->msc_nr == 0) { | ||
317 | jz_writef(CPM_MSC0CDR, CE(1), CLKDIV(div - 1)); | ||
318 | while(jz_readf(CPM_MSC0CDR, BUSY)); | ||
319 | jz_writef(CPM_MSC0CDR, CE(0)); | ||
320 | } else { | ||
321 | jz_writef(CPM_MSC1CDR, CE(1), CLKDIV(div - 1)); | ||
322 | while(jz_readf(CPM_MSC1CDR, BUSY)); | ||
323 | jz_writef(CPM_MSC1CDR, CE(0)); | ||
324 | } | ||
325 | |||
326 | /* Handle MSC_CLKRT */ | ||
327 | uint32_t clkrt = clk_calc_shift(src_freq/div, freq2); | ||
328 | REG_MSC_CLKRT(d->msc_nr) = clkrt; | ||
329 | |||
330 | /* Handle frequency dependent timing settings | ||
331 | * TODO - these settings might be SD specific... | ||
332 | */ | ||
333 | uint32_t out_freq = (src_freq/div) >> clkrt; | ||
334 | if(out_freq > MSC_SPEED_FAST) { | ||
335 | jz_writef(MSC_LPM(d->msc_nr), | ||
336 | DRV_SEL_V(RISE_EDGE_DELAY_QTR_PHASE), | ||
337 | SMP_SEL_V(RISE_EDGE_DELAYED)); | ||
338 | } else { | ||
339 | jz_writef(MSC_LPM(d->msc_nr), | ||
340 | DRV_SEL_V(FALL_EDGE), | ||
341 | SMP_SEL_V(RISE_EDGE)); | ||
342 | } | ||
343 | |||
344 | /* Restart clock if it was running before */ | ||
345 | if(d->clk_status & MSC_CLKST_ENABLE) | ||
346 | jz_writef(MSC_CTRL(d->msc_nr), CLOCK_V(START)); | ||
347 | } | ||
348 | |||
349 | void msc_set_width(msc_drv* d, int width) | ||
350 | { | ||
351 | /* Bus width is controlled per command with MSC_CMDAT. */ | ||
352 | if(width == 8) | ||
353 | jz_vwritef(d->cmdat_def, MSC_CMDAT, BUS_WIDTH_V(8BIT)); | ||
354 | else if(width == 4) | ||
355 | jz_vwritef(d->cmdat_def, MSC_CMDAT, BUS_WIDTH_V(4BIT)); | ||
356 | else | ||
357 | jz_vwritef(d->cmdat_def, MSC_CMDAT, BUS_WIDTH_V(1BIT)); | ||
358 | } | ||
359 | |||
360 | /* --------------------------------------------------------------------------- | ||
361 | * Request API | ||
362 | */ | ||
363 | |||
364 | /* Note -- this must only be called with IRQs disabled */ | ||
365 | static void msc_finish_request(msc_drv* d, int status) | ||
366 | { | ||
367 | REG_MSC_IMASK(d->msc_nr) = 0xffffffff; | ||
368 | REG_MSC_IFLAG(d->msc_nr) = 0xffffffff; | ||
369 | if(d->req->flags & MSC_RF_DATA) | ||
370 | jz_writef(MSC_DMAC(d->msc_nr), ENABLE(0)); | ||
371 | |||
372 | d->req->status = status; | ||
373 | d->req_running = 0; | ||
374 | d->iflag_done = 0; | ||
375 | timeout_cancel(&d->cmd_tmo); | ||
376 | semaphore_release(&d->cmd_done); | ||
377 | } | ||
378 | |||
379 | static int msc_req_timeout(struct timeout* tmo) | ||
380 | { | ||
381 | msc_drv* d = (msc_drv*)tmo->data; | ||
382 | msc_async_abort(d, MSC_REQ_LOCKUP); | ||
383 | return 0; | ||
384 | } | ||
385 | |||
386 | void msc_async_start(msc_drv* d, msc_req* r) | ||
387 | { | ||
388 | /* Determined needed cmdat and interrupts */ | ||
389 | unsigned cmdat = d->cmdat_def; | ||
390 | d->iflag_done = jz_orm(MSC_IFLAG, END_CMD_RES); | ||
391 | |||
392 | cmdat |= jz_orf(MSC_CMDAT, RESP_FMT(r->resptype & ~MSC_RESP_BUSY)); | ||
393 | if(r->resptype & MSC_RESP_BUSY) | ||
394 | cmdat |= jz_orm(MSC_CMDAT, BUSY); | ||
395 | |||
396 | if(r->flags & MSC_RF_INIT) | ||
397 | cmdat |= jz_orm(MSC_CMDAT, INIT); | ||
398 | |||
399 | if(r->flags & MSC_RF_DATA) { | ||
400 | cmdat |= jz_orm(MSC_CMDAT, DATA_EN); | ||
401 | if(r->flags & MSC_RF_PROG) | ||
402 | d->iflag_done = jz_orm(MSC_IFLAG, WR_ALL_DONE); | ||
403 | else | ||
404 | d->iflag_done = jz_orm(MSC_IFLAG, DMA_DATA_DONE); | ||
405 | } | ||
406 | |||
407 | if(r->flags & MSC_RF_WRITE) | ||
408 | cmdat |= jz_orm(MSC_CMDAT, WRITE_READ); | ||
409 | |||
410 | if(r->flags & MSC_RF_AUTO_CMD12) | ||
411 | cmdat |= jz_orm(MSC_CMDAT, AUTO_CMD12); | ||
412 | |||
413 | if(r->flags & MSC_RF_ABORT) | ||
414 | cmdat |= jz_orm(MSC_CMDAT, IO_ABORT); | ||
415 | |||
416 | unsigned imask = jz_orm(MSC_IMASK, | ||
417 | CRC_RES_ERROR, CRC_READ_ERROR, CRC_WRITE_ERROR, | ||
418 | TIME_OUT_RES, TIME_OUT_READ, END_CMD_RES); | ||
419 | imask |= d->iflag_done; | ||
420 | |||
421 | /* Program the controller */ | ||
422 | if(r->flags & MSC_RF_DATA) { | ||
423 | REG_MSC_NOB(d->msc_nr) = r->nr_blocks; | ||
424 | REG_MSC_BLKLEN(d->msc_nr) = r->block_len; | ||
425 | } | ||
426 | |||
427 | REG_MSC_CMD(d->msc_nr) = r->command; | ||
428 | REG_MSC_ARG(d->msc_nr) = r->argument; | ||
429 | REG_MSC_CMDAT(d->msc_nr) = cmdat; | ||
430 | |||
431 | REG_MSC_IFLAG(d->msc_nr) = imask; | ||
432 | REG_MSC_IMASK(d->msc_nr) &= ~imask; | ||
433 | |||
434 | if(r->flags & MSC_RF_DATA) { | ||
435 | d->dma_desc.nda = 0; | ||
436 | d->dma_desc.mem = PHYSADDR(r->data); | ||
437 | d->dma_desc.len = r->nr_blocks * r->block_len; | ||
438 | d->dma_desc.cmd = 2; /* ID=0, ENDI=1, LINK=0 */ | ||
439 | commit_dcache_range(&d->dma_desc, sizeof(d->dma_desc)); | ||
440 | |||
441 | if(r->flags & MSC_RF_WRITE) | ||
442 | commit_dcache_range(r->data, d->dma_desc.len); | ||
443 | else | ||
444 | discard_dcache_range(r->data, d->dma_desc.len); | ||
445 | |||
446 | /* TODO - should use MODE_SEL bit? what value of INCR? */ | ||
447 | unsigned long addr_off = ((unsigned long)r->data) & 3; | ||
448 | jz_writef(MSC_DMAC(d->msc_nr), MODE_SEL(0), INCR(0), DMASEL(0), | ||
449 | ALIGN_EN(addr_off != 0 ? 1 : 0), ADDR_OFFSET(addr_off)); | ||
450 | REG_MSC_DMANDA(d->msc_nr) = PHYSADDR(&d->dma_desc); | ||
451 | } | ||
452 | |||
453 | /* Begin processing */ | ||
454 | d->req = r; | ||
455 | d->req_running = 1; | ||
456 | jz_writef(MSC_CTRL(d->msc_nr), START_OP(1)); | ||
457 | if(r->flags & MSC_RF_DATA) | ||
458 | jz_writef(MSC_DMAC(d->msc_nr), ENABLE(1)); | ||
459 | |||
460 | /* TODO: calculate a suitable lower value for the lockup timeout. | ||
461 | * | ||
462 | * The SD spec defines timings based on the number of blocks transferred, | ||
463 | * see sec. 4.6.2 "Read, write, and erase timeout conditions". This should | ||
464 | * reduce the long delays which happen if errors occur. | ||
465 | * | ||
466 | * Also need to check if registers MSC_RDTO / MSC_RESTO are correctly set. | ||
467 | */ | ||
468 | timeout_register(&d->cmd_tmo, msc_req_timeout, 10*HZ, (intptr_t)d); | ||
469 | } | ||
470 | |||
471 | void msc_async_abort(msc_drv* d, int status) | ||
472 | { | ||
473 | int irq = disable_irq_save(); | ||
474 | if(d->req_running) { | ||
475 | logf("msc%d: async abort status:%d", d->msc_nr, status); | ||
476 | msc_finish_request(d, status); | ||
477 | } | ||
478 | |||
479 | restore_irq(irq); | ||
480 | } | ||
481 | |||
482 | int msc_async_wait(msc_drv* d, int timeout) | ||
483 | { | ||
484 | if(semaphore_wait(&d->cmd_done, timeout) == OBJ_WAIT_TIMEDOUT) | ||
485 | return MSC_REQ_INCOMPLETE; | ||
486 | |||
487 | return d->req->status; | ||
488 | } | ||
489 | |||
490 | int msc_request(msc_drv* d, msc_req* r) | ||
491 | { | ||
492 | msc_async_start(d, r); | ||
493 | return msc_async_wait(d, TIMEOUT_BLOCK); | ||
494 | } | ||
495 | |||
496 | /* --------------------------------------------------------------------------- | ||
497 | * Command response handling | ||
498 | */ | ||
499 | |||
500 | static void msc_read_response(msc_drv* d) | ||
501 | { | ||
502 | unsigned res = REG_MSC_RES(d->msc_nr); | ||
503 | unsigned dat; | ||
504 | switch(d->req->resptype) { | ||
505 | case MSC_RESP_R1: | ||
506 | case MSC_RESP_R1B: | ||
507 | case MSC_RESP_R3: | ||
508 | case MSC_RESP_R6: | ||
509 | case MSC_RESP_R7: | ||
510 | dat = res << 24; | ||
511 | res = REG_MSC_RES(d->msc_nr); | ||
512 | dat |= res << 8; | ||
513 | res = REG_MSC_RES(d->msc_nr); | ||
514 | dat |= res & 0xff; | ||
515 | d->req->response[0] = dat; | ||
516 | break; | ||
517 | |||
518 | case MSC_RESP_R2: | ||
519 | for(int i = 0; i < 4; ++i) { | ||
520 | dat = res << 24; | ||
521 | res = REG_MSC_RES(d->msc_nr); | ||
522 | dat |= res << 8; | ||
523 | res = REG_MSC_RES(d->msc_nr); | ||
524 | dat |= res >> 8; | ||
525 | d->req->response[i] = dat; | ||
526 | } | ||
527 | |||
528 | break; | ||
529 | |||
530 | default: | ||
531 | return; | ||
532 | } | ||
533 | } | ||
534 | |||
535 | static int msc_check_sd_response(msc_drv* d) | ||
536 | { | ||
537 | if(d->req->resptype == MSC_RESP_R1 || | ||
538 | d->req->resptype == MSC_RESP_R1B) { | ||
539 | if(d->req->response[0] & SD_R1_CARD_ERROR) { | ||
540 | logf("msc%d: R1 card error: %08x", d->msc_nr, d->req->response[0]); | ||
541 | return MSC_REQ_CARD_ERR; | ||
542 | } | ||
543 | } | ||
544 | |||
545 | return MSC_REQ_SUCCESS; | ||
546 | } | ||
547 | |||
548 | static int msc_check_response(msc_drv* d) | ||
549 | { | ||
550 | switch(d->config->msc_type) { | ||
551 | case MSC_TYPE_SD: | ||
552 | return msc_check_sd_response(d); | ||
553 | default: | ||
554 | /* TODO - implement msc_check_response for MMC and CE-ATA */ | ||
555 | return 0; | ||
556 | } | ||
557 | } | ||
558 | |||
559 | /* --------------------------------------------------------------------------- | ||
560 | * Interrupt handlers | ||
561 | */ | ||
562 | |||
563 | static void msc_interrupt(msc_drv* d) | ||
564 | { | ||
565 | const unsigned tmo_bits = jz_orm(MSC_IFLAG, TIME_OUT_READ, TIME_OUT_RES); | ||
566 | const unsigned crc_bits = jz_orm(MSC_IFLAG, CRC_RES_ERROR, | ||
567 | CRC_READ_ERROR, CRC_WRITE_ERROR); | ||
568 | const unsigned err_bits = tmo_bits | crc_bits; | ||
569 | |||
570 | unsigned iflag = REG_MSC_IFLAG(d->msc_nr) & ~REG_MSC_IMASK(d->msc_nr); | ||
571 | bool handled = false; | ||
572 | |||
573 | /* In case card was removed */ | ||
574 | if(!msc_card_detect(d)) { | ||
575 | msc_finish_request(d, MSC_REQ_EXTRACTED); | ||
576 | return; | ||
577 | } | ||
578 | |||
579 | /* Check for errors */ | ||
580 | if(iflag & err_bits) { | ||
581 | int st; | ||
582 | if(iflag & crc_bits) | ||
583 | st = MSC_REQ_CRC_ERR; | ||
584 | else if(iflag & tmo_bits) | ||
585 | st = MSC_REQ_TIMEOUT; | ||
586 | else | ||
587 | st = MSC_REQ_ERROR; | ||
588 | |||
589 | msc_finish_request(d, st); | ||
590 | return; | ||
591 | } | ||
592 | |||
593 | /* Read and check the command response */ | ||
594 | if(iflag & BM_MSC_IFLAG_END_CMD_RES) { | ||
595 | msc_read_response(d); | ||
596 | int st = msc_check_response(d); | ||
597 | if(st == MSC_REQ_SUCCESS) { | ||
598 | jz_writef(MSC_IMASK(d->msc_nr), END_CMD_RES(1)); | ||
599 | jz_overwritef(MSC_IFLAG(d->msc_nr), END_CMD_RES(1)); | ||
600 | handled = true; | ||
601 | } else { | ||
602 | msc_finish_request(d, st); | ||
603 | return; | ||
604 | } | ||
605 | } | ||
606 | |||
607 | /* Check if the "done" interrupt is signaled */ | ||
608 | if(iflag & d->iflag_done) { | ||
609 | /* Discard after DMA in case of hardware cache prefetching. | ||
610 | * Only needed for read operations. | ||
611 | */ | ||
612 | if((d->req->flags & MSC_RF_DATA) != 0 && | ||
613 | (d->req->flags & MSC_RF_WRITE) == 0) { | ||
614 | discard_dcache_range(d->req->data, | ||
615 | d->req->block_len * d->req->nr_blocks); | ||
616 | } | ||
617 | |||
618 | msc_finish_request(d, MSC_REQ_SUCCESS); | ||
619 | return; | ||
620 | } | ||
621 | |||
622 | if(!handled) { | ||
623 | panicf("msc%d: irq bug! iflag:%08x raw_iflag:%08lx imask:%08lx", | ||
624 | d->msc_nr, iflag, REG_MSC_IFLAG(d->msc_nr), REG_MSC_IMASK(d->msc_nr)); | ||
625 | } | ||
626 | } | ||
627 | |||
628 | static int msc_cd_callback(struct timeout* tmo) | ||
629 | { | ||
630 | msc_drv* d = (msc_drv*)tmo->data; | ||
631 | |||
632 | /* If card is still present we assume the card is properly inserted */ | ||
633 | if(msc_card_detect(d)) { | ||
634 | d->card_present = 1; | ||
635 | queue_broadcast(SYS_HOTSWAP_INSERTED, d->drive_nr); | ||
636 | } | ||
637 | |||
638 | return 0; | ||
639 | } | ||
640 | |||
641 | static void msc_cd_interrupt(msc_drv* d) | ||
642 | { | ||
643 | if(!msc_card_detect(d)) { | ||
644 | /* Immediately abort and notify when removing a card */ | ||
645 | msc_async_abort(d, MSC_REQ_EXTRACTED); | ||
646 | if(d->card_present) { | ||
647 | d->card_present = 0; | ||
648 | queue_broadcast(SYS_HOTSWAP_EXTRACTED, d->drive_nr); | ||
649 | } | ||
650 | } else { | ||
651 | /* Timer to debounce input */ | ||
652 | timeout_register(&d->cd_tmo, msc_cd_callback, HZ/4, (intptr_t)d); | ||
653 | } | ||
654 | |||
655 | /* Invert the IRQ */ | ||
656 | REG_GPIO_PAT0(d->config->cd_gpio.port) ^= d->config->cd_gpio.pin; | ||
657 | } | ||
658 | |||
659 | void MSC0(void) | ||
660 | { | ||
661 | msc_interrupt(&msc_drivers[0]); | ||
662 | } | ||
663 | |||
664 | void MSC1(void) | ||
665 | { | ||
666 | msc_interrupt(&msc_drivers[1]); | ||
667 | } | ||
668 | |||
669 | #ifdef msc0_cd_interrupt | ||
670 | void msc0_cd_interrupt(void) | ||
671 | { | ||
672 | msc_cd_interrupt(&msc_drivers[0]); | ||
673 | } | ||
674 | #endif | ||
675 | |||
676 | #ifdef msc1_cd_interrupt | ||
677 | void msc1_cd_interrupt(void) | ||
678 | { | ||
679 | msc_cd_interrupt(&msc_drivers[1]); | ||
680 | } | ||
681 | #endif | ||
682 | |||
683 | /* --------------------------------------------------------------------------- | ||
684 | * SD command helpers | ||
685 | */ | ||
686 | |||
687 | int msc_cmd_exec(msc_drv* d, msc_req* r) | ||
688 | { | ||
689 | int status = msc_request(d, r); | ||
690 | if(status == MSC_REQ_SUCCESS) | ||
691 | return status; | ||
692 | else if(status == MSC_REQ_LOCKUP || status == MSC_REQ_EXTRACTED) | ||
693 | d->driver_flags |= MSC_DF_ERRSTATE; | ||
694 | else if(r->flags & (MSC_RF_ERR_CMD12|MSC_RF_AUTO_CMD12)) { | ||
695 | /* After an error, the controller does not automatically issue CMD12, | ||
696 | * so we need to send it if it's needed, as required by the SD spec. | ||
697 | */ | ||
698 | msc_req nreq = {0}; | ||
699 | nreq.command = SD_STOP_TRANSMISSION; | ||
700 | nreq.resptype = MSC_RESP_R1B; | ||
701 | nreq.flags = MSC_RF_ABORT; | ||
702 | logf("msc%d: cmd%d error, sending cmd12", d->msc_nr, r->command); | ||
703 | if(msc_cmd_exec(d, &nreq)) | ||
704 | d->driver_flags |= MSC_DF_ERRSTATE; | ||
705 | } | ||
706 | |||
707 | logf("msc%d: err:%d, cmd%d, arg:%x", d->msc_nr, status, | ||
708 | r->command, r->argument); | ||
709 | return status; | ||
710 | } | ||
711 | |||
712 | int msc_app_cmd_exec(msc_drv* d, msc_req* r) | ||
713 | { | ||
714 | msc_req areq = {0}; | ||
715 | areq.command = SD_APP_CMD; | ||
716 | areq.argument = d->cardinfo.rca; | ||
717 | areq.resptype = MSC_RESP_R1; | ||
718 | if(msc_cmd_exec(d, &areq)) | ||
719 | return areq.status; | ||
720 | |||
721 | /* Verify that CMD55 was accepted */ | ||
722 | if((areq.response[0] & (1 << 5)) == 0) | ||
723 | return MSC_REQ_ERROR; | ||
724 | |||
725 | return msc_cmd_exec(d, r); | ||
726 | } | ||
727 | |||
728 | int msc_cmd_go_idle_state(msc_drv* d) | ||
729 | { | ||
730 | msc_req req = {0}; | ||
731 | req.command = SD_GO_IDLE_STATE; | ||
732 | req.resptype = MSC_RESP_NONE; | ||
733 | req.flags = MSC_RF_INIT; | ||
734 | return msc_cmd_exec(d, &req); | ||
735 | } | ||
736 | |||
737 | int msc_cmd_send_if_cond(msc_drv* d) | ||
738 | { | ||
739 | msc_req req = {0}; | ||
740 | req.command = SD_SEND_IF_COND; | ||
741 | req.argument = 0x1aa; | ||
742 | req.resptype = MSC_RESP_R7; | ||
743 | |||
744 | /* TODO - Check if SEND_IF_COND timeout is really an error | ||
745 | * IIRC, this can occur if the card isn't HCS (old cards < 2 GiB). | ||
746 | */ | ||
747 | if(msc_cmd_exec(d, &req)) | ||
748 | return req.status; | ||
749 | |||
750 | /* Set HCS bit if the card responds correctly */ | ||
751 | if((req.response[0] & 0xff) == 0xaa) | ||
752 | d->driver_flags |= MSC_DF_HCS_CARD; | ||
753 | |||
754 | return MSC_REQ_SUCCESS; | ||
755 | } | ||
756 | |||
757 | int msc_cmd_app_op_cond(msc_drv* d) | ||
758 | { | ||
759 | msc_req req = {0}; | ||
760 | req.command = SD_APP_OP_COND; | ||
761 | req.argument = 0x00300000; /* 3.4 - 3.6 V */ | ||
762 | req.resptype = MSC_RESP_R3; | ||
763 | if(d->driver_flags & MSC_DF_HCS_CARD) | ||
764 | req.argument |= (1 << 30); | ||
765 | |||
766 | int timeout = 2 * HZ; | ||
767 | do { | ||
768 | if(msc_app_cmd_exec(d, &req)) | ||
769 | return req.status; | ||
770 | if(req.response[0] & (1 << 31)) | ||
771 | break; | ||
772 | sleep(1); | ||
773 | } while(--timeout > 0); | ||
774 | |||
775 | if(timeout == 0) | ||
776 | return MSC_REQ_TIMEOUT; | ||
777 | |||
778 | return MSC_REQ_SUCCESS; | ||
779 | } | ||
780 | |||
781 | int msc_cmd_all_send_cid(msc_drv* d) | ||
782 | { | ||
783 | msc_req req = {0}; | ||
784 | req.command = SD_ALL_SEND_CID; | ||
785 | req.resptype = MSC_RESP_R2; | ||
786 | if(msc_cmd_exec(d, &req)) | ||
787 | return req.status; | ||
788 | |||
789 | for(int i = 0; i < 4; ++i) | ||
790 | d->cardinfo.cid[i] = req.response[i]; | ||
791 | |||
792 | return MSC_REQ_SUCCESS; | ||
793 | } | ||
794 | |||
795 | int msc_cmd_send_rca(msc_drv* d) | ||
796 | { | ||
797 | msc_req req = {0}; | ||
798 | req.command = SD_SEND_RELATIVE_ADDR; | ||
799 | req.resptype = MSC_RESP_R6; | ||
800 | if(msc_cmd_exec(d, &req)) | ||
801 | return req.status; | ||
802 | |||
803 | d->cardinfo.rca = req.response[0] & 0xffff0000; | ||
804 | return MSC_REQ_SUCCESS; | ||
805 | } | ||
806 | |||
807 | int msc_cmd_send_csd(msc_drv* d) | ||
808 | { | ||
809 | msc_req req = {0}; | ||
810 | req.command = SD_SEND_CSD; | ||
811 | req.argument = d->cardinfo.rca; | ||
812 | req.resptype = MSC_RESP_R2; | ||
813 | if(msc_cmd_exec(d, &req)) | ||
814 | return req.status; | ||
815 | |||
816 | for(int i = 0; i < 4; ++i) | ||
817 | d->cardinfo.csd[i] = req.response[i]; | ||
818 | sd_parse_csd(&d->cardinfo); | ||
819 | |||
820 | if((req.response[0] >> 30) == 1) | ||
821 | d->driver_flags |= MSC_DF_V2_CARD; | ||
822 | |||
823 | return 0; | ||
824 | } | ||
825 | |||
826 | int msc_cmd_select_card(msc_drv* d) | ||
827 | { | ||
828 | msc_req req = {0}; | ||
829 | req.command = SD_SELECT_CARD; | ||
830 | req.argument = d->cardinfo.rca; | ||
831 | req.resptype = MSC_RESP_R1B; | ||
832 | return msc_cmd_exec(d, &req); | ||
833 | } | ||
834 | |||
835 | int msc_cmd_set_bus_width(msc_drv* d, int width) | ||
836 | { | ||
837 | /* TODO - must we check bus width is supported in the cardinfo? */ | ||
838 | msc_req req = {0}; | ||
839 | req.command = SD_SET_BUS_WIDTH; | ||
840 | req.resptype = MSC_RESP_R1; | ||
841 | switch(width) { | ||
842 | case 1: req.argument = 0; break; | ||
843 | case 4: req.argument = 2; break; | ||
844 | default: return MSC_REQ_ERROR; | ||
845 | } | ||
846 | |||
847 | if(msc_app_cmd_exec(d, &req)) | ||
848 | return req.status; | ||
849 | |||
850 | msc_set_width(d, width); | ||
851 | return MSC_REQ_SUCCESS; | ||
852 | } | ||
853 | |||
854 | int msc_cmd_set_clr_card_detect(msc_drv* d, int arg) | ||
855 | { | ||
856 | msc_req req = {0}; | ||
857 | req.command = SD_SET_CLR_CARD_DETECT; | ||
858 | req.argument = arg; | ||
859 | req.resptype = MSC_RESP_R1; | ||
860 | return msc_app_cmd_exec(d, &req); | ||
861 | } | ||
862 | |||
863 | int msc_cmd_switch_freq(msc_drv* d) | ||
864 | { | ||
865 | /* If card doesn't support High Speed, we don't need to send a command */ | ||
866 | if((d->driver_flags & MSC_DF_V2_CARD) == 0) { | ||
867 | msc_set_speed(d, MSC_SPEED_FAST); | ||
868 | return MSC_REQ_SUCCESS; | ||
869 | } | ||
870 | |||
871 | /* Try switching to High Speed (50 MHz) */ | ||
872 | char buffer[64] CACHEALIGN_ATTR; | ||
873 | msc_req req = {0}; | ||
874 | req.command = SD_SWITCH_FUNC; | ||
875 | req.argument = 0x80fffff1; | ||
876 | req.resptype = MSC_RESP_R1; | ||
877 | req.flags = MSC_RF_DATA; | ||
878 | req.data = &buffer[0]; | ||
879 | req.block_len = 64; | ||
880 | req.nr_blocks = 1; | ||
881 | if(msc_cmd_exec(d, &req)) | ||
882 | return req.status; | ||
883 | |||
884 | msc_set_speed(d, MSC_SPEED_HIGH); | ||
885 | return MSC_REQ_SUCCESS; | ||
886 | } | ||
887 | |||
888 | int msc_cmd_send_status(msc_drv* d) | ||
889 | { | ||
890 | msc_req req = {0}; | ||
891 | req.command = SD_SEND_STATUS; | ||
892 | req.argument = d->cardinfo.rca; | ||
893 | req.resptype = MSC_RESP_R1; | ||
894 | return msc_cmd_exec(d, &req); | ||
895 | } | ||
896 | |||
897 | int msc_cmd_set_block_len(msc_drv* d, unsigned len) | ||
898 | { | ||
899 | msc_req req = {0}; | ||
900 | req.command = SD_SET_BLOCKLEN; | ||
901 | req.argument = len; | ||
902 | req.resptype = MSC_RESP_R1; | ||
903 | return msc_cmd_exec(d, &req); | ||
904 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/msc-x1000.h b/firmware/target/mips/ingenic_x1000/msc-x1000.h new file mode 100644 index 0000000000..53a5b301f0 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/msc-x1000.h | |||
@@ -0,0 +1,186 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef __MSC_X1000_H__ | ||
23 | #define __MSC_X1000_H__ | ||
24 | |||
25 | #include "kernel.h" | ||
26 | #include "sdmmc.h" | ||
27 | #include <stdbool.h> | ||
28 | |||
29 | /* Number of MSC controllers */ | ||
30 | #define MSC_COUNT 2 | ||
31 | |||
32 | /* Media types */ | ||
33 | #define MSC_TYPE_SD 0 | ||
34 | #define MSC_TYPE_MMC 1 | ||
35 | #define MSC_TYPE_ATA 2 | ||
36 | #define MSC_TYPE_ANY 3 | ||
37 | |||
38 | /* Clock modes */ | ||
39 | #define MSC_CLK_MANUAL 0 | ||
40 | #define MSC_CLK_AUTOMATIC 1 | ||
41 | |||
42 | /* Clock status bits */ | ||
43 | #define MSC_CLKST_ENABLE (1 << 0) | ||
44 | #define MSC_CLKST_AUTO (1 << 1) | ||
45 | |||
46 | /* Driver flags */ | ||
47 | #define MSC_DF_ERRSTATE (1 << 0) | ||
48 | #define MSC_DF_READY (1 << 1) | ||
49 | #define MSC_DF_HCS_CARD (1 << 2) | ||
50 | #define MSC_DF_V2_CARD (1 << 3) | ||
51 | |||
52 | /* Request status codes */ | ||
53 | #define MSC_REQ_SUCCESS 0 | ||
54 | #define MSC_REQ_CRC_ERR 1 | ||
55 | #define MSC_REQ_CARD_ERR 2 | ||
56 | #define MSC_REQ_TIMEOUT 3 | ||
57 | #define MSC_REQ_EXTRACTED 4 | ||
58 | #define MSC_REQ_LOCKUP 5 | ||
59 | #define MSC_REQ_ERROR 6 | ||
60 | #define MSC_REQ_INCOMPLETE (-1) | ||
61 | |||
62 | /* Response types */ | ||
63 | #define MSC_RESP_NONE 0 | ||
64 | #define MSC_RESP_BUSY (1 << 7) | ||
65 | #define MSC_RESP_R1 1 | ||
66 | #define MSC_RESP_R1B (MSC_RESP_R1|MSC_RESP_BUSY) | ||
67 | #define MSC_RESP_R2 2 | ||
68 | #define MSC_RESP_R3 3 | ||
69 | #define MSC_RESP_R6 6 | ||
70 | #define MSC_RESP_R7 7 | ||
71 | |||
72 | /* Request flags */ | ||
73 | #define MSC_RF_INIT (1 << 0) | ||
74 | #define MSC_RF_ERR_CMD12 (1 << 1) | ||
75 | #define MSC_RF_AUTO_CMD12 (1 << 2) | ||
76 | #define MSC_RF_PROG (1 << 3) | ||
77 | #define MSC_RF_DATA (1 << 4) | ||
78 | #define MSC_RF_WRITE (1 << 5) | ||
79 | #define MSC_RF_ABORT (1 << 6) | ||
80 | |||
81 | /* Clock speeds */ | ||
82 | #define MSC_SPEED_INIT 400000 | ||
83 | #define MSC_SPEED_FAST 25000000 | ||
84 | #define MSC_SPEED_HIGH 50000000 | ||
85 | |||
86 | typedef struct msc_gpio_data { | ||
87 | int port; | ||
88 | int pin; | ||
89 | int active_level; | ||
90 | } msc_gpio_data; | ||
91 | |||
92 | typedef struct msc_config { | ||
93 | int msc_nr; | ||
94 | int msc_type; | ||
95 | int bus_width; | ||
96 | const char* label; | ||
97 | struct msc_gpio_data cd_gpio; | ||
98 | } msc_config; | ||
99 | |||
100 | typedef struct msc_req { | ||
101 | /* Filled by caller */ | ||
102 | int command; | ||
103 | unsigned argument; | ||
104 | int resptype; | ||
105 | int flags; | ||
106 | void* data; | ||
107 | unsigned nr_blocks; | ||
108 | unsigned block_len; | ||
109 | |||
110 | /* Filled by driver */ | ||
111 | volatile unsigned response[4]; | ||
112 | volatile int status; | ||
113 | } msc_req; | ||
114 | |||
115 | struct sd_dma_desc { | ||
116 | unsigned nda; | ||
117 | unsigned mem; | ||
118 | unsigned len; | ||
119 | unsigned cmd; | ||
120 | } __attribute__((aligned(16))); | ||
121 | |||
122 | typedef struct msc_drv { | ||
123 | int msc_nr; | ||
124 | int drive_nr; | ||
125 | const msc_config* config; | ||
126 | |||
127 | int driver_flags; | ||
128 | int clk_status; | ||
129 | unsigned cmdat_def; | ||
130 | msc_req* req; | ||
131 | unsigned iflag_done; | ||
132 | |||
133 | volatile int req_running; | ||
134 | volatile int card_present; | ||
135 | |||
136 | struct mutex lock; | ||
137 | struct semaphore cmd_done; | ||
138 | struct timeout cmd_tmo; | ||
139 | struct timeout cd_tmo; | ||
140 | struct sd_dma_desc dma_desc; | ||
141 | |||
142 | tCardInfo cardinfo; | ||
143 | } msc_drv; | ||
144 | |||
145 | /* Driver initialization, etc */ | ||
146 | extern void msc_init(void); | ||
147 | extern msc_drv* msc_get(int type, int index); | ||
148 | extern msc_drv* msc_get_by_drive(int drive_nr); | ||
149 | |||
150 | extern void msc_lock(msc_drv* d); | ||
151 | extern void msc_unlock(msc_drv* d); | ||
152 | extern void msc_full_reset(msc_drv* d); | ||
153 | extern bool msc_card_detect(msc_drv* d); | ||
154 | |||
155 | /* Controller API */ | ||
156 | extern void msc_ctl_reset(msc_drv* d); | ||
157 | extern void msc_set_clock_mode(msc_drv* d, int mode); | ||
158 | extern void msc_enable_clock(msc_drv* d, bool enable); | ||
159 | extern void msc_set_speed(msc_drv* d, int rate); | ||
160 | extern void msc_set_width(msc_drv* d, int width); | ||
161 | |||
162 | /* Request API */ | ||
163 | extern void msc_async_start(msc_drv* d, msc_req* r); | ||
164 | extern void msc_async_abort(msc_drv* d, int status); | ||
165 | extern int msc_async_wait(msc_drv* d, int timeout); | ||
166 | extern int msc_request(msc_drv* d, msc_req* r); | ||
167 | |||
168 | /* Command helpers; note these are written with SD in mind | ||
169 | * and should be reviewed before using them for MMC / CE-ATA | ||
170 | */ | ||
171 | extern int msc_cmd_exec(msc_drv* d, msc_req* r); | ||
172 | extern int msc_app_cmd_exec(msc_drv* d, msc_req* r); | ||
173 | extern int msc_cmd_go_idle_state(msc_drv* d); | ||
174 | extern int msc_cmd_send_if_cond(msc_drv* d); | ||
175 | extern int msc_cmd_app_op_cond(msc_drv* d); | ||
176 | extern int msc_cmd_all_send_cid(msc_drv* d); | ||
177 | extern int msc_cmd_send_rca(msc_drv* d); | ||
178 | extern int msc_cmd_send_csd(msc_drv* d); | ||
179 | extern int msc_cmd_select_card(msc_drv* d); | ||
180 | extern int msc_cmd_set_bus_width(msc_drv* d, int width); | ||
181 | extern int msc_cmd_set_clr_card_detect(msc_drv* d, int arg); | ||
182 | extern int msc_cmd_switch_freq(msc_drv* d); | ||
183 | extern int msc_cmd_send_status(msc_drv* d); | ||
184 | extern int msc_cmd_set_block_len(msc_drv* d, unsigned len); | ||
185 | |||
186 | #endif /* __MSC_X1000_H__ */ | ||
diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.c b/firmware/target/mips/ingenic_x1000/nand-x1000.c new file mode 100644 index 0000000000..54a1d11d95 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/nand-x1000.c | |||
@@ -0,0 +1,500 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "nand-x1000.h" | ||
23 | #include "nand-target.h" | ||
24 | #include "sfc-x1000.h" | ||
25 | #include "system.h" | ||
26 | #include <string.h> | ||
27 | |||
28 | #if !defined(NAND_MAX_PAGE_SIZE) || \ | ||
29 | !defined(NAND_INIT_SFC_DEV_CONF) || \ | ||
30 | !defined(NAND_INIT_CLOCK_SPEED) | ||
31 | # error "Target needs to specify NAND driver parameters" | ||
32 | #endif | ||
33 | |||
34 | /* Must be at least as big as a cacheline */ | ||
35 | #define NAND_AUX_BUFFER_SIZE CACHEALIGN_SIZE | ||
36 | |||
37 | /* Writes have been enabled */ | ||
38 | #define NAND_DRV_FLAG_WRITEABLE 0x01 | ||
39 | |||
40 | /* Defined by target */ | ||
41 | extern const nand_chip_desc target_nand_chip_descs[]; | ||
42 | |||
43 | /* Globals for the driver | ||
44 | * TODO: get rid of pagebuffer in the SPL to save code size | ||
45 | */ | ||
46 | static unsigned char pagebuffer[NAND_MAX_PAGE_SIZE] CACHEALIGN_ATTR; | ||
47 | static unsigned char auxbuffer[NAND_AUX_BUFFER_SIZE] CACHEALIGN_ATTR; | ||
48 | static nand_drv nand_driver; | ||
49 | |||
50 | static void nand_drv_reset(nand_drv* d) | ||
51 | { | ||
52 | d->chip_ops = NULL; | ||
53 | d->chip_data = NULL; | ||
54 | d->pagebuf = &pagebuffer[0]; | ||
55 | d->auxbuf = &auxbuffer[0]; | ||
56 | d->raw_page_size = 0; | ||
57 | d->flags = 0; | ||
58 | } | ||
59 | |||
60 | /* Driver code */ | ||
61 | int nand_open(void) | ||
62 | { | ||
63 | sfc_init(); | ||
64 | sfc_lock(); | ||
65 | |||
66 | /* Reset driver state */ | ||
67 | nand_drv_reset(&nand_driver); | ||
68 | |||
69 | /* Init hardware */ | ||
70 | sfc_open(); | ||
71 | sfc_set_dev_conf(NAND_INIT_SFC_DEV_CONF); | ||
72 | sfc_set_clock(NAND_CLOCK_SOURCE, NAND_INIT_CLOCK_SPEED); | ||
73 | |||
74 | /* Identify NAND chip */ | ||
75 | int status = 0; | ||
76 | int nandid = nandcmd_read_id(&nand_driver); | ||
77 | if(nandid < 0) { | ||
78 | status = -1; | ||
79 | goto _err; | ||
80 | } | ||
81 | |||
82 | unsigned char mf_id = nandid >> 8; | ||
83 | unsigned char dev_id = nandid & 0xff; | ||
84 | const nand_chip_desc* desc = &target_nand_chip_descs[0]; | ||
85 | while(1) { | ||
86 | if(desc->data == NULL || desc->ops == NULL) { | ||
87 | status = -1; | ||
88 | goto _err; | ||
89 | } | ||
90 | |||
91 | if(desc->data->mf_id == mf_id && desc->data->dev_id == dev_id) | ||
92 | break; | ||
93 | } | ||
94 | |||
95 | /* Fill driver parameters */ | ||
96 | nand_driver.chip_ops = desc->ops; | ||
97 | nand_driver.chip_data = desc->data; | ||
98 | nand_driver.raw_page_size = desc->data->page_size + desc->data->spare_size; | ||
99 | |||
100 | /* Configure hardware and run init op */ | ||
101 | sfc_set_dev_conf(desc->data->dev_conf); | ||
102 | sfc_set_clock(NAND_CLOCK_SOURCE, desc->data->clock_freq); | ||
103 | |||
104 | if(desc->ops->open(&nand_driver) < 0) { | ||
105 | status = -1; | ||
106 | goto _err; | ||
107 | } | ||
108 | |||
109 | _exit: | ||
110 | sfc_unlock(); | ||
111 | return status; | ||
112 | _err: | ||
113 | nand_drv_reset(&nand_driver); | ||
114 | sfc_close(); | ||
115 | goto _exit; | ||
116 | } | ||
117 | |||
118 | void nand_close(void) | ||
119 | { | ||
120 | sfc_lock(); | ||
121 | nand_driver.chip_ops->close(&nand_driver); | ||
122 | nand_drv_reset(&nand_driver); | ||
123 | sfc_close(); | ||
124 | sfc_unlock(); | ||
125 | } | ||
126 | |||
127 | int nand_enable_writes(bool en) | ||
128 | { | ||
129 | sfc_lock(); | ||
130 | |||
131 | int st = nand_driver.chip_ops->set_wp_enable(&nand_driver, en); | ||
132 | if(st >= 0) { | ||
133 | if(en) | ||
134 | nand_driver.flags |= NAND_DRV_FLAG_WRITEABLE; | ||
135 | else | ||
136 | nand_driver.flags &= ~NAND_DRV_FLAG_WRITEABLE; | ||
137 | } | ||
138 | |||
139 | sfc_unlock(); | ||
140 | return st; | ||
141 | } | ||
142 | |||
143 | extern int nand_read_bytes(uint32_t byteaddr, int count, void* buf) | ||
144 | { | ||
145 | if(count <= 0) | ||
146 | return 0; | ||
147 | |||
148 | nand_drv* d = &nand_driver; | ||
149 | uint32_t rowaddr = byteaddr / d->chip_data->page_size; | ||
150 | uint32_t coladdr = byteaddr % d->chip_data->page_size; | ||
151 | unsigned char* dstbuf = (unsigned char*)buf; | ||
152 | int status = 0; | ||
153 | |||
154 | sfc_lock(); | ||
155 | do { | ||
156 | if(d->chip_ops->read_page(d, rowaddr, d->pagebuf) < 0) { | ||
157 | status = -1; | ||
158 | goto _end; | ||
159 | } | ||
160 | |||
161 | if(d->chip_ops->ecc_read(d, d->pagebuf) < 0) { | ||
162 | status = -1; | ||
163 | goto _end; | ||
164 | } | ||
165 | |||
166 | int amount = d->chip_data->page_size - coladdr; | ||
167 | if(amount > count) | ||
168 | amount = count; | ||
169 | |||
170 | memcpy(dstbuf, d->pagebuf, amount); | ||
171 | dstbuf += amount; | ||
172 | count -= amount; | ||
173 | rowaddr += 1; | ||
174 | coladdr = 0; | ||
175 | } while(count > 0); | ||
176 | |||
177 | _end: | ||
178 | sfc_unlock(); | ||
179 | return status; | ||
180 | } | ||
181 | |||
182 | int nand_write_bytes(uint32_t byteaddr, int count, const void* buf) | ||
183 | { | ||
184 | nand_drv* d = &nand_driver; | ||
185 | |||
186 | if((d->flags & NAND_DRV_FLAG_WRITEABLE) == 0) | ||
187 | return -1; | ||
188 | |||
189 | if(count <= 0) | ||
190 | return 0; | ||
191 | |||
192 | uint32_t rowaddr = byteaddr / d->chip_data->page_size; | ||
193 | uint32_t coladdr = byteaddr % d->chip_data->page_size; | ||
194 | |||
195 | /* Only support whole page writes right now */ | ||
196 | if(coladdr != 0) | ||
197 | return -1; | ||
198 | if(count % d->chip_data->page_size) | ||
199 | return -1; | ||
200 | |||
201 | const unsigned char* srcbuf = (const unsigned char*)buf; | ||
202 | int status = 0; | ||
203 | |||
204 | sfc_lock(); | ||
205 | do { | ||
206 | memcpy(d->pagebuf, srcbuf, d->chip_data->page_size); | ||
207 | d->chip_ops->ecc_write(d, d->pagebuf); | ||
208 | |||
209 | if(d->chip_ops->write_page(d, rowaddr, d->pagebuf) < 0) { | ||
210 | status = -1; | ||
211 | goto _end; | ||
212 | } | ||
213 | |||
214 | rowaddr += 1; | ||
215 | srcbuf += d->chip_data->page_size; | ||
216 | count -= d->chip_data->page_size; | ||
217 | } while(count > 0); | ||
218 | |||
219 | _end: | ||
220 | sfc_unlock(); | ||
221 | return status; | ||
222 | } | ||
223 | |||
224 | int nand_erase_block(uint32_t byteaddr) | ||
225 | { | ||
226 | nand_drv* d = &nand_driver; | ||
227 | |||
228 | if((d->flags & NAND_DRV_FLAG_WRITEABLE) == 0) | ||
229 | return -1; | ||
230 | |||
231 | /* Ensure address is aligned to a block boundary */ | ||
232 | uint32_t blockaddr = byteaddr / d->chip_data->page_size; | ||
233 | if(blockaddr % d->chip_data->block_size) | ||
234 | return -1; | ||
235 | |||
236 | int status = 0; | ||
237 | sfc_lock(); | ||
238 | |||
239 | if(d->chip_ops->erase_block(d, blockaddr)) { | ||
240 | status = -1; | ||
241 | goto _end; | ||
242 | } | ||
243 | |||
244 | _end: | ||
245 | sfc_unlock(); | ||
246 | return status; | ||
247 | } | ||
248 | |||
249 | int nandcmd_read_id(nand_drv* d) | ||
250 | { | ||
251 | sfc_op op = {0}; | ||
252 | op.command = NAND_CMD_READ_ID; | ||
253 | op.flags = SFC_FLAG_READ; | ||
254 | op.addr_bytes = 1; | ||
255 | op.addr_lo = 0; | ||
256 | op.data_bytes = 2; | ||
257 | op.buffer = d->auxbuf; | ||
258 | if(sfc_exec(&op)) | ||
259 | return -1; | ||
260 | |||
261 | return (d->auxbuf[0] << 8) | d->auxbuf[1]; | ||
262 | } | ||
263 | |||
264 | int nandcmd_write_enable(nand_drv* d) | ||
265 | { | ||
266 | (void)d; | ||
267 | |||
268 | sfc_op op = {0}; | ||
269 | op.command = NAND_CMD_WRITE_ENABLE; | ||
270 | if(sfc_exec(&op)) | ||
271 | return -1; | ||
272 | |||
273 | return 0; | ||
274 | } | ||
275 | |||
276 | int nandcmd_get_feature(nand_drv* d, int reg) | ||
277 | { | ||
278 | sfc_op op = {0}; | ||
279 | op.command = NAND_CMD_GET_FEATURE; | ||
280 | op.flags = SFC_FLAG_READ; | ||
281 | op.addr_bytes = 1; | ||
282 | op.addr_lo = reg & 0xff; | ||
283 | op.data_bytes = 1; | ||
284 | op.buffer = d->auxbuf; | ||
285 | if(sfc_exec(&op)) | ||
286 | return -1; | ||
287 | |||
288 | return d->auxbuf[0]; | ||
289 | } | ||
290 | |||
291 | int nandcmd_set_feature(nand_drv* d, int reg, int val) | ||
292 | { | ||
293 | sfc_op op = {0}; | ||
294 | op.command = NAND_CMD_SET_FEATURE; | ||
295 | op.flags = SFC_FLAG_READ; | ||
296 | op.addr_bytes = 1; | ||
297 | op.addr_lo = reg & 0xff; | ||
298 | op.data_bytes = 1; | ||
299 | op.buffer = d->auxbuf; | ||
300 | d->auxbuf[0] = val & 0xff; | ||
301 | if(sfc_exec(&op)) | ||
302 | return -1; | ||
303 | |||
304 | return 0; | ||
305 | } | ||
306 | |||
307 | int nandcmd_page_read_to_cache(nand_drv* d, uint32_t rowaddr) | ||
308 | { | ||
309 | sfc_op op = {0}; | ||
310 | op.command = NAND_CMD_PAGE_READ_TO_CACHE; | ||
311 | op.addr_bytes = d->chip_data->rowaddr_width; | ||
312 | op.addr_lo = rowaddr; | ||
313 | if(sfc_exec(&op)) | ||
314 | return -1; | ||
315 | |||
316 | return 0; | ||
317 | } | ||
318 | |||
319 | int nandcmd_read_from_cache(nand_drv* d, unsigned char* buf) | ||
320 | { | ||
321 | sfc_op op = {0}; | ||
322 | if(d->chip_data->flags & NANDCHIP_FLAG_QUAD) { | ||
323 | op.command = NAND_CMD_READ_FROM_CACHEx4; | ||
324 | op.mode = SFC_MODE_QUAD_IO; | ||
325 | } else { | ||
326 | op.command = NAND_CMD_READ_FROM_CACHE; | ||
327 | op.mode = SFC_MODE_STANDARD; | ||
328 | } | ||
329 | |||
330 | op.flags = SFC_FLAG_READ; | ||
331 | op.addr_bytes = d->chip_data->coladdr_width; | ||
332 | op.addr_lo = 0; | ||
333 | op.dummy_bits = 8; | ||
334 | op.data_bytes = d->raw_page_size; | ||
335 | op.buffer = buf; | ||
336 | if(sfc_exec(&op)) | ||
337 | return -1; | ||
338 | |||
339 | return 0; | ||
340 | } | ||
341 | |||
342 | int nandcmd_program_load(nand_drv* d, const unsigned char* buf) | ||
343 | { | ||
344 | sfc_op op = {0}; | ||
345 | if(d->chip_data->flags & NANDCHIP_FLAG_QUAD) { | ||
346 | op.command = NAND_CMD_PROGRAM_LOADx4; | ||
347 | op.mode = SFC_MODE_QUAD_IO; | ||
348 | } else { | ||
349 | op.command = NAND_CMD_PROGRAM_LOAD; | ||
350 | op.mode = SFC_MODE_STANDARD; | ||
351 | } | ||
352 | |||
353 | op.flags = SFC_FLAG_WRITE; | ||
354 | op.addr_bytes = d->chip_data->coladdr_width; | ||
355 | op.addr_lo = 0; | ||
356 | op.data_bytes = d->raw_page_size; | ||
357 | op.buffer = (void*)buf; | ||
358 | if(sfc_exec(&op)) | ||
359 | return -1; | ||
360 | |||
361 | return 0; | ||
362 | } | ||
363 | |||
364 | int nandcmd_program_execute(nand_drv* d, uint32_t rowaddr) | ||
365 | { | ||
366 | sfc_op op = {0}; | ||
367 | op.command = NAND_CMD_PROGRAM_EXECUTE; | ||
368 | op.addr_bytes = d->chip_data->rowaddr_width; | ||
369 | op.addr_lo = rowaddr; | ||
370 | if(sfc_exec(&op)) | ||
371 | return -1; | ||
372 | |||
373 | return 0; | ||
374 | } | ||
375 | |||
376 | int nandcmd_block_erase(nand_drv* d, uint32_t blockaddr) | ||
377 | { | ||
378 | sfc_op op = {0}; | ||
379 | op.command = NAND_CMD_BLOCK_ERASE; | ||
380 | op.addr_bytes = d->chip_data->rowaddr_width; | ||
381 | op.addr_lo = blockaddr; | ||
382 | if(sfc_exec(&op)) | ||
383 | return 01; | ||
384 | |||
385 | return 0; | ||
386 | } | ||
387 | |||
388 | const nand_chip_ops nand_chip_ops_std = { | ||
389 | .open = nandop_std_open, | ||
390 | .close = nandop_std_close, | ||
391 | .read_page = nandop_std_read_page, | ||
392 | .write_page = nandop_std_write_page, | ||
393 | .erase_block = nandop_std_erase_block, | ||
394 | .set_wp_enable = nandop_std_set_wp_enable, | ||
395 | .ecc_read = nandop_ecc_none_read, | ||
396 | .ecc_write = nandop_ecc_none_write, | ||
397 | }; | ||
398 | |||
399 | /* Helper needed by other ops */ | ||
400 | static int nandop_std_wait_status(nand_drv* d, int errbit) | ||
401 | { | ||
402 | int reg; | ||
403 | do { | ||
404 | reg = nandcmd_get_feature(d, NAND_FREG_STATUS); | ||
405 | if(reg < 0) | ||
406 | return -1; | ||
407 | } while(reg & NAND_FREG_STATUS_OIP); | ||
408 | |||
409 | if(reg & errbit) | ||
410 | return -1; | ||
411 | |||
412 | return reg; | ||
413 | } | ||
414 | |||
415 | int nandop_std_open(nand_drv* d) | ||
416 | { | ||
417 | (void)d; | ||
418 | return 0; | ||
419 | } | ||
420 | |||
421 | void nandop_std_close(nand_drv* d) | ||
422 | { | ||
423 | (void)d; | ||
424 | } | ||
425 | |||
426 | int nandop_std_read_page(nand_drv* d, uint32_t rowaddr, unsigned char* buf) | ||
427 | { | ||
428 | if(nandcmd_page_read_to_cache(d, rowaddr) < 0) | ||
429 | return -1; | ||
430 | if(nandop_std_wait_status(d, 0) < 0) | ||
431 | return -1; | ||
432 | if(nandcmd_read_from_cache(d, buf) < 0) | ||
433 | return -1; | ||
434 | |||
435 | return 0; | ||
436 | } | ||
437 | |||
438 | int nandop_std_write_page(nand_drv* d, uint32_t rowaddr, const unsigned char* buf) | ||
439 | { | ||
440 | if(nandcmd_write_enable(d) < 0) | ||
441 | return -1; | ||
442 | if(nandcmd_program_load(d, buf) < 0) | ||
443 | return -1; | ||
444 | if(nandcmd_program_execute(d, rowaddr) < 0) | ||
445 | return -1; | ||
446 | if(nandop_std_wait_status(d, NAND_FREG_STATUS_P_FAIL) < 0) | ||
447 | return -1; | ||
448 | |||
449 | return 0; | ||
450 | } | ||
451 | |||
452 | int nandop_std_erase_block(nand_drv* d, uint32_t blockaddr) | ||
453 | { | ||
454 | if(nandcmd_write_enable(d) < 0) | ||
455 | return -1; | ||
456 | if(nandcmd_block_erase(d, blockaddr) < 0) | ||
457 | return -1; | ||
458 | if(nandop_std_wait_status(d, NAND_FREG_STATUS_E_FAIL) < 0) | ||
459 | return -1; | ||
460 | |||
461 | return 0; | ||
462 | } | ||
463 | |||
464 | int nandop_std_set_wp_enable(nand_drv* d, bool en) | ||
465 | { | ||
466 | int val = nandcmd_get_feature(d, NAND_FREG_PROTECTION); | ||
467 | if(val < 0) | ||
468 | return -1; | ||
469 | |||
470 | if(en) { | ||
471 | val &= ~NAND_FREG_PROTECTION_ALLBP; | ||
472 | if(d->chip_data->flags & NANDCHIP_FLAG_USE_BRWD) | ||
473 | val &= ~NAND_FREG_PROTECTION_BRWD; | ||
474 | } else { | ||
475 | val |= NAND_FREG_PROTECTION_ALLBP; | ||
476 | if(d->chip_data->flags & NANDCHIP_FLAG_USE_BRWD) | ||
477 | val |= NAND_FREG_PROTECTION_BRWD; | ||
478 | } | ||
479 | |||
480 | sfc_set_wp_enable(false); | ||
481 | int status = nandcmd_set_feature(d, NAND_FREG_PROTECTION, val); | ||
482 | sfc_set_wp_enable(true); | ||
483 | |||
484 | if(status < 0) | ||
485 | return -1; | ||
486 | |||
487 | return 0; | ||
488 | } | ||
489 | |||
490 | int nandop_ecc_none_read(nand_drv* d, unsigned char* buf) | ||
491 | { | ||
492 | (void)d; | ||
493 | (void)buf; | ||
494 | return 0; | ||
495 | } | ||
496 | |||
497 | void nandop_ecc_none_write(nand_drv* d, unsigned char* buf) | ||
498 | { | ||
499 | memset(&buf[d->chip_data->page_size], 0xff, d->chip_data->spare_size); | ||
500 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.h b/firmware/target/mips/ingenic_x1000/nand-x1000.h new file mode 100644 index 0000000000..865feb38c5 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/nand-x1000.h | |||
@@ -0,0 +1,213 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef __NAND_X1000_H__ | ||
23 | #define __NAND_X1000_H__ | ||
24 | |||
25 | /* NOTE: this is a very minimal API designed only to support a bootloader. | ||
26 | * Not suitable for general data storage. It doesn't have proper support for | ||
27 | * partial page writes, access to spare area, etc, which are all necessary | ||
28 | * for an effective flash translation layer. | ||
29 | */ | ||
30 | |||
31 | #include <stdint.h> | ||
32 | #include <stdbool.h> | ||
33 | #include <stddef.h> | ||
34 | |||
35 | /* Chip supports quad I/O for page read/write */ | ||
36 | #define NANDCHIP_FLAG_QUAD 0x01 | ||
37 | |||
38 | /* Set/clear the BRWD bit when enabling/disabling write protection */ | ||
39 | #define NANDCHIP_FLAG_USE_BRWD 0x02 | ||
40 | |||
41 | typedef struct nand_drv nand_drv; | ||
42 | |||
43 | /* Defines some static information about a NAND chip */ | ||
44 | typedef struct nand_chip_data { | ||
45 | const char* name; /* Name for debugging purposes */ | ||
46 | uint8_t mf_id; /* Manufacturer ID */ | ||
47 | uint8_t dev_id; /* Device ID */ | ||
48 | uint8_t rowaddr_width; /* Number of bytes in row addresses */ | ||
49 | uint8_t coladdr_width; /* Number of bytes in column addresses */ | ||
50 | uint32_t dev_conf; /* Value to write to SFC_DEV_CONF register */ | ||
51 | uint32_t clock_freq; /* Frequency to switch to after identification */ | ||
52 | uint32_t block_size; /* Number of pages per eraseblock */ | ||
53 | uint32_t page_size; /* Number of data bytes per page */ | ||
54 | uint32_t spare_size; /* Number of spare bytes per page */ | ||
55 | int flags; /* Various flags */ | ||
56 | } nand_chip_data; | ||
57 | |||
58 | /* Defines high-level operations used to implement the public API. | ||
59 | * Chips may need to override operations if the default ones aren't suitable. | ||
60 | * | ||
61 | * Negative return codes return an error, while zero or positive codes are | ||
62 | * considered successful. This allows a function to return meaningful data, | ||
63 | * if applicable. | ||
64 | */ | ||
65 | typedef struct nand_chip_ops { | ||
66 | /* Called once after identifying the chip */ | ||
67 | int(*open)(nand_drv* d); | ||
68 | |||
69 | /* Called once when the driver is closed */ | ||
70 | void(*close)(nand_drv* d); | ||
71 | |||
72 | /* Read or write a complete page including both main and spare areas. */ | ||
73 | int(*read_page)(nand_drv* d, uint32_t rowaddr, unsigned char* buf); | ||
74 | int(*write_page)(nand_drv* d, uint32_t rowaddr, const unsigned char* buf); | ||
75 | |||
76 | /* Erase a block. */ | ||
77 | int(*erase_block)(nand_drv* d, uint32_t blockaddr); | ||
78 | |||
79 | /* Enable or disable the chip's write protection. */ | ||
80 | int(*set_wp_enable)(nand_drv* d, bool en); | ||
81 | |||
82 | /* Perform error correction and detection on a raw page (main + spare). | ||
83 | * Return the number of errors detected and corrected, or a negative value | ||
84 | * if errors were detected but could not be corrected. | ||
85 | */ | ||
86 | int(*ecc_read)(nand_drv* d, unsigned char* buf); | ||
87 | |||
88 | /* Generate ECC data for a page. The buffer main area is already filled | ||
89 | * and this function should write ECC data into the spare area. | ||
90 | */ | ||
91 | void(*ecc_write)(nand_drv* d, unsigned char* buf); | ||
92 | } nand_chip_ops; | ||
93 | |||
94 | /* Struct used to list all supported NAND chips in an array */ | ||
95 | typedef struct nand_chip_desc { | ||
96 | const nand_chip_data* data; | ||
97 | const nand_chip_ops* ops; | ||
98 | } nand_chip_desc; | ||
99 | |||
100 | /* NAND driver structure. It can be accessed by chip ops, but they must not | ||
101 | * modify any fields except for "auxbuf", which is a small buffer that can | ||
102 | * be used for commands that need to read/write small amounts of data: often | ||
103 | * needed for polling status, etc. | ||
104 | */ | ||
105 | struct nand_drv { | ||
106 | const nand_chip_ops* chip_ops; | ||
107 | const nand_chip_data* chip_data; | ||
108 | unsigned char* pagebuf; | ||
109 | unsigned char* auxbuf; | ||
110 | uint32_t raw_page_size; | ||
111 | int flags; | ||
112 | }; | ||
113 | |||
114 | /* Note: sfc_init() must be called prior to nand_open() */ | ||
115 | extern int nand_open(void); | ||
116 | extern void nand_close(void); | ||
117 | |||
118 | /* Controls device-side write protection registers as well as software lock. | ||
119 | * Erase and program operations will fail unless you first enable writes. | ||
120 | */ | ||
121 | extern int nand_enable_writes(bool en); | ||
122 | |||
123 | /* Byte-based NAND operations */ | ||
124 | extern int nand_read_bytes(uint32_t byteaddr, int count, void* buf); | ||
125 | extern int nand_write_bytes(uint32_t byteaddr, int count, const void* buf); | ||
126 | extern int nand_erase_block(uint32_t byteaddr); | ||
127 | |||
128 | /* NAND command numbers */ | ||
129 | #define NAND_CMD_READ_ID 0x9f | ||
130 | #define NAND_CMD_WRITE_ENABLE 0x06 | ||
131 | #define NAND_CMD_GET_FEATURE 0x0f | ||
132 | #define NAND_CMD_SET_FEATURE 0x1f | ||
133 | #define NAND_CMD_PAGE_READ_TO_CACHE 0x13 | ||
134 | #define NAND_CMD_READ_FROM_CACHE 0x0b | ||
135 | #define NAND_CMD_READ_FROM_CACHEx4 0x6b | ||
136 | #define NAND_CMD_PROGRAM_LOAD 0x02 | ||
137 | #define NAND_CMD_PROGRAM_LOADx4 0x32 | ||
138 | #define NAND_CMD_PROGRAM_EXECUTE 0x10 | ||
139 | #define NAND_CMD_BLOCK_ERASE 0xd8 | ||
140 | |||
141 | /* NAND device register addresses for GET_FEATURE / SET_FEATURE */ | ||
142 | #define NAND_FREG_PROTECTION 0xa0 | ||
143 | #define NAND_FREG_FEATURE 0xb0 | ||
144 | #define NAND_FREG_STATUS 0xc0 | ||
145 | |||
146 | /* Protection register bits */ | ||
147 | #define NAND_FREG_PROTECTION_BRWD 0x80 | ||
148 | #define NAND_FREG_PROTECTION_BP2 0x20 | ||
149 | #define NAND_FREG_PROTECTION_BP1 0x10 | ||
150 | #define NAND_FREG_PROTECTION_BP0 0x80 | ||
151 | /* Mask of BP bits 0-2 */ | ||
152 | #define NAND_FREG_PROTECTION_ALLBP (0x38) | ||
153 | |||
154 | /* Feature register bits */ | ||
155 | #define NAND_FREG_FEATURE_QE 0x01 | ||
156 | |||
157 | /* Status register bits */ | ||
158 | #define NAND_FREG_STATUS_OIP 0x01 | ||
159 | #define NAND_FREG_STATUS_WEL 0x02 | ||
160 | #define NAND_FREG_STATUS_E_FAIL 0x04 | ||
161 | #define NAND_FREG_STATUS_P_FAIL 0x08 | ||
162 | |||
163 | /* Standard implementations for low-level NAND commands. I'm not aware of any | ||
164 | * actual standard governing these, but it seems many vendors follow the same | ||
165 | * command numbering, status bits, and behavior so these implementations should | ||
166 | * work across a wide variety of chips. | ||
167 | * | ||
168 | * If adding a new NAND chip which only has a minor deviation from these | ||
169 | * standard implementations, consider adding a flag and modifying these | ||
170 | * functions to change their behavior based on the flag, instead of writing | ||
171 | * a whole new implementation. | ||
172 | * | ||
173 | * None of these functions are directly called by the high-level driver code, | ||
174 | * except for nandcmd_std_read_id(). They can be used to implement higher-level | ||
175 | * functions in a device's "nand_chip_ops". | ||
176 | */ | ||
177 | extern int nandcmd_read_id(nand_drv* d); | ||
178 | extern int nandcmd_write_enable(nand_drv* d); | ||
179 | extern int nandcmd_get_feature(nand_drv* d, int reg); | ||
180 | extern int nandcmd_set_feature(nand_drv* d, int reg, int val); | ||
181 | extern int nandcmd_page_read_to_cache(nand_drv* d, uint32_t rowaddr); | ||
182 | extern int nandcmd_read_from_cache(nand_drv* d, unsigned char* buf); | ||
183 | extern int nandcmd_program_load(nand_drv* d, const unsigned char* buf); | ||
184 | extern int nandcmd_program_execute(nand_drv* d, uint32_t rowaddr); | ||
185 | extern int nandcmd_block_erase(nand_drv* d, uint32_t blockaddr); | ||
186 | |||
187 | /* Table filled with all the standard operations for chips which don't | ||
188 | * need to override any operations. | ||
189 | */ | ||
190 | extern const nand_chip_ops nand_chip_ops_std; | ||
191 | |||
192 | /* Standard NAND chip ops based on the standard "nandcmd" functions. | ||
193 | * | ||
194 | * Same advice applies here as there: if it's possible to support minor | ||
195 | * chip variations with a flag, modify these functions to do so. | ||
196 | */ | ||
197 | extern int nandop_std_open(nand_drv* d); | ||
198 | extern void nandop_std_close(nand_drv* d); | ||
199 | extern int nandop_std_read_page(nand_drv* d, uint32_t rowaddr, unsigned char* buf); | ||
200 | extern int nandop_std_write_page(nand_drv* d, uint32_t rowaddr, const unsigned char* buf); | ||
201 | extern int nandop_std_erase_block(nand_drv* d, uint32_t blockaddr); | ||
202 | extern int nandop_std_set_wp_enable(nand_drv* d, bool en); | ||
203 | |||
204 | /* The default ECC implementation is a no-op: reads always succeed without | ||
205 | * reporting errors and writes will fill the spare area with '0xff' bytes. | ||
206 | * | ||
207 | * For chips that support internal ECC, this often works because the chip will | ||
208 | * ignore writes to the ECC areas. | ||
209 | */ | ||
210 | extern int nandop_ecc_none_read(nand_drv* d, unsigned char* buf); | ||
211 | extern void nandop_ecc_none_write(nand_drv* d, unsigned char* buf); | ||
212 | |||
213 | #endif /* __NAND_X1000_H__ */ | ||
diff --git a/firmware/target/mips/ingenic_x1000/pcm-x1000.c b/firmware/target/mips/ingenic_x1000/pcm-x1000.c new file mode 100644 index 0000000000..9ae6f5a956 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/pcm-x1000.c | |||
@@ -0,0 +1,165 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "system.h" | ||
23 | #include "kernel.h" | ||
24 | #include "audiohw.h" | ||
25 | #include "pcm.h" | ||
26 | #include "pcm-internal.h" | ||
27 | #include "panic.h" | ||
28 | #include "dma-x1000.h" | ||
29 | #include "irq-x1000.h" | ||
30 | #include "x1000/aic.h" | ||
31 | |||
32 | #define AIC_STATE_STOPPED 0 | ||
33 | #define AIC_STATE_PLAYING 1 | ||
34 | |||
35 | volatile unsigned aic_tx_underruns = 0; | ||
36 | |||
37 | static int aic_state = AIC_STATE_STOPPED; | ||
38 | |||
39 | static int aic_lock = 0; | ||
40 | static volatile int aic_dma_pending_event = DMA_EVENT_NONE; | ||
41 | |||
42 | static dma_desc aic_dma_desc; | ||
43 | |||
44 | static void pcm_dma_int_cb(int event); | ||
45 | |||
46 | void pcm_play_dma_init(void) | ||
47 | { | ||
48 | /* Let the target initialize its hardware and setup the AIC */ | ||
49 | audiohw_init(); | ||
50 | |||
51 | /* Set DMA callback */ | ||
52 | dma_set_callback(DMA_CHANNEL_AUDIO, pcm_dma_int_cb); | ||
53 | |||
54 | /* Program FIFO threshold -- DMA settings must match */ | ||
55 | jz_writef(AIC_CFG, TFTH(16)); | ||
56 | |||
57 | /* Ensure all playback is disabled */ | ||
58 | jz_writef(AIC_CCR, ERPL(0)); | ||
59 | |||
60 | /* Enable the controller */ | ||
61 | jz_writef(AIC_CFG, ENABLE(1)); | ||
62 | |||
63 | /* Enable interrupts */ | ||
64 | system_enable_irq(IRQ_AIC); | ||
65 | } | ||
66 | |||
67 | void pcm_play_dma_postinit(void) | ||
68 | { | ||
69 | audiohw_postinit(); | ||
70 | } | ||
71 | |||
72 | void pcm_dma_apply_settings(void) | ||
73 | { | ||
74 | audiohw_set_frequency(pcm_fsel); | ||
75 | } | ||
76 | |||
77 | static void pcm_dma_start(const void* addr, size_t size) | ||
78 | { | ||
79 | aic_dma_desc.cm = jz_orf(DMA_CHN_CM, SAI(1), DAI(0), RDIL(9), | ||
80 | SP_V(32BIT), DP_V(32BIT), TSZ_V(AUTO), | ||
81 | STDE(0), TIE(1), LINK(0)); | ||
82 | aic_dma_desc.sa = PHYSADDR(addr); | ||
83 | aic_dma_desc.ta = PHYSADDR(JA_AIC_DR); | ||
84 | aic_dma_desc.tc = size; | ||
85 | aic_dma_desc.sd = 0; | ||
86 | aic_dma_desc.rt = jz_orf(DMA_CHN_RT, TYPE_V(I2S_TX)); | ||
87 | aic_dma_desc.pad0 = 0; | ||
88 | aic_dma_desc.pad1 = 0; | ||
89 | |||
90 | commit_dcache_range(&aic_dma_desc, sizeof(dma_desc)); | ||
91 | commit_dcache_range(addr, size); | ||
92 | |||
93 | REG_DMA_CHN_DA(DMA_CHANNEL_AUDIO) = PHYSADDR(&aic_dma_desc); | ||
94 | jz_writef(DMA_CHN_CS(DMA_CHANNEL_AUDIO), DES8(1), NDES(0)); | ||
95 | jz_set(DMA_DB, 1 << DMA_CHANNEL_AUDIO); | ||
96 | jz_writef(DMA_CHN_CS(DMA_CHANNEL_AUDIO), CTE(1)); | ||
97 | |||
98 | pcm_play_dma_status_callback(PCM_DMAST_STARTED); | ||
99 | } | ||
100 | |||
101 | static void pcm_dma_handle_event(int event) | ||
102 | { | ||
103 | if(event == DMA_EVENT_COMPLETE) { | ||
104 | const void* addr; | ||
105 | size_t size; | ||
106 | if(pcm_play_dma_complete_callback(PCM_DMAST_OK, &addr, &size)) | ||
107 | pcm_dma_start(addr, size); | ||
108 | } else if(event == DMA_EVENT_NONE) { | ||
109 | /* ignored, so callers don't need to check for this */ | ||
110 | } else { | ||
111 | pcm_play_dma_status_callback(PCM_DMAST_ERR_DMA); | ||
112 | } | ||
113 | } | ||
114 | |||
115 | static void pcm_dma_int_cb(int event) | ||
116 | { | ||
117 | if(aic_lock) { | ||
118 | aic_dma_pending_event = event; | ||
119 | return; | ||
120 | } else { | ||
121 | pcm_dma_handle_event(event); | ||
122 | } | ||
123 | } | ||
124 | |||
125 | void pcm_play_dma_start(const void* addr, size_t size) | ||
126 | { | ||
127 | aic_dma_pending_event = DMA_EVENT_NONE; | ||
128 | aic_state = AIC_STATE_PLAYING; | ||
129 | |||
130 | pcm_dma_start(addr, size); | ||
131 | jz_writef(AIC_CCR, TDMS(1), ETUR(1), ERPL(1)); | ||
132 | } | ||
133 | |||
134 | void pcm_play_dma_stop(void) | ||
135 | { | ||
136 | jz_writef(AIC_CCR, TDMS(0), ETUR(0), ERPL(0)); | ||
137 | jz_writef(AIC_CCR, TFLUSH(1)); | ||
138 | |||
139 | aic_dma_pending_event = DMA_EVENT_NONE; | ||
140 | aic_state = AIC_STATE_STOPPED; | ||
141 | } | ||
142 | |||
143 | void pcm_play_lock(void) | ||
144 | { | ||
145 | ++aic_lock; | ||
146 | } | ||
147 | |||
148 | void pcm_play_unlock(void) | ||
149 | { | ||
150 | int irq = disable_irq_save(); | ||
151 | if(--aic_lock == 0 && aic_state == AIC_STATE_PLAYING) { | ||
152 | pcm_dma_handle_event(aic_dma_pending_event); | ||
153 | aic_dma_pending_event = DMA_EVENT_NONE; | ||
154 | } | ||
155 | |||
156 | restore_irq(irq); | ||
157 | } | ||
158 | |||
159 | void AIC(void) | ||
160 | { | ||
161 | if(jz_readf(AIC_SR, TUR)) { | ||
162 | aic_tx_underruns += 1; | ||
163 | jz_writef(AIC_SR, TUR(0)); | ||
164 | } | ||
165 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/pwm-x1000.c b/firmware/target/mips/ingenic_x1000/pwm-x1000.c new file mode 100644 index 0000000000..37d2856c1a --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/pwm-x1000.c | |||
@@ -0,0 +1,170 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "pwm-x1000.h" | ||
23 | #include "clk-x1000.h" | ||
24 | #include "gpio-x1000.h" | ||
25 | #include "system.h" | ||
26 | #include "kernel.h" | ||
27 | #include "x1000/tcu.h" | ||
28 | |||
29 | struct pwm_gpio_data { | ||
30 | int port; | ||
31 | unsigned pin; | ||
32 | int func; | ||
33 | }; | ||
34 | |||
35 | struct pwm_state { | ||
36 | struct pwm_gpio_data gpio; | ||
37 | int period_ns; | ||
38 | int duty_ns; | ||
39 | int full_ticks; | ||
40 | int half_ticks; | ||
41 | int prescaler; | ||
42 | }; | ||
43 | |||
44 | static struct pwm_state pwm_state[] = { | ||
45 | {{GPIO_C, 1 << 25, GPIO_DEVICE(0)}, -1, -1, -1, -1, -1}, | ||
46 | {{GPIO_C, 1 << 26, GPIO_DEVICE(1)}, -1, -1, -1, -1, -1}, | ||
47 | {{GPIO_C, 1 << 27, GPIO_DEVICE(1)}, -1, -1, -1, -1, -1}, | ||
48 | {{GPIO_B, 1 << 6, GPIO_DEVICE(2)}, -1, -1, -1, -1, -1}, | ||
49 | {{GPIO_C, 1 << 24, GPIO_DEVICE(0)}, -1, -1, -1, -1, -1}, | ||
50 | }; | ||
51 | |||
52 | void pwm_init(int chn) | ||
53 | { | ||
54 | /* clear cached state */ | ||
55 | struct pwm_state* st = &pwm_state[chn]; | ||
56 | st->period_ns = -1; | ||
57 | st->duty_ns = -1; | ||
58 | st->full_ticks = -1; | ||
59 | st->prescaler = -1; | ||
60 | st->prescaler = -1; | ||
61 | |||
62 | /* clear GPIO and disable timer */ | ||
63 | gpio_config(st->gpio.port, st->gpio.pin, GPIO_OUTPUT(0)); | ||
64 | jz_clr(TCU_STOP, 1 << chn); | ||
65 | jz_clr(TCU_ENABLE, 1 << chn); | ||
66 | jz_set(TCU_STOP, 1 << chn); | ||
67 | } | ||
68 | |||
69 | void pwm_set_period(int chn, int period_ns, int duty_ns) | ||
70 | { | ||
71 | struct pwm_state* st = &pwm_state[chn]; | ||
72 | unsigned long long tmp; | ||
73 | int full_ticks = st->full_ticks; | ||
74 | int half_ticks = st->half_ticks; | ||
75 | int prescaler = st->prescaler; | ||
76 | |||
77 | if(period_ns != st->period_ns) { | ||
78 | /* calculate full tick period and prescaler */ | ||
79 | tmp = clk_get(X1000_CLK_PCLK) / 1000000; | ||
80 | tmp *= period_ns; | ||
81 | tmp /= 1000; | ||
82 | |||
83 | prescaler = 0; | ||
84 | while(tmp > 0xffff && prescaler < 5) { | ||
85 | tmp /= 4; | ||
86 | prescaler += 1; | ||
87 | } | ||
88 | |||
89 | full_ticks = (tmp > 0xffff) ? 0xffff : tmp; | ||
90 | st->period_ns = period_ns; | ||
91 | } | ||
92 | |||
93 | if(duty_ns != st->duty_ns) { | ||
94 | /* calculate half tick value */ | ||
95 | tmp = full_ticks; | ||
96 | tmp *= duty_ns; | ||
97 | tmp /= period_ns; | ||
98 | |||
99 | half_ticks = (tmp > 0xffff) ? 0xffff : tmp; | ||
100 | if(half_ticks >= full_ticks) | ||
101 | half_ticks = full_ticks - 1; | ||
102 | st->duty_ns = duty_ns; | ||
103 | } | ||
104 | |||
105 | /* need to clear STOP bit to access timer unit registers */ | ||
106 | int was_stopped = !!(jz_read(TCU_STOP) & (1 << chn)); | ||
107 | if(was_stopped) | ||
108 | jz_clr(TCU_STOP, 1 << chn); | ||
109 | |||
110 | /* check if timer is currently running */ | ||
111 | int was_enabled = !!(jz_read(TCU_ENABLE) & (1 << chn)); | ||
112 | int enabled = was_enabled; | ||
113 | |||
114 | if(prescaler != st->prescaler) { | ||
115 | /* must disable timer to change these settings */ | ||
116 | if(was_enabled) { | ||
117 | jz_clr(TCU_ENABLE, 1 << chn); | ||
118 | enabled = 0; | ||
119 | } | ||
120 | |||
121 | jz_overwritef(TCU_CTRL(chn), SHUTDOWN_V(GRACEFUL), INIT_LVL(0), | ||
122 | PWM_EN(1), PRESCALE(prescaler), SOURCE_V(PCLK)); | ||
123 | REG_TCU_COUNT(chn) = 0; | ||
124 | st->prescaler = prescaler; | ||
125 | } | ||
126 | |||
127 | if(full_ticks != st->full_ticks || half_ticks != st->half_ticks) { | ||
128 | if(enabled) { | ||
129 | /* avoid changing PWM settings in the middle of a cycle */ | ||
130 | unsigned cmp = REG_TCU_CMP_FULL(chn) - 1; | ||
131 | long deadline = current_tick + 3; | ||
132 | while(REG_TCU_COUNT(chn) < cmp | ||
133 | && TIME_BEFORE(current_tick, deadline)); | ||
134 | } | ||
135 | |||
136 | /* these can be changed while the timer is running */ | ||
137 | REG_TCU_CMP_FULL(chn) = full_ticks; | ||
138 | REG_TCU_CMP_HALF(chn) = full_ticks - half_ticks; | ||
139 | st->full_ticks = full_ticks; | ||
140 | st->half_ticks = half_ticks; | ||
141 | } | ||
142 | |||
143 | /* restore the enable/stop state */ | ||
144 | if(was_enabled && !enabled) | ||
145 | jz_set(TCU_ENABLE, 1 << chn); | ||
146 | if(was_stopped) | ||
147 | jz_set(TCU_STOP, 1 << chn); | ||
148 | } | ||
149 | |||
150 | void pwm_enable(int chn) | ||
151 | { | ||
152 | /* Start timer */ | ||
153 | jz_clr(TCU_STOP, 1 << chn); | ||
154 | jz_set(TCU_ENABLE, 1 << chn); | ||
155 | |||
156 | /* Configure GPIO function */ | ||
157 | struct pwm_state* st = &pwm_state[chn]; | ||
158 | gpio_config(st->gpio.port, st->gpio.pin, st->gpio.func); | ||
159 | } | ||
160 | |||
161 | void pwm_disable(int chn) | ||
162 | { | ||
163 | /* Set GPIO to output 0 */ | ||
164 | struct pwm_state* st = &pwm_state[chn]; | ||
165 | gpio_config(st->gpio.port, st->gpio.pin, GPIO_OUTPUT(0)); | ||
166 | |||
167 | /* Stop timer */ | ||
168 | jz_clr(TCU_ENABLE, 1 << chn); | ||
169 | jz_set(TCU_STOP, 1 << chn); | ||
170 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/pwm-x1000.h b/firmware/target/mips/ingenic_x1000/pwm-x1000.h new file mode 100644 index 0000000000..0cea266d63 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/pwm-x1000.h | |||
@@ -0,0 +1,47 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef __PWM_X1000_H__ | ||
23 | #define __PWM_X1000_H__ | ||
24 | |||
25 | /* Usage: | ||
26 | * - There are 5 PWM channels (0-4) corresponding to TCUs 0-4 | ||
27 | * - Call pwm_init(n) before using channel n | ||
28 | * - Call pwm_set_period() to change the period and duty cycle at any time | ||
29 | * - Call pwm_enable() and pwm_disable() to turn the output on and off | ||
30 | * - Don't allow two threads to control the same channel at the same time | ||
31 | * - Don't call pwm_init(), pwm_enable(), or pwm_disable() from an interrupt | ||
32 | * | ||
33 | * After calling pwm_init(), the channel is essentially in a disabled state so | ||
34 | * you will need to call pwm_set_period() and then pwm_enable() to turn it on. | ||
35 | * Don't alter the channel's TCU or GPIO pin state after calling pwm_init(). | ||
36 | * | ||
37 | * After calling pwm_disable(), it is safe to use the channel's TCU or GPIO pin | ||
38 | * for some other purpose, but you must call pwm_init() before you can use the | ||
39 | * channel as PWM output again. | ||
40 | */ | ||
41 | |||
42 | extern void pwm_init(int chn); | ||
43 | extern void pwm_set_period(int chn, int period_ns, int duty_ns); | ||
44 | extern void pwm_enable(int chn); | ||
45 | extern void pwm_disable(int chn); | ||
46 | |||
47 | #endif /* __PWM_X1000_H__ */ | ||
diff --git a/firmware/target/mips/ingenic_x1000/sd-x1000.c b/firmware/target/mips/ingenic_x1000/sd-x1000.c new file mode 100644 index 0000000000..7fba617ce3 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/sd-x1000.c | |||
@@ -0,0 +1,236 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "storage.h" | ||
23 | #include "sdmmc.h" | ||
24 | #include "sd.h" | ||
25 | #include "msc-x1000.h" | ||
26 | #include <string.h> | ||
27 | |||
28 | /* #define LOGF_ENABLE */ | ||
29 | #include "logf.h" | ||
30 | |||
31 | static msc_drv* sd_to_msc[MSC_COUNT]; | ||
32 | static long _sd_last_disk_activity = 0; | ||
33 | |||
34 | static int sd_init_card(msc_drv* d) | ||
35 | { | ||
36 | int s; | ||
37 | if(s = msc_cmd_go_idle_state(d)) return -100 - s; | ||
38 | if(s = msc_cmd_send_if_cond(d)) return -110 - s; | ||
39 | if(s = msc_cmd_app_op_cond(d)) return -120 - s; | ||
40 | if(s = msc_cmd_all_send_cid(d)) return -130 - s; | ||
41 | if(s = msc_cmd_send_rca(d)) return -140 - s; | ||
42 | if(s = msc_cmd_send_csd(d)) return -150 - s; | ||
43 | if(s = msc_cmd_select_card(d)) return -160 - s; | ||
44 | if(s = msc_cmd_set_clr_card_detect(d, 0)) return -170 - s; | ||
45 | if(s = msc_cmd_set_bus_width(d, 4)) return -180 - s; | ||
46 | if(s = msc_cmd_switch_freq(d)) return -190 - s; | ||
47 | d->driver_flags |= MSC_DF_READY; | ||
48 | d->cardinfo.initialized = 1; | ||
49 | return 0; | ||
50 | } | ||
51 | |||
52 | static int sd_transfer(msc_drv* d, bool write, | ||
53 | unsigned long start, int count, void* buf) | ||
54 | { | ||
55 | int status = -1; | ||
56 | |||
57 | msc_lock(d); | ||
58 | if(!d->card_present) | ||
59 | goto _exit; | ||
60 | |||
61 | /* Hopefully puts the driver into a working state */ | ||
62 | if(d->driver_flags & MSC_DF_ERRSTATE) { | ||
63 | logf("MSC%d: attempting to reset after ERRSTATE", d->msc_nr); | ||
64 | msc_full_reset(d); | ||
65 | } | ||
66 | |||
67 | /* Init card if needed */ | ||
68 | if((d->driver_flags & MSC_DF_READY) == 0) { | ||
69 | if(status = sd_init_card(d)) { | ||
70 | logf("MSC%d: card init failed (code %d)", d->msc_nr, status); | ||
71 | d->driver_flags |= MSC_DF_ERRSTATE; | ||
72 | d->cardinfo.initialized = status; | ||
73 | goto _exit; | ||
74 | } | ||
75 | } | ||
76 | |||
77 | /* Ensure parameters are within range */ | ||
78 | if(count < 1) | ||
79 | goto _exit; | ||
80 | if(start + count > d->cardinfo.numblocks) | ||
81 | goto _exit; | ||
82 | |||
83 | do { | ||
84 | /* We can only do 65536 blocks at a time */ | ||
85 | int xfer_count = count > 0xffff ? 0xffff : count; | ||
86 | |||
87 | /* Set block length. I think this is only necessary for non-HCS cards. | ||
88 | * HCS cards always use 512 bytes so we shouldn't need it. | ||
89 | */ | ||
90 | if((d->driver_flags & MSC_DF_HCS_CARD) == 0) | ||
91 | if(status = msc_cmd_set_block_len(d, SD_BLOCK_SIZE)) | ||
92 | goto _exit; | ||
93 | |||
94 | /* TODO - look into using CMD23 to improve transfer performance. | ||
95 | * This specifies the number of blocks ahead of time, instead of | ||
96 | * relying on CMD12 to stop transmission. CMD12 is still needed | ||
97 | * in the event of errors though. | ||
98 | */ | ||
99 | msc_req req = {0}; | ||
100 | req.data = buf; | ||
101 | req.nr_blocks = xfer_count; | ||
102 | req.block_len = SD_BLOCK_SIZE; | ||
103 | req.resptype = MSC_RESP_R1; | ||
104 | req.flags = MSC_RF_DATA; | ||
105 | if(xfer_count > 1) | ||
106 | req.flags |= MSC_RF_AUTO_CMD12; | ||
107 | if(write) { | ||
108 | req.command = xfer_count == 1 ? SD_WRITE_BLOCK | ||
109 | : SD_WRITE_MULTIPLE_BLOCK; | ||
110 | req.flags |= MSC_RF_PROG | MSC_RF_WRITE; | ||
111 | } else { | ||
112 | req.command = xfer_count == 1 ? SD_READ_SINGLE_BLOCK | ||
113 | : SD_READ_MULTIPLE_BLOCK; | ||
114 | } | ||
115 | |||
116 | if(d->driver_flags & MSC_DF_V2_CARD) | ||
117 | req.argument = start; | ||
118 | else | ||
119 | req.argument = start * SD_BLOCK_SIZE; | ||
120 | |||
121 | if(status = msc_cmd_exec(d, &req)) | ||
122 | goto _exit; | ||
123 | |||
124 | /* TODO - properly handle reading the last block of the SD card | ||
125 | * This is likely to fail if we're reading near the end because | ||
126 | * the SD card will try to read past the last sector and then | ||
127 | * signal an error. So we need to ignore that error, but only if | ||
128 | * it was expected to occur. (See SD spec sec. 4.3.3, "Block Read") | ||
129 | */ | ||
130 | if(status = msc_cmd_send_status(d)) | ||
131 | goto _exit; | ||
132 | |||
133 | /* Advance the buffer and adjust start/count */ | ||
134 | buf += xfer_count * SD_BLOCK_SIZE; | ||
135 | start += xfer_count; | ||
136 | count -= xfer_count; | ||
137 | } while(count > 0); | ||
138 | |||
139 | _exit: | ||
140 | msc_unlock(d); | ||
141 | return status; | ||
142 | } | ||
143 | |||
144 | int sd_read_sectors(IF_MD(int drive,) unsigned long start, | ||
145 | int count, void* buf) | ||
146 | { | ||
147 | return sd_transfer(sd_to_msc[IF_MD_DRV(drive)], false, | ||
148 | start, count, buf); | ||
149 | } | ||
150 | |||
151 | int sd_write_sectors(IF_MD(int drive,) unsigned long start, | ||
152 | int count, const void* buf) | ||
153 | { | ||
154 | return sd_transfer(sd_to_msc[IF_MD_DRV(drive)], true, | ||
155 | start, count, (void*)buf); | ||
156 | } | ||
157 | |||
158 | tCardInfo* card_get_info_target(int card_nr) | ||
159 | { | ||
160 | /* Defensive measures */ | ||
161 | if(card_nr < 0 || card_nr >= MSC_COUNT || sd_to_msc[card_nr] == NULL) { | ||
162 | static tCardInfo null_info = { 0 }; | ||
163 | return &null_info; | ||
164 | } | ||
165 | |||
166 | return &sd_to_msc[card_nr]->cardinfo; | ||
167 | } | ||
168 | |||
169 | int sd_event(long id, intptr_t data) | ||
170 | { | ||
171 | if(id == SYS_HOTSWAP_EXTRACTED) { | ||
172 | msc_drv* d = msc_get_by_drive(data); | ||
173 | if(d) | ||
174 | msc_full_reset(d); | ||
175 | return 0; | ||
176 | } else { | ||
177 | return storage_event_default_handler(id, data, _sd_last_disk_activity, | ||
178 | STORAGE_SD); | ||
179 | } | ||
180 | } | ||
181 | |||
182 | long sd_last_disk_activity(void) | ||
183 | { | ||
184 | return _sd_last_disk_activity; | ||
185 | } | ||
186 | |||
187 | bool sd_present(IF_MD_NONVOID(int drive)) | ||
188 | { | ||
189 | /* Seems that volume_properties() in firmware/common/disk.c may pass | ||
190 | * drive = -1 when the SD card is not inserted, so just return false. | ||
191 | */ | ||
192 | if(drive < 0) | ||
193 | return false; | ||
194 | |||
195 | return sd_to_msc[IF_MD_DRV(drive)]->card_present; | ||
196 | } | ||
197 | |||
198 | bool sd_removable(IF_MD_NONVOID(int drive)) | ||
199 | { | ||
200 | /* Same reason as sd_present() */ | ||
201 | if(drive < 0) | ||
202 | return false; | ||
203 | |||
204 | return sd_to_msc[IF_MD_DRV(drive)]->config->cd_gpio.pin != 0; | ||
205 | } | ||
206 | |||
207 | #ifndef CONFIG_STORAGE_MULTI | ||
208 | static | ||
209 | #endif | ||
210 | int sd_num_drives(int first_drive) | ||
211 | { | ||
212 | int n = 0; | ||
213 | for(; n < MSC_COUNT; ++n) { | ||
214 | msc_drv* d = msc_get(MSC_TYPE_SD, n); | ||
215 | if(d == NULL) | ||
216 | break; | ||
217 | |||
218 | d->drive_nr = first_drive + n; | ||
219 | sd_to_msc[n] = d; | ||
220 | } | ||
221 | |||
222 | for(int i = n; i < MSC_COUNT; ++i) | ||
223 | sd_to_msc[i] = NULL; | ||
224 | |||
225 | return n; | ||
226 | } | ||
227 | |||
228 | int sd_init(void) | ||
229 | { | ||
230 | msc_init(); | ||
231 | #ifndef CONFIG_STORAGE_MULTI | ||
232 | sd_num_drives(0); | ||
233 | #endif | ||
234 | |||
235 | return 0; | ||
236 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/sfc-x1000.c b/firmware/target/mips/ingenic_x1000/sfc-x1000.c new file mode 100644 index 0000000000..9537cdc035 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/sfc-x1000.c | |||
@@ -0,0 +1,298 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "system.h" | ||
23 | #include "kernel.h" | ||
24 | #include "panic.h" | ||
25 | #include "sfc-x1000.h" | ||
26 | #include "gpio-x1000.h" | ||
27 | #include "irq-x1000.h" | ||
28 | #include "x1000/sfc.h" | ||
29 | #include "x1000/cpm.h" | ||
30 | |||
31 | #ifndef BOOTLOADER_SPL | ||
32 | /* DMA only works once the system is properly booted */ | ||
33 | # define NEED_SFC_DMA | ||
34 | #endif | ||
35 | |||
36 | #if defined(BOOTLOADER_SPL) | ||
37 | # if X1000_EXCLK_FREQ == 24000000 | ||
38 | # define FIXED_CLK_FREQ 600000000 | ||
39 | # define FIXED_CLK_SRC X1000_CLK_MPLL | ||
40 | # elif X1000_EXCLK_FREQ == 26000000 | ||
41 | # define FIXED_CLK_FREQ 598000000 | ||
42 | # define FIXED_CLK_SRC X1000_CLK_MPLL | ||
43 | # else | ||
44 | # error "bad EXCLK freq" | ||
45 | # endif | ||
46 | #endif | ||
47 | |||
48 | #define FIFO_THRESH 31 | ||
49 | |||
50 | #define SFC_STATUS_PENDING (-1) | ||
51 | |||
52 | #ifdef NEED_SFC_DMA | ||
53 | static struct mutex sfc_mutex; | ||
54 | static struct semaphore sfc_sema; | ||
55 | static struct timeout sfc_lockup_tmo; | ||
56 | static bool sfc_inited = false; | ||
57 | static volatile int sfc_status; | ||
58 | #else | ||
59 | # define sfc_status SFC_STATUS_OK | ||
60 | #endif | ||
61 | |||
62 | void sfc_init(void) | ||
63 | { | ||
64 | #ifdef NEED_SFC_DMA | ||
65 | if(sfc_inited) | ||
66 | return; | ||
67 | |||
68 | mutex_init(&sfc_mutex); | ||
69 | semaphore_init(&sfc_sema, 1, 0); | ||
70 | sfc_inited = true; | ||
71 | #endif | ||
72 | } | ||
73 | |||
74 | void sfc_lock(void) | ||
75 | { | ||
76 | #ifdef NEED_SFC_DMA | ||
77 | mutex_lock(&sfc_mutex); | ||
78 | #endif | ||
79 | } | ||
80 | |||
81 | void sfc_unlock(void) | ||
82 | { | ||
83 | #ifdef NEED_SFC_DMA | ||
84 | mutex_unlock(&sfc_mutex); | ||
85 | #endif | ||
86 | } | ||
87 | |||
88 | void sfc_open(void) | ||
89 | { | ||
90 | gpio_config(GPIO_A, 0x3f << 26, GPIO_DEVICE(1)); | ||
91 | jz_writef(CPM_CLKGR, SFC(0)); | ||
92 | jz_writef(SFC_GLB, OP_MODE_V(SLAVE), PHASE_NUM(1), | ||
93 | THRESHOLD(FIFO_THRESH), WP_EN(1)); | ||
94 | REG_SFC_CGE = 0; | ||
95 | REG_SFC_INTC = 0x1f; | ||
96 | REG_SFC_MEM_ADDR = 0; | ||
97 | |||
98 | #ifdef NEED_SFC_DMA | ||
99 | jz_writef(SFC_GLB, OP_MODE_V(DMA), BURST_MD_V(INCR32)); | ||
100 | system_enable_irq(IRQ_SFC); | ||
101 | #endif | ||
102 | } | ||
103 | |||
104 | void sfc_close(void) | ||
105 | { | ||
106 | #ifdef NEED_SFC_DMA | ||
107 | system_disable_irq(IRQ_SFC); | ||
108 | #endif | ||
109 | |||
110 | REG_SFC_CGE = 0x1f; | ||
111 | jz_writef(CPM_CLKGR, SFC(1)); | ||
112 | } | ||
113 | |||
114 | void sfc_set_clock(x1000_clk_t clksrc, uint32_t freq) | ||
115 | { | ||
116 | uint32_t in_freq; | ||
117 | #ifdef FIXED_CLK_FREQ | ||
118 | /* Small optimization to save code space in SPL by not polling clock */ | ||
119 | clksrc = FIXED_CLK_SRC; | ||
120 | in_freq = FIXED_CLK_FREQ; | ||
121 | #else | ||
122 | in_freq = clk_get(clksrc); | ||
123 | #endif | ||
124 | |||
125 | uint32_t div = clk_calc_div(in_freq, freq); | ||
126 | jz_writef(CPM_SSICDR, CE(1), CLKDIV(div - 1), | ||
127 | SFC_CS(clksrc == X1000_CLK_MPLL ? 1 : 0)); | ||
128 | while(jz_readf(CPM_SSICDR, BUSY)); | ||
129 | jz_writef(CPM_SSICDR, CE(0)); | ||
130 | } | ||
131 | |||
132 | #ifdef NEED_SFC_DMA | ||
133 | static int sfc_lockup_tmo_cb(struct timeout* tmo) | ||
134 | { | ||
135 | (void)tmo; | ||
136 | |||
137 | int irq = disable_irq_save(); | ||
138 | if(sfc_status == SFC_STATUS_PENDING) { | ||
139 | sfc_status = SFC_STATUS_LOCKUP; | ||
140 | jz_overwritef(SFC_TRIG, STOP(1)); | ||
141 | semaphore_release(&sfc_sema); | ||
142 | } | ||
143 | |||
144 | restore_irq(irq); | ||
145 | return 0; | ||
146 | } | ||
147 | |||
148 | static void sfc_wait_end(void) | ||
149 | { | ||
150 | semaphore_wait(&sfc_sema, TIMEOUT_BLOCK); | ||
151 | } | ||
152 | |||
153 | void SFC(void) | ||
154 | { | ||
155 | unsigned sr = REG_SFC_SR & ~REG_SFC_INTC; | ||
156 | |||
157 | if(jz_vreadf(sr, SFC_SR, OVER)) { | ||
158 | jz_overwritef(SFC_SCR, CLR_OVER(1)); | ||
159 | sfc_status = SFC_STATUS_OVERFLOW; | ||
160 | } else if(jz_vreadf(sr, SFC_SR, UNDER)) { | ||
161 | jz_overwritef(SFC_SCR, CLR_UNDER(1)); | ||
162 | sfc_status = SFC_STATUS_UNDERFLOW; | ||
163 | } else if(jz_vreadf(sr, SFC_SR, END)) { | ||
164 | jz_overwritef(SFC_SCR, CLR_END(1)); | ||
165 | sfc_status = SFC_STATUS_OK; | ||
166 | } else { | ||
167 | panicf("SFC IRQ bug"); | ||
168 | return; | ||
169 | } | ||
170 | |||
171 | /* Not sure this is wholly correct */ | ||
172 | if(sfc_status != SFC_STATUS_OK) | ||
173 | jz_overwritef(SFC_TRIG, STOP(1)); | ||
174 | |||
175 | REG_SFC_INTC = 0x1f; | ||
176 | semaphore_release(&sfc_sema); | ||
177 | } | ||
178 | #else | ||
179 | /* Note the X1000 is *very* picky about how the SFC FIFOs are accessed | ||
180 | * so please do NOT try to rearrange the code without testing it first! | ||
181 | */ | ||
182 | |||
183 | void sfc_fifo_read(unsigned* buffer, int data_bytes) | ||
184 | { | ||
185 | int data_words = (data_bytes + 3) / 4; | ||
186 | while(data_words > 0) { | ||
187 | if(jz_readf(SFC_SR, RREQ)) { | ||
188 | jz_overwritef(SFC_SCR, CLR_RREQ(1)); | ||
189 | |||
190 | int amount = data_words > FIFO_THRESH ? FIFO_THRESH : data_words; | ||
191 | data_words -= amount; | ||
192 | while(amount > 0) { | ||
193 | *buffer++ = REG_SFC_DATA; | ||
194 | amount -= 1; | ||
195 | } | ||
196 | } | ||
197 | } | ||
198 | } | ||
199 | |||
200 | void sfc_fifo_write(const unsigned* buffer, int data_bytes) | ||
201 | { | ||
202 | int data_words = (data_bytes + 3) / 4; | ||
203 | while(data_words > 0) { | ||
204 | if(jz_readf(SFC_SR, TREQ)) { | ||
205 | jz_overwritef(SFC_SCR, CLR_TREQ(1)); | ||
206 | |||
207 | int amount = data_words > FIFO_THRESH ? FIFO_THRESH : data_words; | ||
208 | data_words -= amount; | ||
209 | while(amount > 0) { | ||
210 | REG_SFC_DATA = *buffer++; | ||
211 | amount -= 1; | ||
212 | } | ||
213 | } | ||
214 | } | ||
215 | } | ||
216 | |||
217 | static void sfc_wait_end(void) | ||
218 | { | ||
219 | while(jz_readf(SFC_SR, END) == 0); | ||
220 | jz_overwritef(SFC_SCR, CLR_TREQ(1)); | ||
221 | } | ||
222 | |||
223 | #endif /* NEED_SFC_DMA */ | ||
224 | |||
225 | int sfc_exec(const sfc_op* op) | ||
226 | { | ||
227 | #ifdef NEED_SFC_DMA | ||
228 | uint32_t intc_clear = jz_orm(SFC_INTC, MSK_END); | ||
229 | #endif | ||
230 | |||
231 | if(op->flags & (SFC_FLAG_READ|SFC_FLAG_WRITE)) { | ||
232 | jz_writef(SFC_TRAN_CONF(0), DATA_EN(1)); | ||
233 | REG_SFC_TRAN_LENGTH = op->data_bytes; | ||
234 | #ifdef NEED_SFC_DMA | ||
235 | REG_SFC_MEM_ADDR = PHYSADDR(op->buffer); | ||
236 | #endif | ||
237 | |||
238 | if(op->flags & SFC_FLAG_READ) | ||
239 | { | ||
240 | jz_writef(SFC_GLB, TRAN_DIR_V(READ)); | ||
241 | #ifdef NEED_SFC_DMA | ||
242 | discard_dcache_range(op->buffer, op->data_bytes); | ||
243 | intc_clear |= jz_orm(SFC_INTC, MSK_OVER); | ||
244 | #endif | ||
245 | } | ||
246 | else | ||
247 | { | ||
248 | jz_writef(SFC_GLB, TRAN_DIR_V(WRITE)); | ||
249 | #ifdef NEED_SFC_DMA | ||
250 | commit_dcache_range(op->buffer, op->data_bytes); | ||
251 | intc_clear |= jz_orm(SFC_INTC, MSK_UNDER); | ||
252 | #endif | ||
253 | } | ||
254 | } else { | ||
255 | jz_writef(SFC_TRAN_CONF(0), DATA_EN(0)); | ||
256 | REG_SFC_TRAN_LENGTH = 0; | ||
257 | #ifdef NEED_SFC_DMA | ||
258 | REG_SFC_MEM_ADDR = 0; | ||
259 | #endif | ||
260 | } | ||
261 | |||
262 | bool dummy_first = (op->flags & SFC_FLAG_DUMMYFIRST) != 0; | ||
263 | jz_writef(SFC_TRAN_CONF(0), | ||
264 | MODE(op->mode), POLL_EN(0), | ||
265 | ADDR_WIDTH(op->addr_bytes), | ||
266 | PHASE_FMT(dummy_first ? 1 : 0), | ||
267 | DUMMY_BITS(op->dummy_bits), | ||
268 | COMMAND(op->command), CMD_EN(1)); | ||
269 | |||
270 | REG_SFC_DEV_ADDR(0) = op->addr_lo; | ||
271 | REG_SFC_DEV_PLUS(0) = op->addr_hi; | ||
272 | |||
273 | #ifdef NEED_SFC_DMA | ||
274 | sfc_status = SFC_STATUS_PENDING; | ||
275 | timeout_register(&sfc_lockup_tmo, sfc_lockup_tmo_cb, 10*HZ, 0); | ||
276 | REG_SFC_SCR = 0x1f; | ||
277 | REG_SFC_INTC &= ~intc_clear; | ||
278 | #endif | ||
279 | |||
280 | jz_overwritef(SFC_TRIG, FLUSH(1)); | ||
281 | jz_overwritef(SFC_TRIG, START(1)); | ||
282 | |||
283 | #ifndef NEED_SFC_DMA | ||
284 | if(op->flags & SFC_FLAG_READ) | ||
285 | sfc_fifo_read((unsigned*)op->buffer, op->data_bytes); | ||
286 | if(op->flags & SFC_FLAG_WRITE) | ||
287 | sfc_fifo_write((const unsigned*)op->buffer, op->data_bytes); | ||
288 | #endif | ||
289 | |||
290 | sfc_wait_end(); | ||
291 | |||
292 | #ifdef NEED_SFC_DMA | ||
293 | if(op->flags & SFC_FLAG_READ) | ||
294 | discard_dcache_range(op->buffer, op->data_bytes); | ||
295 | #endif | ||
296 | |||
297 | return sfc_status; | ||
298 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/sfc-x1000.h b/firmware/target/mips/ingenic_x1000/sfc-x1000.h new file mode 100644 index 0000000000..283f171697 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/sfc-x1000.h | |||
@@ -0,0 +1,105 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include <stdint.h> | ||
23 | #include <stdbool.h> | ||
24 | #include "clk-x1000.h" | ||
25 | #include "x1000/sfc.h" | ||
26 | |||
27 | /* SPI flash controller interface -- this is a low-level driver upon which | ||
28 | * you can build NAND/NOR flash drivers. The main function is sfc_exec(), | ||
29 | * used to issue commands, transfer data, etc. | ||
30 | */ | ||
31 | |||
32 | #define SFC_FLAG_READ 0x01 /* Read data */ | ||
33 | #define SFC_FLAG_WRITE 0x02 /* Write data */ | ||
34 | #define SFC_FLAG_DUMMYFIRST 0x04 /* Do dummy bits before sending address. | ||
35 | * Default is dummy bits after address. | ||
36 | */ | ||
37 | |||
38 | /* SPI transfer mode. If in doubt, check with the X1000 manual and confirm | ||
39 | * the transfer format is what you expect. | ||
40 | */ | ||
41 | #define SFC_MODE_STANDARD 0 | ||
42 | #define SFC_MODE_DUAL_IN_DUAL_OUT 1 | ||
43 | #define SFC_MODE_DUAL_IO 2 | ||
44 | #define SFC_MODE_FULL_DUAL_IO 3 | ||
45 | #define SFC_MODE_QUAD_IN_QUAD_OUT 4 | ||
46 | #define SFC_MODE_QUAD_IO 5 | ||
47 | #define SFC_MODE_FULL_QUAD_IO 6 | ||
48 | |||
49 | /* Return status codes for sfc_exec() */ | ||
50 | #define SFC_STATUS_OK 0 | ||
51 | #define SFC_STATUS_OVERFLOW 1 | ||
52 | #define SFC_STATUS_UNDERFLOW 2 | ||
53 | #define SFC_STATUS_LOCKUP 3 | ||
54 | |||
55 | typedef struct sfc_op { | ||
56 | int command; /* Command number */ | ||
57 | int mode; /* SPI transfer mode */ | ||
58 | int flags; /* Flags for this op */ | ||
59 | int addr_bytes; /* Number of address bytes */ | ||
60 | int dummy_bits; /* Number of dummy bits (yes: bits, not bytes) */ | ||
61 | uint32_t addr_lo; /* Lower 32 bits of address */ | ||
62 | uint32_t addr_hi; /* Upper 32 bits of address */ | ||
63 | int data_bytes; /* Number of data bytes to read/write */ | ||
64 | void* buffer; /* Data buffer -- MUST be word-aligned */ | ||
65 | } sfc_op; | ||
66 | |||
67 | /* One-time driver init for mutexes/etc needed for handling interrupts. | ||
68 | * This can be safely called multiple times; only the first call will | ||
69 | * actually perform the init. | ||
70 | */ | ||
71 | extern void sfc_init(void); | ||
72 | |||
73 | /* Controller mutex -- lock before touching the driver */ | ||
74 | extern void sfc_lock(void); | ||
75 | extern void sfc_unlock(void); | ||
76 | |||
77 | /* Open/close the driver. The driver must be open in order to do operations. | ||
78 | * Closing the driver shuts off the hardware; the driver can be re-opened at | ||
79 | * a later time when it's needed again. | ||
80 | * | ||
81 | * After opening the driver, you must also program a valid device configuration | ||
82 | * and clock rate using sfc_set_dev_conf() and sfc_set_clock(). | ||
83 | */ | ||
84 | extern void sfc_open(void); | ||
85 | extern void sfc_close(void); | ||
86 | |||
87 | /* These functions can be called at any time while the driver is open, but | ||
88 | * must not be called while there is an operation in progress. It's the | ||
89 | * caller's job to ensure the configuration will work with the device and | ||
90 | * be capable of reading back data correctly. | ||
91 | * | ||
92 | * - sfc_set_dev_conf() writes its argument to the SFC_DEV_CONF register. | ||
93 | * - sfc_set_wp_enable() sets the state of the write-protect pin (WP). | ||
94 | * - sfc_set_clock() sets the controller clock frequency (in Hz). | ||
95 | */ | ||
96 | #define sfc_set_dev_conf(dev_conf) \ | ||
97 | do { REG_SFC_DEV_CONF = (dev_conf); } while(0) | ||
98 | |||
99 | #define sfc_set_wp_enable(en) \ | ||
100 | jz_writef(SFC_GLB, WP_EN((en) ? 1 : 0)) | ||
101 | |||
102 | extern void sfc_set_clock(x1000_clk_t clksrc, uint32_t freq); | ||
103 | |||
104 | /* Execute an operation. Returns zero on success, nonzero on failure. */ | ||
105 | extern int sfc_exec(const sfc_op* op); | ||
diff --git a/firmware/target/mips/ingenic_x1000/spl.lds b/firmware/target/mips/ingenic_x1000/spl.lds new file mode 100644 index 0000000000..2a0b6b3eaa --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/spl.lds | |||
@@ -0,0 +1,47 @@ | |||
1 | #include "config.h" | ||
2 | |||
3 | OUTPUT_FORMAT("elf32-littlemips") | ||
4 | OUTPUT_ARCH(MIPS) | ||
5 | ENTRY(_start) | ||
6 | STARTUP(target/mips/ingenic_x1000/crt0.o) | ||
7 | |||
8 | /* TCSM is 16 KiB and is mapped starting at address 0xf4000000. | ||
9 | * | ||
10 | * The SPL is loaded to TCSM + 0x1000. The area below that is stack space. | ||
11 | * The first 2 KiB of SPL is just headers. The code begins at TCSM + 0x1800. | ||
12 | * The maskrom will jump to that address (via jalr) after loading the SPL. | ||
13 | */ | ||
14 | MEMORY { TCSM : ORIGIN = 0xf4001800, LENGTH = 0x2800 } | ||
15 | |||
16 | SECTIONS | ||
17 | { | ||
18 | .text : | ||
19 | { | ||
20 | *(.init.text); | ||
21 | *(.text*); | ||
22 | } > TCSM | ||
23 | |||
24 | . = ALIGN(4); | ||
25 | .rodata : | ||
26 | { | ||
27 | *(.rodata*); | ||
28 | } > TCSM | ||
29 | |||
30 | . = ALIGN(4); | ||
31 | .data : | ||
32 | { | ||
33 | *(.data*); | ||
34 | *(.sdata*); | ||
35 | } > TCSM | ||
36 | |||
37 | . = ALIGN(4); | ||
38 | .bss (NOLOAD) : | ||
39 | { | ||
40 | _bssbegin = .; | ||
41 | *(.sbss*); | ||
42 | *(.bss*); | ||
43 | *(COMMON); | ||
44 | *(.scommon*); | ||
45 | _bssend = .; | ||
46 | } > TCSM | ||
47 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/system-target.h b/firmware/target/mips/ingenic_x1000/system-target.h new file mode 100644 index 0000000000..a2f0a6ff70 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/system-target.h | |||
@@ -0,0 +1,148 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef __SYSTEM_TARGET_H__ | ||
23 | #define __SYSTEM_TARGET_H__ | ||
24 | |||
25 | /* For the sake of system.h CACHEALIGN macros. | ||
26 | * We need this to align DMA buffers, etc. | ||
27 | */ | ||
28 | #define CACHEALIGN_BITS 5 | ||
29 | #define CACHE_SIZE (16*1024) | ||
30 | |||
31 | #include "mmu-mips.h" | ||
32 | #include "mipsregs.h" | ||
33 | #include "mipsr2-endian.h" | ||
34 | #include <stdint.h> | ||
35 | |||
36 | /* Get physical address for DMA */ | ||
37 | #define PHYSADDR(addr) (((unsigned long)(addr)) & 0x1fffffff) | ||
38 | |||
39 | #define HIGHEST_IRQ_LEVEL 0 | ||
40 | |||
41 | /* Rockbox API */ | ||
42 | #define enable_irq() set_c0_status(ST0_IE) | ||
43 | #define disable_irq() clear_c0_status(ST0_IE) | ||
44 | #define disable_irq_save() set_irq_level(0) | ||
45 | #define restore_irq(arg) write_c0_status(arg) | ||
46 | |||
47 | static inline int set_irq_level(int lev) | ||
48 | { | ||
49 | unsigned reg, oldreg; | ||
50 | reg = oldreg = read_c0_status(); | ||
51 | if(lev) | ||
52 | reg |= ST0_IE; | ||
53 | else | ||
54 | reg &= ~ST0_IE; | ||
55 | |||
56 | write_c0_status(reg); | ||
57 | return oldreg; | ||
58 | } | ||
59 | |||
60 | /* CPU idle stats, updated each kernel tick in kernel-x1000.c */ | ||
61 | extern int __cpu_idle_avg; | ||
62 | extern int __cpu_idle_cur; | ||
63 | extern uint32_t __cpu_idle_ticks; | ||
64 | extern uint32_t __cpu_idle_reftick; | ||
65 | |||
66 | static inline uint32_t __ost_read32(void); | ||
67 | static inline void core_sleep(void) | ||
68 | { | ||
69 | uint32_t t1 = __ost_read32(); | ||
70 | |||
71 | __asm__ __volatile__( | ||
72 | ".set push\n\t" | ||
73 | ".set mips32r2\n\t" | ||
74 | "mfc0 $8, $12\n\t" | ||
75 | "move $9, $8\n\t" | ||
76 | "la $10, 0x8000000\n\t" | ||
77 | "or $8, $10\n\t" | ||
78 | "mtc0 $8, $12\n\t" | ||
79 | "wait\n\t" | ||
80 | "mtc0 $9, $12\n\t" | ||
81 | ".set pop\n\t" | ||
82 | ::: "t0", "t1", "t2"); | ||
83 | |||
84 | uint32_t t2 = __ost_read32(); | ||
85 | __cpu_idle_ticks += t2 - t1; | ||
86 | |||
87 | enable_irq(); | ||
88 | } | ||
89 | |||
90 | /* IRQ control */ | ||
91 | extern void system_enable_irq(int irq); | ||
92 | extern void system_disable_irq(int irq); | ||
93 | |||
94 | /* Simple delay API */ | ||
95 | #define OST_FREQUENCY (X1000_EXCLK_FREQ / 4) | ||
96 | #define OST_TICKS_PER_US (OST_FREQUENCY / 1000000) | ||
97 | #define MAX_OST_DELAY_ARG 0x7fffffff | ||
98 | #define MAX_UDELAY_ARG (MAX_OST_DELAY_ARG / OST_TICKS_PER_US) | ||
99 | #define MAX_MDELAY_ARG (MAX_UDELAY_ARG / 1000) | ||
100 | |||
101 | /* Macros adapted from include/linux/delay.h, | ||
102 | * Copyright (C) 1993 Linus Torvalds | ||
103 | * | ||
104 | * These optimize away all calculations to compile time for the common case | ||
105 | * of small constant arguments, reducing to a single __ost_delay() call. | ||
106 | */ | ||
107 | |||
108 | #define udelay(n) \ | ||
109 | ((__builtin_constant_p(n) && (n) <= MAX_UDELAY_ARG) ? \ | ||
110 | __ost_delay((n) * OST_TICKS_PER_US) : __udelay((n))) | ||
111 | |||
112 | #define mdelay(n) \ | ||
113 | ((__builtin_constant_p(n) && (n) <= MAX_MDELAY_ARG) ? \ | ||
114 | __ost_delay((n) * 1000 * OST_TICKS_PER_US) : __mdelay((n))) | ||
115 | |||
116 | /* Slow path implementations which handle their full argument range by | ||
117 | * looping and calling __ost_delay() repeatedly. | ||
118 | */ | ||
119 | extern void __udelay(uint32_t us); | ||
120 | extern void __mdelay(uint32_t ms); | ||
121 | |||
122 | /* Read full 64-bit OST counter value; this requires disabling IRQs | ||
123 | * to safely read the counter. | ||
124 | */ | ||
125 | extern uint64_t __ost_read64(void); | ||
126 | |||
127 | static inline uint32_t __ost_read32(void) | ||
128 | { | ||
129 | /* Read OST_2CNTL using raw address to avoid exposing internal headers. | ||
130 | * The 64-bit counter is read with IRQs disabled and since threads are | ||
131 | * not pre-emptive in Rockbox we won't trash anybody's 64-bit read by | ||
132 | * reading the low count without locking. | ||
133 | */ | ||
134 | return *(const volatile uint32_t*)0xb2000020; | ||
135 | } | ||
136 | |||
137 | /* NOTE: it is required that count < MAX_OST_DELAY_ARG, this is to provide | ||
138 | * some slack in the 32-bit counter so we can reliably detect the timeout. | ||
139 | */ | ||
140 | static inline void __ost_delay(uint32_t count) | ||
141 | { | ||
142 | /* Add one to ensure we delay for at least the time given */ | ||
143 | count += 1; | ||
144 | uint32_t start = __ost_read32(); | ||
145 | while(__ost_read32() - start < count); | ||
146 | } | ||
147 | |||
148 | #endif /* __SYSTEM_TARGET_H__ */ | ||
diff --git a/firmware/target/mips/ingenic_x1000/system-x1000.c b/firmware/target/mips/ingenic_x1000/system-x1000.c new file mode 100644 index 0000000000..54513cffb2 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/system-x1000.c | |||
@@ -0,0 +1,418 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "system.h" | ||
23 | #include "mips.h" | ||
24 | #include "panic.h" | ||
25 | #include "button.h" | ||
26 | #include "gpio-x1000.h" | ||
27 | #include "dma-x1000.h" | ||
28 | #include "irq-x1000.h" | ||
29 | #include "clk-x1000.h" | ||
30 | #include "x1000/cpm.h" | ||
31 | #include "x1000/ost.h" | ||
32 | #include "x1000/tcu.h" | ||
33 | #include "x1000/wdt.h" | ||
34 | #include "x1000/intc.h" | ||
35 | #include "x1000/msc.h" | ||
36 | #include "x1000/aic.h" | ||
37 | |||
38 | int __cpu_idle_avg = 0; | ||
39 | int __cpu_idle_cur = 0; | ||
40 | uint32_t __cpu_idle_ticks = 0; | ||
41 | uint32_t __cpu_idle_reftick = 0; | ||
42 | |||
43 | static void system_init_clk(void) | ||
44 | { | ||
45 | /* Gate all clocks except CPU/bus/memory/RTC */ | ||
46 | REG_CPM_CLKGR = ~jz_orm(CPM_CLKGR, CPU_BIT, DDR, AHB0, APB0, RTC); | ||
47 | |||
48 | /* Switch to EXCLK */ | ||
49 | clk_set_ccr_mux(CLKMUX_SCLK_A(EXCLK) | CLKMUX_CPU(SCLK_A) | | ||
50 | CLKMUX_AHB0(SCLK_A) | CLKMUX_AHB2(SCLK_A)); | ||
51 | clk_set_ccr_div(1, 1, 1, 1, 1); | ||
52 | |||
53 | #ifdef FIIO_M3K | ||
54 | /* Nominal clock configuration | ||
55 | * --------------------------- | ||
56 | * APLL at 1 GHz, MPLL disabled | ||
57 | * CPU at 1 GHz, L2 cache at 500 MHz | ||
58 | * AHB0 and AHB2 at 200 MHz | ||
59 | * PCLK at 100 MHz | ||
60 | * DDR at 200 MHz | ||
61 | */ | ||
62 | jz_writef(CPM_APCR, BS(1), PLLM(41), PLLN(0), PLLOD(0), ENABLE(1)); | ||
63 | while(jz_readf(CPM_APCR, ON) == 0); | ||
64 | |||
65 | clk_set_ccr_div(1, 2, 5, 5, 10); | ||
66 | clk_set_ccr_mux(CLKMUX_SCLK_A(APLL) | CLKMUX_CPU(SCLK_A) | | ||
67 | CLKMUX_AHB0(SCLK_A) | CLKMUX_AHB2(SCLK_A)); | ||
68 | clk_set_ddr(X1000_CLK_SCLK_A, 5); | ||
69 | |||
70 | /* Shut off MPLL, since nobody should be using it now */ | ||
71 | jz_writef(CPM_MPCR, ENABLE(0)); | ||
72 | #else | ||
73 | # error "Please define system clock configuration for target" | ||
74 | #endif | ||
75 | } | ||
76 | |||
77 | /* Prepare the CPU to process interrupts, but don't enable them yet */ | ||
78 | static void system_init_irq(void) | ||
79 | { | ||
80 | /* Mask all interrupts */ | ||
81 | jz_set(INTC_MSK(0), 0xffffffff); | ||
82 | jz_set(INTC_MSK(1), 0xffffffff); | ||
83 | |||
84 | /* It's safe to unmask these unconditionally */ | ||
85 | jz_clr(INTC_MSK(0), (1 << IRQ0_GPIO0) | (1 << IRQ0_GPIO1) | | ||
86 | (1 << IRQ0_GPIO2) | (1 << IRQ0_GPIO3) | | ||
87 | (1 << IRQ0_TCU1)); | ||
88 | |||
89 | /* Setup CP0 registers */ | ||
90 | write_c0_status(M_StatusCU0 | M_StatusIM2 | M_StatusIM3); | ||
91 | write_c0_cause(M_CauseIV); | ||
92 | } | ||
93 | |||
94 | /* First thing called from Rockbox main() */ | ||
95 | void system_init(void) | ||
96 | { | ||
97 | /* Setup system clocks */ | ||
98 | system_init_clk(); | ||
99 | |||
100 | /* Ungate timers and turn them all off by default */ | ||
101 | jz_writef(CPM_CLKGR, TCU(0), OST(0)); | ||
102 | jz_clrf(OST_ENABLE, OST1, OST2); | ||
103 | jz_write(OST_1MSK, 1); | ||
104 | jz_write(OST_1FLG, 0); | ||
105 | jz_clr(TCU_ENABLE, 0x80ff); | ||
106 | jz_set(TCU_MASK, 0xff10ff); | ||
107 | jz_clr(TCU_FLAG, 0xff10ff); | ||
108 | jz_set(TCU_STOP, 0x180ff); | ||
109 | |||
110 | /* Start OST2, needed for delay timer */ | ||
111 | jz_writef(OST_CTRL, PRESCALE2_V(BY_4)); | ||
112 | jz_writef(OST_CLEAR, OST2(1)); | ||
113 | jz_write(OST_2CNTH, 0); | ||
114 | jz_write(OST_2CNTL, 0); | ||
115 | jz_setf(OST_ENABLE, OST2); | ||
116 | |||
117 | /* Ensure CPU sleep mode is IDLE and not SLEEP */ | ||
118 | jz_writef(CPM_LCR, LPM_V(IDLE)); | ||
119 | |||
120 | /* All other init */ | ||
121 | gpio_init(); | ||
122 | system_init_irq(); | ||
123 | dma_init(); | ||
124 | mmu_init(); | ||
125 | } | ||
126 | |||
127 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ | ||
128 | void set_cpu_frequency(long tgt_freq) | ||
129 | { | ||
130 | /* Clamp target frequency to "sane" values */ | ||
131 | if(tgt_freq < 0) tgt_freq = 0; | ||
132 | if(tgt_freq > CPU_FREQ) tgt_freq = CPU_FREQ; | ||
133 | |||
134 | /* Find out input clock */ | ||
135 | uint32_t in_freq; | ||
136 | switch(jz_readf(CPM_CCR, SEL_CPLL)) { | ||
137 | case 1: in_freq = clk_get(X1000_CLK_SCLK_A); break; | ||
138 | case 2: in_freq = clk_get(X1000_CLK_MPLL); break; | ||
139 | default: return; | ||
140 | } | ||
141 | |||
142 | /* Clamp to valid range */ | ||
143 | if(tgt_freq < 1) | ||
144 | tgt_freq = 1; | ||
145 | if(tgt_freq > (long)in_freq) | ||
146 | tgt_freq = in_freq; | ||
147 | |||
148 | /* Calculate CPU clock divider */ | ||
149 | uint32_t cdiv = clk_calc_div(in_freq, tgt_freq); | ||
150 | if(cdiv > 16) cdiv = 16; | ||
151 | if(cdiv < 1) cdiv = 1; | ||
152 | |||
153 | /* Calculate L2 cache clock. */ | ||
154 | uint32_t l2div = cdiv; | ||
155 | if(cdiv == 1) | ||
156 | l2div = 2; | ||
157 | |||
158 | /* Change CPU/L2 frequency */ | ||
159 | jz_writef(CPM_CCR, CE_CPU(1), L2DIV(l2div - 1), CDIV(cdiv - 1)); | ||
160 | while(jz_readf(CPM_CSR, CDIV_BUSY)); | ||
161 | jz_writef(CPM_CCR, CE_CPU(0)); | ||
162 | |||
163 | /* Update value for Rockbox */ | ||
164 | cpu_frequency = in_freq / cdiv; | ||
165 | } | ||
166 | #endif | ||
167 | |||
168 | void system_reboot(void) | ||
169 | { | ||
170 | jz_clr(TCU_STOP, 0x10000); | ||
171 | jz_writef(WDT_CTRL, PRESCALE_V(BY_4), SOURCE_V(EXT)); | ||
172 | jz_write(WDT_COUNT, 0); | ||
173 | jz_write(WDT_DATA, X1000_EXCLK_FREQ / 1000); | ||
174 | jz_write(WDT_ENABLE, 1); | ||
175 | while(1); | ||
176 | } | ||
177 | |||
178 | int system_memory_guard(int mode) | ||
179 | { | ||
180 | /* unused */ | ||
181 | (void)mode; | ||
182 | return 0; | ||
183 | } | ||
184 | |||
185 | /* Simple delay API -- slow path functions */ | ||
186 | |||
187 | void __udelay(uint32_t us) | ||
188 | { | ||
189 | while(us > MAX_UDELAY_ARG) { | ||
190 | __ost_delay(MAX_UDELAY_ARG * OST_TICKS_PER_US); | ||
191 | us -= MAX_UDELAY_ARG; | ||
192 | } | ||
193 | |||
194 | __ost_delay(us * OST_TICKS_PER_US); | ||
195 | } | ||
196 | |||
197 | void __mdelay(uint32_t ms) | ||
198 | { | ||
199 | while(ms > MAX_MDELAY_ARG) { | ||
200 | __ost_delay(MAX_MDELAY_ARG * 1000 * OST_TICKS_PER_US); | ||
201 | ms -= MAX_MDELAY_ARG; | ||
202 | } | ||
203 | |||
204 | __ost_delay(ms * 1000 * OST_TICKS_PER_US); | ||
205 | } | ||
206 | |||
207 | uint64_t __ost_read64(void) | ||
208 | { | ||
209 | int irq = disable_irq_save(); | ||
210 | uint64_t lcnt = REG_OST_2CNTL; | ||
211 | uint64_t hcnt = REG_OST_2CNTHB; | ||
212 | restore_irq(irq); | ||
213 | return (hcnt << 32) | lcnt; | ||
214 | } | ||
215 | |||
216 | /* IRQ handling */ | ||
217 | static int irq = 0; | ||
218 | static unsigned ipr0 = 0, ipr1 = 0; | ||
219 | |||
220 | static void UIRQ(void) | ||
221 | { | ||
222 | panicf("Unhandled interrupt occurred: %d", irq); | ||
223 | } | ||
224 | |||
225 | #define intr(name) extern __attribute__((weak, alias("UIRQ"))) void name(void) | ||
226 | |||
227 | /* Main interrupts */ | ||
228 | intr(DMIC); intr(AIC); intr(SFC); intr(SSI0); intr(OTG); intr(AES); | ||
229 | intr(TCU2); intr(TCU1); intr(TCU0); intr(CIM); intr(LCD); intr(RTC); | ||
230 | intr(MSC1); intr(MSC0); intr(SCC); intr(PCM0); intr(HARB2); intr(HARB0); | ||
231 | intr(CPM); intr(UART2); intr(UART1); intr(UART0); intr(DDR); intr(EFUSE); | ||
232 | intr(MAC); intr(I2C2); intr(I2C1); intr(I2C0); intr(JPEG); | ||
233 | intr(PDMA); intr(PDMAD); intr(PDMAM); | ||
234 | /* GPIO A - 32 pins */ | ||
235 | intr(GPIOA00); intr(GPIOA01); intr(GPIOA02); intr(GPIOA03); intr(GPIOA04); | ||
236 | intr(GPIOA05); intr(GPIOA06); intr(GPIOA07); intr(GPIOA08); intr(GPIOA09); | ||
237 | intr(GPIOA10); intr(GPIOA11); intr(GPIOA12); intr(GPIOA13); intr(GPIOA14); | ||
238 | intr(GPIOA15); intr(GPIOA16); intr(GPIOA17); intr(GPIOA18); intr(GPIOA19); | ||
239 | intr(GPIOA20); intr(GPIOA21); intr(GPIOA22); intr(GPIOA23); intr(GPIOA24); | ||
240 | intr(GPIOA25); intr(GPIOA26); intr(GPIOA27); intr(GPIOA28); intr(GPIOA29); | ||
241 | intr(GPIOA30); intr(GPIOA31); | ||
242 | /* GPIO B - 32 pins */ | ||
243 | intr(GPIOB00); intr(GPIOB01); intr(GPIOB02); intr(GPIOB03); intr(GPIOB04); | ||
244 | intr(GPIOB05); intr(GPIOB06); intr(GPIOB07); intr(GPIOB08); intr(GPIOB09); | ||
245 | intr(GPIOB10); intr(GPIOB11); intr(GPIOB12); intr(GPIOB13); intr(GPIOB14); | ||
246 | intr(GPIOB15); intr(GPIOB16); intr(GPIOB17); intr(GPIOB18); intr(GPIOB19); | ||
247 | intr(GPIOB20); intr(GPIOB21); intr(GPIOB22); intr(GPIOB23); intr(GPIOB24); | ||
248 | intr(GPIOB25); intr(GPIOB26); intr(GPIOB27); intr(GPIOB28); intr(GPIOB29); | ||
249 | intr(GPIOB30); intr(GPIOB31); | ||
250 | /* GPIO C - 26 pins */ | ||
251 | intr(GPIOC00); intr(GPIOC01); intr(GPIOC02); intr(GPIOC03); intr(GPIOC04); | ||
252 | intr(GPIOC05); intr(GPIOC06); intr(GPIOC07); intr(GPIOC08); intr(GPIOC09); | ||
253 | intr(GPIOC10); intr(GPIOC11); intr(GPIOC12); intr(GPIOC13); intr(GPIOC14); | ||
254 | intr(GPIOC15); intr(GPIOC16); intr(GPIOC17); intr(GPIOC18); intr(GPIOC19); | ||
255 | intr(GPIOC20); intr(GPIOC21); intr(GPIOC22); intr(GPIOC23); intr(GPIOC24); | ||
256 | intr(GPIOC25); | ||
257 | /* GPIO D - 6 pins */ | ||
258 | intr(GPIOD00); intr(GPIOD01); intr(GPIOD02); intr(GPIOD03); intr(GPIOD04); | ||
259 | intr(GPIOD05); | ||
260 | |||
261 | /* OST interrupt -- has no IRQ number since it's got special handling */ | ||
262 | intr(OST); | ||
263 | |||
264 | #undef intr | ||
265 | |||
266 | static void(*const irqvector[])(void) = { | ||
267 | /* ICSR0: 0 - 31 */ | ||
268 | DMIC, AIC, UIRQ, UIRQ, UIRQ, UIRQ, UIRQ, SFC, | ||
269 | SSI0, UIRQ, PDMA, PDMAD, UIRQ, UIRQ, UIRQ, UIRQ, | ||
270 | UIRQ, UIRQ, UIRQ, UIRQ, UIRQ, OTG, UIRQ, AES, | ||
271 | UIRQ, TCU2, TCU1, TCU0, UIRQ, UIRQ, CIM, LCD, | ||
272 | /* ICSR1: 32 - 63 */ | ||
273 | RTC, UIRQ, UIRQ, UIRQ, MSC1, MSC0, SCC, UIRQ, | ||
274 | PCM0, UIRQ, UIRQ, UIRQ, HARB2, UIRQ, HARB0, CPM, | ||
275 | UIRQ, UART2, UART1, UART0, DDR, UIRQ, EFUSE, MAC, | ||
276 | UIRQ, UIRQ, I2C2, I2C1, I2C0, PDMAM, JPEG, UIRQ, | ||
277 | /* GPIO A: 64 - 95 */ | ||
278 | GPIOA00, GPIOA01, GPIOA02, GPIOA03, GPIOA04, GPIOA05, GPIOA06, GPIOA07, | ||
279 | GPIOA08, GPIOA09, GPIOA10, GPIOA11, GPIOA12, GPIOA13, GPIOA14, GPIOA15, | ||
280 | GPIOA16, GPIOA17, GPIOA18, GPIOA19, GPIOA20, GPIOA21, GPIOA22, GPIOA23, | ||
281 | GPIOA24, GPIOA25, GPIOA26, GPIOA27, GPIOA28, GPIOA29, GPIOA30, GPIOA31, | ||
282 | /* GPIO B: 96 - 127 */ | ||
283 | GPIOB00, GPIOB01, GPIOB02, GPIOB03, GPIOB04, GPIOB05, GPIOB06, GPIOB07, | ||
284 | GPIOB08, GPIOB09, GPIOB10, GPIOB11, GPIOB12, GPIOB13, GPIOB14, GPIOB15, | ||
285 | GPIOB16, GPIOB17, GPIOB18, GPIOB19, GPIOB20, GPIOB21, GPIOB22, GPIOB23, | ||
286 | GPIOB24, GPIOB25, GPIOB26, GPIOB27, GPIOB28, GPIOB29, GPIOB30, GPIOB31, | ||
287 | /* GPIO C: 128 - 159 */ | ||
288 | GPIOC00, GPIOC01, GPIOC02, GPIOC03, GPIOC04, GPIOC05, GPIOC06, GPIOC07, | ||
289 | GPIOC08, GPIOC09, GPIOC10, GPIOC11, GPIOC12, GPIOC13, GPIOC14, GPIOC15, | ||
290 | GPIOC16, GPIOC17, GPIOC18, GPIOC19, GPIOC20, GPIOC21, GPIOC22, GPIOC23, | ||
291 | GPIOC24, GPIOC25, UIRQ, UIRQ, UIRQ, UIRQ, UIRQ, UIRQ, | ||
292 | /* GPIO D: 160 - 165 */ | ||
293 | GPIOD00, GPIOD01, GPIOD02, GPIOD03, GPIOD04, GPIOD05, | ||
294 | }; | ||
295 | |||
296 | void system_enable_irq(int irq) | ||
297 | { | ||
298 | if(IRQ_IS_GROUP0(irq)) { | ||
299 | jz_clr(INTC_MSK(0), 1 << IRQ_TO_GROUP0(irq)); | ||
300 | } else if(IRQ_IS_GROUP1(irq)) { | ||
301 | jz_clr(INTC_MSK(1), 1 << IRQ_TO_GROUP1(irq)); | ||
302 | } | ||
303 | } | ||
304 | |||
305 | void system_disable_irq(int irq) | ||
306 | { | ||
307 | if(IRQ_IS_GROUP0(irq)) { | ||
308 | jz_set(INTC_MSK(0), 1 << IRQ_TO_GROUP0(irq)); | ||
309 | } else if(IRQ_IS_GROUP1(irq)) { | ||
310 | jz_set(INTC_MSK(1), 1 << IRQ_TO_GROUP1(irq)); | ||
311 | } | ||
312 | } | ||
313 | |||
314 | static int vector_gpio_irq(int port) | ||
315 | { | ||
316 | int n = find_first_set_bit(REG_GPIO_FLAG(port)); | ||
317 | if(n & 32) | ||
318 | return -1; | ||
319 | |||
320 | jz_clr(GPIO_FLAG(port), 1 << n); | ||
321 | return IRQ_GPIO(port, n); | ||
322 | } | ||
323 | |||
324 | static int vector_irq(void) | ||
325 | { | ||
326 | int n = find_first_set_bit(ipr0); | ||
327 | if(n & 32) { | ||
328 | n = find_first_set_bit(ipr1); | ||
329 | if(n & 32) | ||
330 | return -1; | ||
331 | ipr1 &= ~(1 << n); | ||
332 | n += 32; | ||
333 | } else { | ||
334 | ipr0 &= ~(1 << n); | ||
335 | } | ||
336 | |||
337 | switch(n) { | ||
338 | case IRQ0_GPIO0: n = vector_gpio_irq(GPIO_A); break; | ||
339 | case IRQ0_GPIO1: n = vector_gpio_irq(GPIO_B); break; | ||
340 | case IRQ0_GPIO2: n = vector_gpio_irq(GPIO_C); break; | ||
341 | case IRQ0_GPIO3: n = vector_gpio_irq(GPIO_D); break; | ||
342 | default: break; | ||
343 | } | ||
344 | |||
345 | return n; | ||
346 | } | ||
347 | |||
348 | void intr_handler(unsigned cause) | ||
349 | { | ||
350 | /* OST interrupt is handled separately */ | ||
351 | if(cause & M_CauseIP3) { | ||
352 | OST(); | ||
353 | return; | ||
354 | } | ||
355 | |||
356 | /* Gather pending interrupts */ | ||
357 | ipr0 |= REG_INTC_PND(0); | ||
358 | ipr1 |= REG_INTC_PND(1); | ||
359 | |||
360 | /* Process and dispatch interrupt */ | ||
361 | irq = vector_irq(); | ||
362 | if(irq < 0) | ||
363 | return; | ||
364 | |||
365 | irqvector[irq](); | ||
366 | } | ||
367 | |||
368 | void tlb_refill_handler(void) | ||
369 | { | ||
370 | panicf("TLB refill handler at 0x%08lx! [0x%x]", | ||
371 | read_c0_epc(), read_c0_badvaddr()); | ||
372 | } | ||
373 | |||
374 | #define EXC(x,y) case (x): return (y); | ||
375 | static char* parse_exception(unsigned cause) | ||
376 | { | ||
377 | switch(cause & M_CauseExcCode) | ||
378 | { | ||
379 | EXC(EXC_INT, "Interrupt"); | ||
380 | EXC(EXC_MOD, "TLB Modified"); | ||
381 | EXC(EXC_TLBL, "TLB Exception (Load or Ifetch)"); | ||
382 | EXC(EXC_ADEL, "Address Error (Load or Ifetch)"); | ||
383 | EXC(EXC_ADES, "Address Error (Store)"); | ||
384 | EXC(EXC_TLBS, "TLB Exception (Store)"); | ||
385 | EXC(EXC_IBE, "Instruction Bus Error"); | ||
386 | EXC(EXC_DBE, "Data Bus Error"); | ||
387 | EXC(EXC_SYS, "Syscall"); | ||
388 | EXC(EXC_BP, "Breakpoint"); | ||
389 | EXC(EXC_RI, "Reserved Instruction"); | ||
390 | EXC(EXC_CPU, "Coprocessor Unusable"); | ||
391 | EXC(EXC_OV, "Overflow"); | ||
392 | EXC(EXC_TR, "Trap Instruction"); | ||
393 | EXC(EXC_FPE, "Floating Point Exception"); | ||
394 | EXC(EXC_C2E, "COP2 Exception"); | ||
395 | EXC(EXC_MDMX, "MDMX Exception"); | ||
396 | EXC(EXC_WATCH, "Watch Exception"); | ||
397 | EXC(EXC_MCHECK, "Machine Check Exception"); | ||
398 | EXC(EXC_CacheErr, "Cache error caused re-entry to Debug Mode"); | ||
399 | default: | ||
400 | return 0; | ||
401 | } | ||
402 | } | ||
403 | #undef EXC | ||
404 | |||
405 | void exception_handler(unsigned cause, unsigned epc, unsigned stack_ptr) | ||
406 | { | ||
407 | panicf("Exception occurred: %s [0x%08x] at 0x%08x (stack at 0x%08x)", | ||
408 | parse_exception(cause), read_c0_badvaddr(), epc, stack_ptr); | ||
409 | } | ||
410 | |||
411 | void system_exception_wait(void) | ||
412 | { | ||
413 | #ifdef FIIO_M3K | ||
414 | while(button_read_device() != (BUTTON_POWER|BUTTON_VOL_DOWN)); | ||
415 | #else | ||
416 | while(1); | ||
417 | #endif | ||
418 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/timer-x1000.c b/firmware/target/mips/ingenic_x1000/timer-x1000.c new file mode 100644 index 0000000000..de97cbb3a3 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/timer-x1000.c | |||
@@ -0,0 +1,85 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "timer.h" | ||
23 | #include "x1000/tcu.h" | ||
24 | |||
25 | #define TIMER_CHN 5 | ||
26 | |||
27 | bool timer_set(long cycles, bool start) | ||
28 | { | ||
29 | if(cycles <= 0) | ||
30 | return false; | ||
31 | |||
32 | /* Calculate timer interval */ | ||
33 | unsigned long counter = cycles; | ||
34 | unsigned prescale = 0; | ||
35 | while(counter > 0xffff && prescale < 5) { | ||
36 | counter /= 4; | ||
37 | prescale += 1; | ||
38 | } | ||
39 | |||
40 | /* Duration too long */ | ||
41 | if(counter > 0xffff) | ||
42 | return false; | ||
43 | |||
44 | /* Unregister old function */ | ||
45 | if(start && pfn_unregister) { | ||
46 | pfn_unregister(); | ||
47 | pfn_unregister = 0; | ||
48 | } | ||
49 | |||
50 | /* Configure the timer */ | ||
51 | jz_clr(TCU_STOP, 1 << TIMER_CHN); | ||
52 | jz_clr(TCU_ENABLE, 1 << TIMER_CHN); | ||
53 | jz_overwritef(TCU_CTRL(TIMER_CHN), SOURCE_V(EXT), PRESCALE(prescale)); | ||
54 | jz_write(TCU_CMP_FULL(TIMER_CHN), counter); | ||
55 | jz_write(TCU_CMP_HALF(TIMER_CHN), 0); | ||
56 | jz_clr(TCU_FLAG, 1 << TIMER_CHN); | ||
57 | jz_clr(TCU_MASK, 1 << TIMER_CHN); | ||
58 | |||
59 | if(start) | ||
60 | return timer_start(); | ||
61 | else | ||
62 | return true; | ||
63 | } | ||
64 | |||
65 | bool timer_start(void) | ||
66 | { | ||
67 | jz_set(TCU_ENABLE, 1 << TIMER_CHN); | ||
68 | return true; | ||
69 | } | ||
70 | |||
71 | void timer_stop(void) | ||
72 | { | ||
73 | jz_clr(TCU_ENABLE, 1 << TIMER_CHN); | ||
74 | jz_set(TCU_MASK, 1 << TIMER_CHN); | ||
75 | jz_clr(TCU_FLAG, 1 << TIMER_CHN); | ||
76 | jz_set(TCU_STOP, 1 << TIMER_CHN); | ||
77 | } | ||
78 | |||
79 | void TCU1(void) | ||
80 | { | ||
81 | jz_clr(TCU_FLAG, 1 << TIMER_CHN); | ||
82 | |||
83 | if(pfn_timer) | ||
84 | pfn_timer(); | ||
85 | } | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/aic.h b/firmware/target/mips/ingenic_x1000/x1000/aic.h new file mode 100644 index 0000000000..e9c68511d7 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/aic.h | |||
@@ -0,0 +1,359 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_AIC_H__ | ||
25 | #define __HEADERGEN_AIC_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_AIC_CFG jz_reg(AIC_CFG) | ||
30 | #define JA_AIC_CFG (0xb0020000 + 0x0) | ||
31 | #define JT_AIC_CFG JIO_32_RW | ||
32 | #define JN_AIC_CFG AIC_CFG | ||
33 | #define JI_AIC_CFG | ||
34 | #define BP_AIC_CFG_RFTH 24 | ||
35 | #define BM_AIC_CFG_RFTH 0xf000000 | ||
36 | #define BF_AIC_CFG_RFTH(v) (((v) & 0xf) << 24) | ||
37 | #define BFM_AIC_CFG_RFTH(v) BM_AIC_CFG_RFTH | ||
38 | #define BF_AIC_CFG_RFTH_V(e) BF_AIC_CFG_RFTH(BV_AIC_CFG_RFTH__##e) | ||
39 | #define BFM_AIC_CFG_RFTH_V(v) BM_AIC_CFG_RFTH | ||
40 | #define BP_AIC_CFG_TFTH 16 | ||
41 | #define BM_AIC_CFG_TFTH 0x1f0000 | ||
42 | #define BF_AIC_CFG_TFTH(v) (((v) & 0x1f) << 16) | ||
43 | #define BFM_AIC_CFG_TFTH(v) BM_AIC_CFG_TFTH | ||
44 | #define BF_AIC_CFG_TFTH_V(e) BF_AIC_CFG_TFTH(BV_AIC_CFG_TFTH__##e) | ||
45 | #define BFM_AIC_CFG_TFTH_V(v) BM_AIC_CFG_TFTH | ||
46 | #define BP_AIC_CFG_MSB 12 | ||
47 | #define BM_AIC_CFG_MSB 0x1000 | ||
48 | #define BF_AIC_CFG_MSB(v) (((v) & 0x1) << 12) | ||
49 | #define BFM_AIC_CFG_MSB(v) BM_AIC_CFG_MSB | ||
50 | #define BF_AIC_CFG_MSB_V(e) BF_AIC_CFG_MSB(BV_AIC_CFG_MSB__##e) | ||
51 | #define BFM_AIC_CFG_MSB_V(v) BM_AIC_CFG_MSB | ||
52 | #define BP_AIC_CFG_IBCKD 10 | ||
53 | #define BM_AIC_CFG_IBCKD 0x400 | ||
54 | #define BF_AIC_CFG_IBCKD(v) (((v) & 0x1) << 10) | ||
55 | #define BFM_AIC_CFG_IBCKD(v) BM_AIC_CFG_IBCKD | ||
56 | #define BF_AIC_CFG_IBCKD_V(e) BF_AIC_CFG_IBCKD(BV_AIC_CFG_IBCKD__##e) | ||
57 | #define BFM_AIC_CFG_IBCKD_V(v) BM_AIC_CFG_IBCKD | ||
58 | #define BP_AIC_CFG_ISYNCD 9 | ||
59 | #define BM_AIC_CFG_ISYNCD 0x200 | ||
60 | #define BF_AIC_CFG_ISYNCD(v) (((v) & 0x1) << 9) | ||
61 | #define BFM_AIC_CFG_ISYNCD(v) BM_AIC_CFG_ISYNCD | ||
62 | #define BF_AIC_CFG_ISYNCD_V(e) BF_AIC_CFG_ISYNCD(BV_AIC_CFG_ISYNCD__##e) | ||
63 | #define BFM_AIC_CFG_ISYNCD_V(v) BM_AIC_CFG_ISYNCD | ||
64 | #define BP_AIC_CFG_DMODE 8 | ||
65 | #define BM_AIC_CFG_DMODE 0x100 | ||
66 | #define BF_AIC_CFG_DMODE(v) (((v) & 0x1) << 8) | ||
67 | #define BFM_AIC_CFG_DMODE(v) BM_AIC_CFG_DMODE | ||
68 | #define BF_AIC_CFG_DMODE_V(e) BF_AIC_CFG_DMODE(BV_AIC_CFG_DMODE__##e) | ||
69 | #define BFM_AIC_CFG_DMODE_V(v) BM_AIC_CFG_DMODE | ||
70 | #define BP_AIC_CFG_CDC_SLAVE 7 | ||
71 | #define BM_AIC_CFG_CDC_SLAVE 0x80 | ||
72 | #define BF_AIC_CFG_CDC_SLAVE(v) (((v) & 0x1) << 7) | ||
73 | #define BFM_AIC_CFG_CDC_SLAVE(v) BM_AIC_CFG_CDC_SLAVE | ||
74 | #define BF_AIC_CFG_CDC_SLAVE_V(e) BF_AIC_CFG_CDC_SLAVE(BV_AIC_CFG_CDC_SLAVE__##e) | ||
75 | #define BFM_AIC_CFG_CDC_SLAVE_V(v) BM_AIC_CFG_CDC_SLAVE | ||
76 | #define BP_AIC_CFG_LSMP 6 | ||
77 | #define BM_AIC_CFG_LSMP 0x40 | ||
78 | #define BF_AIC_CFG_LSMP(v) (((v) & 0x1) << 6) | ||
79 | #define BFM_AIC_CFG_LSMP(v) BM_AIC_CFG_LSMP | ||
80 | #define BF_AIC_CFG_LSMP_V(e) BF_AIC_CFG_LSMP(BV_AIC_CFG_LSMP__##e) | ||
81 | #define BFM_AIC_CFG_LSMP_V(v) BM_AIC_CFG_LSMP | ||
82 | #define BP_AIC_CFG_ICDC 5 | ||
83 | #define BM_AIC_CFG_ICDC 0x20 | ||
84 | #define BF_AIC_CFG_ICDC(v) (((v) & 0x1) << 5) | ||
85 | #define BFM_AIC_CFG_ICDC(v) BM_AIC_CFG_ICDC | ||
86 | #define BF_AIC_CFG_ICDC_V(e) BF_AIC_CFG_ICDC(BV_AIC_CFG_ICDC__##e) | ||
87 | #define BFM_AIC_CFG_ICDC_V(v) BM_AIC_CFG_ICDC | ||
88 | #define BP_AIC_CFG_AUSEL 4 | ||
89 | #define BM_AIC_CFG_AUSEL 0x10 | ||
90 | #define BF_AIC_CFG_AUSEL(v) (((v) & 0x1) << 4) | ||
91 | #define BFM_AIC_CFG_AUSEL(v) BM_AIC_CFG_AUSEL | ||
92 | #define BF_AIC_CFG_AUSEL_V(e) BF_AIC_CFG_AUSEL(BV_AIC_CFG_AUSEL__##e) | ||
93 | #define BFM_AIC_CFG_AUSEL_V(v) BM_AIC_CFG_AUSEL | ||
94 | #define BP_AIC_CFG_RST 3 | ||
95 | #define BM_AIC_CFG_RST 0x8 | ||
96 | #define BF_AIC_CFG_RST(v) (((v) & 0x1) << 3) | ||
97 | #define BFM_AIC_CFG_RST(v) BM_AIC_CFG_RST | ||
98 | #define BF_AIC_CFG_RST_V(e) BF_AIC_CFG_RST(BV_AIC_CFG_RST__##e) | ||
99 | #define BFM_AIC_CFG_RST_V(v) BM_AIC_CFG_RST | ||
100 | #define BP_AIC_CFG_BCKD 2 | ||
101 | #define BM_AIC_CFG_BCKD 0x4 | ||
102 | #define BF_AIC_CFG_BCKD(v) (((v) & 0x1) << 2) | ||
103 | #define BFM_AIC_CFG_BCKD(v) BM_AIC_CFG_BCKD | ||
104 | #define BF_AIC_CFG_BCKD_V(e) BF_AIC_CFG_BCKD(BV_AIC_CFG_BCKD__##e) | ||
105 | #define BFM_AIC_CFG_BCKD_V(v) BM_AIC_CFG_BCKD | ||
106 | #define BP_AIC_CFG_SYNCD 1 | ||
107 | #define BM_AIC_CFG_SYNCD 0x2 | ||
108 | #define BF_AIC_CFG_SYNCD(v) (((v) & 0x1) << 1) | ||
109 | #define BFM_AIC_CFG_SYNCD(v) BM_AIC_CFG_SYNCD | ||
110 | #define BF_AIC_CFG_SYNCD_V(e) BF_AIC_CFG_SYNCD(BV_AIC_CFG_SYNCD__##e) | ||
111 | #define BFM_AIC_CFG_SYNCD_V(v) BM_AIC_CFG_SYNCD | ||
112 | #define BP_AIC_CFG_ENABLE 0 | ||
113 | #define BM_AIC_CFG_ENABLE 0x1 | ||
114 | #define BF_AIC_CFG_ENABLE(v) (((v) & 0x1) << 0) | ||
115 | #define BFM_AIC_CFG_ENABLE(v) BM_AIC_CFG_ENABLE | ||
116 | #define BF_AIC_CFG_ENABLE_V(e) BF_AIC_CFG_ENABLE(BV_AIC_CFG_ENABLE__##e) | ||
117 | #define BFM_AIC_CFG_ENABLE_V(v) BM_AIC_CFG_ENABLE | ||
118 | |||
119 | #define REG_AIC_CCR jz_reg(AIC_CCR) | ||
120 | #define JA_AIC_CCR (0xb0020000 + 0x4) | ||
121 | #define JT_AIC_CCR JIO_32_RW | ||
122 | #define JN_AIC_CCR AIC_CCR | ||
123 | #define JI_AIC_CCR | ||
124 | #define BP_AIC_CCR_CHANNEL 24 | ||
125 | #define BM_AIC_CCR_CHANNEL 0x7000000 | ||
126 | #define BF_AIC_CCR_CHANNEL(v) (((v) & 0x7) << 24) | ||
127 | #define BFM_AIC_CCR_CHANNEL(v) BM_AIC_CCR_CHANNEL | ||
128 | #define BF_AIC_CCR_CHANNEL_V(e) BF_AIC_CCR_CHANNEL(BV_AIC_CCR_CHANNEL__##e) | ||
129 | #define BFM_AIC_CCR_CHANNEL_V(v) BM_AIC_CCR_CHANNEL | ||
130 | #define BP_AIC_CCR_OSS 19 | ||
131 | #define BM_AIC_CCR_OSS 0x380000 | ||
132 | #define BF_AIC_CCR_OSS(v) (((v) & 0x7) << 19) | ||
133 | #define BFM_AIC_CCR_OSS(v) BM_AIC_CCR_OSS | ||
134 | #define BF_AIC_CCR_OSS_V(e) BF_AIC_CCR_OSS(BV_AIC_CCR_OSS__##e) | ||
135 | #define BFM_AIC_CCR_OSS_V(v) BM_AIC_CCR_OSS | ||
136 | #define BP_AIC_CCR_ISS 16 | ||
137 | #define BM_AIC_CCR_ISS 0x70000 | ||
138 | #define BF_AIC_CCR_ISS(v) (((v) & 0x7) << 16) | ||
139 | #define BFM_AIC_CCR_ISS(v) BM_AIC_CCR_ISS | ||
140 | #define BF_AIC_CCR_ISS_V(e) BF_AIC_CCR_ISS(BV_AIC_CCR_ISS__##e) | ||
141 | #define BFM_AIC_CCR_ISS_V(v) BM_AIC_CCR_ISS | ||
142 | #define BP_AIC_CCR_PACK16 28 | ||
143 | #define BM_AIC_CCR_PACK16 0x10000000 | ||
144 | #define BF_AIC_CCR_PACK16(v) (((v) & 0x1) << 28) | ||
145 | #define BFM_AIC_CCR_PACK16(v) BM_AIC_CCR_PACK16 | ||
146 | #define BF_AIC_CCR_PACK16_V(e) BF_AIC_CCR_PACK16(BV_AIC_CCR_PACK16__##e) | ||
147 | #define BFM_AIC_CCR_PACK16_V(v) BM_AIC_CCR_PACK16 | ||
148 | #define BP_AIC_CCR_RDMS 15 | ||
149 | #define BM_AIC_CCR_RDMS 0x8000 | ||
150 | #define BF_AIC_CCR_RDMS(v) (((v) & 0x1) << 15) | ||
151 | #define BFM_AIC_CCR_RDMS(v) BM_AIC_CCR_RDMS | ||
152 | #define BF_AIC_CCR_RDMS_V(e) BF_AIC_CCR_RDMS(BV_AIC_CCR_RDMS__##e) | ||
153 | #define BFM_AIC_CCR_RDMS_V(v) BM_AIC_CCR_RDMS | ||
154 | #define BP_AIC_CCR_TDMS 14 | ||
155 | #define BM_AIC_CCR_TDMS 0x4000 | ||
156 | #define BF_AIC_CCR_TDMS(v) (((v) & 0x1) << 14) | ||
157 | #define BFM_AIC_CCR_TDMS(v) BM_AIC_CCR_TDMS | ||
158 | #define BF_AIC_CCR_TDMS_V(e) BF_AIC_CCR_TDMS(BV_AIC_CCR_TDMS__##e) | ||
159 | #define BFM_AIC_CCR_TDMS_V(v) BM_AIC_CCR_TDMS | ||
160 | #define BP_AIC_CCR_M2S 11 | ||
161 | #define BM_AIC_CCR_M2S 0x800 | ||
162 | #define BF_AIC_CCR_M2S(v) (((v) & 0x1) << 11) | ||
163 | #define BFM_AIC_CCR_M2S(v) BM_AIC_CCR_M2S | ||
164 | #define BF_AIC_CCR_M2S_V(e) BF_AIC_CCR_M2S(BV_AIC_CCR_M2S__##e) | ||
165 | #define BFM_AIC_CCR_M2S_V(v) BM_AIC_CCR_M2S | ||
166 | #define BP_AIC_CCR_ENDSW 10 | ||
167 | #define BM_AIC_CCR_ENDSW 0x400 | ||
168 | #define BF_AIC_CCR_ENDSW(v) (((v) & 0x1) << 10) | ||
169 | #define BFM_AIC_CCR_ENDSW(v) BM_AIC_CCR_ENDSW | ||
170 | #define BF_AIC_CCR_ENDSW_V(e) BF_AIC_CCR_ENDSW(BV_AIC_CCR_ENDSW__##e) | ||
171 | #define BFM_AIC_CCR_ENDSW_V(v) BM_AIC_CCR_ENDSW | ||
172 | #define BP_AIC_CCR_ASVTSU 9 | ||
173 | #define BM_AIC_CCR_ASVTSU 0x200 | ||
174 | #define BF_AIC_CCR_ASVTSU(v) (((v) & 0x1) << 9) | ||
175 | #define BFM_AIC_CCR_ASVTSU(v) BM_AIC_CCR_ASVTSU | ||
176 | #define BF_AIC_CCR_ASVTSU_V(e) BF_AIC_CCR_ASVTSU(BV_AIC_CCR_ASVTSU__##e) | ||
177 | #define BFM_AIC_CCR_ASVTSU_V(v) BM_AIC_CCR_ASVTSU | ||
178 | #define BP_AIC_CCR_TFLUSH 8 | ||
179 | #define BM_AIC_CCR_TFLUSH 0x100 | ||
180 | #define BF_AIC_CCR_TFLUSH(v) (((v) & 0x1) << 8) | ||
181 | #define BFM_AIC_CCR_TFLUSH(v) BM_AIC_CCR_TFLUSH | ||
182 | #define BF_AIC_CCR_TFLUSH_V(e) BF_AIC_CCR_TFLUSH(BV_AIC_CCR_TFLUSH__##e) | ||
183 | #define BFM_AIC_CCR_TFLUSH_V(v) BM_AIC_CCR_TFLUSH | ||
184 | #define BP_AIC_CCR_RFLUSH 7 | ||
185 | #define BM_AIC_CCR_RFLUSH 0x80 | ||
186 | #define BF_AIC_CCR_RFLUSH(v) (((v) & 0x1) << 7) | ||
187 | #define BFM_AIC_CCR_RFLUSH(v) BM_AIC_CCR_RFLUSH | ||
188 | #define BF_AIC_CCR_RFLUSH_V(e) BF_AIC_CCR_RFLUSH(BV_AIC_CCR_RFLUSH__##e) | ||
189 | #define BFM_AIC_CCR_RFLUSH_V(v) BM_AIC_CCR_RFLUSH | ||
190 | #define BP_AIC_CCR_EROR 6 | ||
191 | #define BM_AIC_CCR_EROR 0x40 | ||
192 | #define BF_AIC_CCR_EROR(v) (((v) & 0x1) << 6) | ||
193 | #define BFM_AIC_CCR_EROR(v) BM_AIC_CCR_EROR | ||
194 | #define BF_AIC_CCR_EROR_V(e) BF_AIC_CCR_EROR(BV_AIC_CCR_EROR__##e) | ||
195 | #define BFM_AIC_CCR_EROR_V(v) BM_AIC_CCR_EROR | ||
196 | #define BP_AIC_CCR_ETUR 5 | ||
197 | #define BM_AIC_CCR_ETUR 0x20 | ||
198 | #define BF_AIC_CCR_ETUR(v) (((v) & 0x1) << 5) | ||
199 | #define BFM_AIC_CCR_ETUR(v) BM_AIC_CCR_ETUR | ||
200 | #define BF_AIC_CCR_ETUR_V(e) BF_AIC_CCR_ETUR(BV_AIC_CCR_ETUR__##e) | ||
201 | #define BFM_AIC_CCR_ETUR_V(v) BM_AIC_CCR_ETUR | ||
202 | #define BP_AIC_CCR_ERFS 4 | ||
203 | #define BM_AIC_CCR_ERFS 0x10 | ||
204 | #define BF_AIC_CCR_ERFS(v) (((v) & 0x1) << 4) | ||
205 | #define BFM_AIC_CCR_ERFS(v) BM_AIC_CCR_ERFS | ||
206 | #define BF_AIC_CCR_ERFS_V(e) BF_AIC_CCR_ERFS(BV_AIC_CCR_ERFS__##e) | ||
207 | #define BFM_AIC_CCR_ERFS_V(v) BM_AIC_CCR_ERFS | ||
208 | #define BP_AIC_CCR_ETFS 3 | ||
209 | #define BM_AIC_CCR_ETFS 0x8 | ||
210 | #define BF_AIC_CCR_ETFS(v) (((v) & 0x1) << 3) | ||
211 | #define BFM_AIC_CCR_ETFS(v) BM_AIC_CCR_ETFS | ||
212 | #define BF_AIC_CCR_ETFS_V(e) BF_AIC_CCR_ETFS(BV_AIC_CCR_ETFS__##e) | ||
213 | #define BFM_AIC_CCR_ETFS_V(v) BM_AIC_CCR_ETFS | ||
214 | #define BP_AIC_CCR_ENLBF 2 | ||
215 | #define BM_AIC_CCR_ENLBF 0x4 | ||
216 | #define BF_AIC_CCR_ENLBF(v) (((v) & 0x1) << 2) | ||
217 | #define BFM_AIC_CCR_ENLBF(v) BM_AIC_CCR_ENLBF | ||
218 | #define BF_AIC_CCR_ENLBF_V(e) BF_AIC_CCR_ENLBF(BV_AIC_CCR_ENLBF__##e) | ||
219 | #define BFM_AIC_CCR_ENLBF_V(v) BM_AIC_CCR_ENLBF | ||
220 | #define BP_AIC_CCR_ERPL 1 | ||
221 | #define BM_AIC_CCR_ERPL 0x2 | ||
222 | #define BF_AIC_CCR_ERPL(v) (((v) & 0x1) << 1) | ||
223 | #define BFM_AIC_CCR_ERPL(v) BM_AIC_CCR_ERPL | ||
224 | #define BF_AIC_CCR_ERPL_V(e) BF_AIC_CCR_ERPL(BV_AIC_CCR_ERPL__##e) | ||
225 | #define BFM_AIC_CCR_ERPL_V(v) BM_AIC_CCR_ERPL | ||
226 | #define BP_AIC_CCR_EREC 0 | ||
227 | #define BM_AIC_CCR_EREC 0x1 | ||
228 | #define BF_AIC_CCR_EREC(v) (((v) & 0x1) << 0) | ||
229 | #define BFM_AIC_CCR_EREC(v) BM_AIC_CCR_EREC | ||
230 | #define BF_AIC_CCR_EREC_V(e) BF_AIC_CCR_EREC(BV_AIC_CCR_EREC__##e) | ||
231 | #define BFM_AIC_CCR_EREC_V(v) BM_AIC_CCR_EREC | ||
232 | |||
233 | #define REG_AIC_I2SCR jz_reg(AIC_I2SCR) | ||
234 | #define JA_AIC_I2SCR (0xb0020000 + 0x10) | ||
235 | #define JT_AIC_I2SCR JIO_32_RW | ||
236 | #define JN_AIC_I2SCR AIC_I2SCR | ||
237 | #define JI_AIC_I2SCR | ||
238 | #define BP_AIC_I2SCR_RFIRST 17 | ||
239 | #define BM_AIC_I2SCR_RFIRST 0x20000 | ||
240 | #define BF_AIC_I2SCR_RFIRST(v) (((v) & 0x1) << 17) | ||
241 | #define BFM_AIC_I2SCR_RFIRST(v) BM_AIC_I2SCR_RFIRST | ||
242 | #define BF_AIC_I2SCR_RFIRST_V(e) BF_AIC_I2SCR_RFIRST(BV_AIC_I2SCR_RFIRST__##e) | ||
243 | #define BFM_AIC_I2SCR_RFIRST_V(v) BM_AIC_I2SCR_RFIRST | ||
244 | #define BP_AIC_I2SCR_SWLH 16 | ||
245 | #define BM_AIC_I2SCR_SWLH 0x10000 | ||
246 | #define BF_AIC_I2SCR_SWLH(v) (((v) & 0x1) << 16) | ||
247 | #define BFM_AIC_I2SCR_SWLH(v) BM_AIC_I2SCR_SWLH | ||
248 | #define BF_AIC_I2SCR_SWLH_V(e) BF_AIC_I2SCR_SWLH(BV_AIC_I2SCR_SWLH__##e) | ||
249 | #define BFM_AIC_I2SCR_SWLH_V(v) BM_AIC_I2SCR_SWLH | ||
250 | #define BP_AIC_I2SCR_ISTPBK 13 | ||
251 | #define BM_AIC_I2SCR_ISTPBK 0x2000 | ||
252 | #define BF_AIC_I2SCR_ISTPBK(v) (((v) & 0x1) << 13) | ||
253 | #define BFM_AIC_I2SCR_ISTPBK(v) BM_AIC_I2SCR_ISTPBK | ||
254 | #define BF_AIC_I2SCR_ISTPBK_V(e) BF_AIC_I2SCR_ISTPBK(BV_AIC_I2SCR_ISTPBK__##e) | ||
255 | #define BFM_AIC_I2SCR_ISTPBK_V(v) BM_AIC_I2SCR_ISTPBK | ||
256 | #define BP_AIC_I2SCR_STPBK 12 | ||
257 | #define BM_AIC_I2SCR_STPBK 0x1000 | ||
258 | #define BF_AIC_I2SCR_STPBK(v) (((v) & 0x1) << 12) | ||
259 | #define BFM_AIC_I2SCR_STPBK(v) BM_AIC_I2SCR_STPBK | ||
260 | #define BF_AIC_I2SCR_STPBK_V(e) BF_AIC_I2SCR_STPBK(BV_AIC_I2SCR_STPBK__##e) | ||
261 | #define BFM_AIC_I2SCR_STPBK_V(v) BM_AIC_I2SCR_STPBK | ||
262 | #define BP_AIC_I2SCR_ESCLK 4 | ||
263 | #define BM_AIC_I2SCR_ESCLK 0x10 | ||
264 | #define BF_AIC_I2SCR_ESCLK(v) (((v) & 0x1) << 4) | ||
265 | #define BFM_AIC_I2SCR_ESCLK(v) BM_AIC_I2SCR_ESCLK | ||
266 | #define BF_AIC_I2SCR_ESCLK_V(e) BF_AIC_I2SCR_ESCLK(BV_AIC_I2SCR_ESCLK__##e) | ||
267 | #define BFM_AIC_I2SCR_ESCLK_V(v) BM_AIC_I2SCR_ESCLK | ||
268 | #define BP_AIC_I2SCR_AMSL 0 | ||
269 | #define BM_AIC_I2SCR_AMSL 0x1 | ||
270 | #define BF_AIC_I2SCR_AMSL(v) (((v) & 0x1) << 0) | ||
271 | #define BFM_AIC_I2SCR_AMSL(v) BM_AIC_I2SCR_AMSL | ||
272 | #define BF_AIC_I2SCR_AMSL_V(e) BF_AIC_I2SCR_AMSL(BV_AIC_I2SCR_AMSL__##e) | ||
273 | #define BFM_AIC_I2SCR_AMSL_V(v) BM_AIC_I2SCR_AMSL | ||
274 | |||
275 | #define REG_AIC_SR jz_reg(AIC_SR) | ||
276 | #define JA_AIC_SR (0xb0020000 + 0x14) | ||
277 | #define JT_AIC_SR JIO_32_RW | ||
278 | #define JN_AIC_SR AIC_SR | ||
279 | #define JI_AIC_SR | ||
280 | #define BP_AIC_SR_RFL 24 | ||
281 | #define BM_AIC_SR_RFL 0x3f000000 | ||
282 | #define BF_AIC_SR_RFL(v) (((v) & 0x3f) << 24) | ||
283 | #define BFM_AIC_SR_RFL(v) BM_AIC_SR_RFL | ||
284 | #define BF_AIC_SR_RFL_V(e) BF_AIC_SR_RFL(BV_AIC_SR_RFL__##e) | ||
285 | #define BFM_AIC_SR_RFL_V(v) BM_AIC_SR_RFL | ||
286 | #define BP_AIC_SR_TFL 8 | ||
287 | #define BM_AIC_SR_TFL 0x3f00 | ||
288 | #define BF_AIC_SR_TFL(v) (((v) & 0x3f) << 8) | ||
289 | #define BFM_AIC_SR_TFL(v) BM_AIC_SR_TFL | ||
290 | #define BF_AIC_SR_TFL_V(e) BF_AIC_SR_TFL(BV_AIC_SR_TFL__##e) | ||
291 | #define BFM_AIC_SR_TFL_V(v) BM_AIC_SR_TFL | ||
292 | #define BP_AIC_SR_ROR 6 | ||
293 | #define BM_AIC_SR_ROR 0x40 | ||
294 | #define BF_AIC_SR_ROR(v) (((v) & 0x1) << 6) | ||
295 | #define BFM_AIC_SR_ROR(v) BM_AIC_SR_ROR | ||
296 | #define BF_AIC_SR_ROR_V(e) BF_AIC_SR_ROR(BV_AIC_SR_ROR__##e) | ||
297 | #define BFM_AIC_SR_ROR_V(v) BM_AIC_SR_ROR | ||
298 | #define BP_AIC_SR_TUR 5 | ||
299 | #define BM_AIC_SR_TUR 0x20 | ||
300 | #define BF_AIC_SR_TUR(v) (((v) & 0x1) << 5) | ||
301 | #define BFM_AIC_SR_TUR(v) BM_AIC_SR_TUR | ||
302 | #define BF_AIC_SR_TUR_V(e) BF_AIC_SR_TUR(BV_AIC_SR_TUR__##e) | ||
303 | #define BFM_AIC_SR_TUR_V(v) BM_AIC_SR_TUR | ||
304 | #define BP_AIC_SR_RFS 4 | ||
305 | #define BM_AIC_SR_RFS 0x10 | ||
306 | #define BF_AIC_SR_RFS(v) (((v) & 0x1) << 4) | ||
307 | #define BFM_AIC_SR_RFS(v) BM_AIC_SR_RFS | ||
308 | #define BF_AIC_SR_RFS_V(e) BF_AIC_SR_RFS(BV_AIC_SR_RFS__##e) | ||
309 | #define BFM_AIC_SR_RFS_V(v) BM_AIC_SR_RFS | ||
310 | #define BP_AIC_SR_TFS 3 | ||
311 | #define BM_AIC_SR_TFS 0x8 | ||
312 | #define BF_AIC_SR_TFS(v) (((v) & 0x1) << 3) | ||
313 | #define BFM_AIC_SR_TFS(v) BM_AIC_SR_TFS | ||
314 | #define BF_AIC_SR_TFS_V(e) BF_AIC_SR_TFS(BV_AIC_SR_TFS__##e) | ||
315 | #define BFM_AIC_SR_TFS_V(v) BM_AIC_SR_TFS | ||
316 | |||
317 | #define REG_AIC_I2SSR jz_reg(AIC_I2SSR) | ||
318 | #define JA_AIC_I2SSR (0xb0020000 + 0x1c) | ||
319 | #define JT_AIC_I2SSR JIO_32_RW | ||
320 | #define JN_AIC_I2SSR AIC_I2SSR | ||
321 | #define JI_AIC_I2SSR | ||
322 | #define BP_AIC_I2SSR_CHBSY 5 | ||
323 | #define BM_AIC_I2SSR_CHBSY 0x20 | ||
324 | #define BF_AIC_I2SSR_CHBSY(v) (((v) & 0x1) << 5) | ||
325 | #define BFM_AIC_I2SSR_CHBSY(v) BM_AIC_I2SSR_CHBSY | ||
326 | #define BF_AIC_I2SSR_CHBSY_V(e) BF_AIC_I2SSR_CHBSY(BV_AIC_I2SSR_CHBSY__##e) | ||
327 | #define BFM_AIC_I2SSR_CHBSY_V(v) BM_AIC_I2SSR_CHBSY | ||
328 | #define BP_AIC_I2SSR_TBSY 4 | ||
329 | #define BM_AIC_I2SSR_TBSY 0x10 | ||
330 | #define BF_AIC_I2SSR_TBSY(v) (((v) & 0x1) << 4) | ||
331 | #define BFM_AIC_I2SSR_TBSY(v) BM_AIC_I2SSR_TBSY | ||
332 | #define BF_AIC_I2SSR_TBSY_V(e) BF_AIC_I2SSR_TBSY(BV_AIC_I2SSR_TBSY__##e) | ||
333 | #define BFM_AIC_I2SSR_TBSY_V(v) BM_AIC_I2SSR_TBSY | ||
334 | #define BP_AIC_I2SSR_RBSY 3 | ||
335 | #define BM_AIC_I2SSR_RBSY 0x8 | ||
336 | #define BF_AIC_I2SSR_RBSY(v) (((v) & 0x1) << 3) | ||
337 | #define BFM_AIC_I2SSR_RBSY(v) BM_AIC_I2SSR_RBSY | ||
338 | #define BF_AIC_I2SSR_RBSY_V(e) BF_AIC_I2SSR_RBSY(BV_AIC_I2SSR_RBSY__##e) | ||
339 | #define BFM_AIC_I2SSR_RBSY_V(v) BM_AIC_I2SSR_RBSY | ||
340 | #define BP_AIC_I2SSR_BSY 2 | ||
341 | #define BM_AIC_I2SSR_BSY 0x4 | ||
342 | #define BF_AIC_I2SSR_BSY(v) (((v) & 0x1) << 2) | ||
343 | #define BFM_AIC_I2SSR_BSY(v) BM_AIC_I2SSR_BSY | ||
344 | #define BF_AIC_I2SSR_BSY_V(e) BF_AIC_I2SSR_BSY(BV_AIC_I2SSR_BSY__##e) | ||
345 | #define BFM_AIC_I2SSR_BSY_V(v) BM_AIC_I2SSR_BSY | ||
346 | |||
347 | #define REG_AIC_I2SDIV jz_reg(AIC_I2SDIV) | ||
348 | #define JA_AIC_I2SDIV (0xb0020000 + 0x30) | ||
349 | #define JT_AIC_I2SDIV JIO_32_RW | ||
350 | #define JN_AIC_I2SDIV AIC_I2SDIV | ||
351 | #define JI_AIC_I2SDIV | ||
352 | |||
353 | #define REG_AIC_DR jz_reg(AIC_DR) | ||
354 | #define JA_AIC_DR (0xb0020000 + 0x34) | ||
355 | #define JT_AIC_DR JIO_32_RW | ||
356 | #define JN_AIC_DR AIC_DR | ||
357 | #define JI_AIC_DR | ||
358 | |||
359 | #endif /* __HEADERGEN_AIC_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/cpm.h b/firmware/target/mips/ingenic_x1000/x1000/cpm.h new file mode 100644 index 0000000000..752d270f20 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/cpm.h | |||
@@ -0,0 +1,896 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_CPM_H__ | ||
25 | #define __HEADERGEN_CPM_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_CPM_CCR jz_reg(CPM_CCR) | ||
30 | #define JA_CPM_CCR (0xb0000000 + 0x0) | ||
31 | #define JT_CPM_CCR JIO_32_RW | ||
32 | #define JN_CPM_CCR CPM_CCR | ||
33 | #define JI_CPM_CCR | ||
34 | #define BP_CPM_CCR_SEL_SRC 30 | ||
35 | #define BM_CPM_CCR_SEL_SRC 0xc0000000 | ||
36 | #define BV_CPM_CCR_SEL_SRC__STOP 0x0 | ||
37 | #define BV_CPM_CCR_SEL_SRC__EXCLK 0x1 | ||
38 | #define BV_CPM_CCR_SEL_SRC__APLL 0x2 | ||
39 | #define BF_CPM_CCR_SEL_SRC(v) (((v) & 0x3) << 30) | ||
40 | #define BFM_CPM_CCR_SEL_SRC(v) BM_CPM_CCR_SEL_SRC | ||
41 | #define BF_CPM_CCR_SEL_SRC_V(e) BF_CPM_CCR_SEL_SRC(BV_CPM_CCR_SEL_SRC__##e) | ||
42 | #define BFM_CPM_CCR_SEL_SRC_V(v) BM_CPM_CCR_SEL_SRC | ||
43 | #define BP_CPM_CCR_SEL_CPLL 28 | ||
44 | #define BM_CPM_CCR_SEL_CPLL 0x30000000 | ||
45 | #define BV_CPM_CCR_SEL_CPLL__STOP 0x0 | ||
46 | #define BV_CPM_CCR_SEL_CPLL__SCLK_A 0x1 | ||
47 | #define BV_CPM_CCR_SEL_CPLL__MPLL 0x2 | ||
48 | #define BF_CPM_CCR_SEL_CPLL(v) (((v) & 0x3) << 28) | ||
49 | #define BFM_CPM_CCR_SEL_CPLL(v) BM_CPM_CCR_SEL_CPLL | ||
50 | #define BF_CPM_CCR_SEL_CPLL_V(e) BF_CPM_CCR_SEL_CPLL(BV_CPM_CCR_SEL_CPLL__##e) | ||
51 | #define BFM_CPM_CCR_SEL_CPLL_V(v) BM_CPM_CCR_SEL_CPLL | ||
52 | #define BP_CPM_CCR_SEL_H0PLL 26 | ||
53 | #define BM_CPM_CCR_SEL_H0PLL 0xc000000 | ||
54 | #define BV_CPM_CCR_SEL_H0PLL__STOP 0x0 | ||
55 | #define BV_CPM_CCR_SEL_H0PLL__SCLK_A 0x1 | ||
56 | #define BV_CPM_CCR_SEL_H0PLL__MPLL 0x2 | ||
57 | #define BF_CPM_CCR_SEL_H0PLL(v) (((v) & 0x3) << 26) | ||
58 | #define BFM_CPM_CCR_SEL_H0PLL(v) BM_CPM_CCR_SEL_H0PLL | ||
59 | #define BF_CPM_CCR_SEL_H0PLL_V(e) BF_CPM_CCR_SEL_H0PLL(BV_CPM_CCR_SEL_H0PLL__##e) | ||
60 | #define BFM_CPM_CCR_SEL_H0PLL_V(v) BM_CPM_CCR_SEL_H0PLL | ||
61 | #define BP_CPM_CCR_SEL_H2PLL 24 | ||
62 | #define BM_CPM_CCR_SEL_H2PLL 0x3000000 | ||
63 | #define BV_CPM_CCR_SEL_H2PLL__STOP 0x0 | ||
64 | #define BV_CPM_CCR_SEL_H2PLL__SCLK_A 0x1 | ||
65 | #define BV_CPM_CCR_SEL_H2PLL__MPLL 0x2 | ||
66 | #define BF_CPM_CCR_SEL_H2PLL(v) (((v) & 0x3) << 24) | ||
67 | #define BFM_CPM_CCR_SEL_H2PLL(v) BM_CPM_CCR_SEL_H2PLL | ||
68 | #define BF_CPM_CCR_SEL_H2PLL_V(e) BF_CPM_CCR_SEL_H2PLL(BV_CPM_CCR_SEL_H2PLL__##e) | ||
69 | #define BFM_CPM_CCR_SEL_H2PLL_V(v) BM_CPM_CCR_SEL_H2PLL | ||
70 | #define BP_CPM_CCR_PDIV 16 | ||
71 | #define BM_CPM_CCR_PDIV 0xf0000 | ||
72 | #define BF_CPM_CCR_PDIV(v) (((v) & 0xf) << 16) | ||
73 | #define BFM_CPM_CCR_PDIV(v) BM_CPM_CCR_PDIV | ||
74 | #define BF_CPM_CCR_PDIV_V(e) BF_CPM_CCR_PDIV(BV_CPM_CCR_PDIV__##e) | ||
75 | #define BFM_CPM_CCR_PDIV_V(v) BM_CPM_CCR_PDIV | ||
76 | #define BP_CPM_CCR_H2DIV 12 | ||
77 | #define BM_CPM_CCR_H2DIV 0xf000 | ||
78 | #define BF_CPM_CCR_H2DIV(v) (((v) & 0xf) << 12) | ||
79 | #define BFM_CPM_CCR_H2DIV(v) BM_CPM_CCR_H2DIV | ||
80 | #define BF_CPM_CCR_H2DIV_V(e) BF_CPM_CCR_H2DIV(BV_CPM_CCR_H2DIV__##e) | ||
81 | #define BFM_CPM_CCR_H2DIV_V(v) BM_CPM_CCR_H2DIV | ||
82 | #define BP_CPM_CCR_H0DIV 8 | ||
83 | #define BM_CPM_CCR_H0DIV 0xf00 | ||
84 | #define BF_CPM_CCR_H0DIV(v) (((v) & 0xf) << 8) | ||
85 | #define BFM_CPM_CCR_H0DIV(v) BM_CPM_CCR_H0DIV | ||
86 | #define BF_CPM_CCR_H0DIV_V(e) BF_CPM_CCR_H0DIV(BV_CPM_CCR_H0DIV__##e) | ||
87 | #define BFM_CPM_CCR_H0DIV_V(v) BM_CPM_CCR_H0DIV | ||
88 | #define BP_CPM_CCR_L2DIV 4 | ||
89 | #define BM_CPM_CCR_L2DIV 0xf0 | ||
90 | #define BF_CPM_CCR_L2DIV(v) (((v) & 0xf) << 4) | ||
91 | #define BFM_CPM_CCR_L2DIV(v) BM_CPM_CCR_L2DIV | ||
92 | #define BF_CPM_CCR_L2DIV_V(e) BF_CPM_CCR_L2DIV(BV_CPM_CCR_L2DIV__##e) | ||
93 | #define BFM_CPM_CCR_L2DIV_V(v) BM_CPM_CCR_L2DIV | ||
94 | #define BP_CPM_CCR_CDIV 0 | ||
95 | #define BM_CPM_CCR_CDIV 0xf | ||
96 | #define BF_CPM_CCR_CDIV(v) (((v) & 0xf) << 0) | ||
97 | #define BFM_CPM_CCR_CDIV(v) BM_CPM_CCR_CDIV | ||
98 | #define BF_CPM_CCR_CDIV_V(e) BF_CPM_CCR_CDIV(BV_CPM_CCR_CDIV__##e) | ||
99 | #define BFM_CPM_CCR_CDIV_V(v) BM_CPM_CCR_CDIV | ||
100 | #define BP_CPM_CCR_GATE_SCLKA 23 | ||
101 | #define BM_CPM_CCR_GATE_SCLKA 0x800000 | ||
102 | #define BF_CPM_CCR_GATE_SCLKA(v) (((v) & 0x1) << 23) | ||
103 | #define BFM_CPM_CCR_GATE_SCLKA(v) BM_CPM_CCR_GATE_SCLKA | ||
104 | #define BF_CPM_CCR_GATE_SCLKA_V(e) BF_CPM_CCR_GATE_SCLKA(BV_CPM_CCR_GATE_SCLKA__##e) | ||
105 | #define BFM_CPM_CCR_GATE_SCLKA_V(v) BM_CPM_CCR_GATE_SCLKA | ||
106 | #define BP_CPM_CCR_CE_CPU 22 | ||
107 | #define BM_CPM_CCR_CE_CPU 0x400000 | ||
108 | #define BF_CPM_CCR_CE_CPU(v) (((v) & 0x1) << 22) | ||
109 | #define BFM_CPM_CCR_CE_CPU(v) BM_CPM_CCR_CE_CPU | ||
110 | #define BF_CPM_CCR_CE_CPU_V(e) BF_CPM_CCR_CE_CPU(BV_CPM_CCR_CE_CPU__##e) | ||
111 | #define BFM_CPM_CCR_CE_CPU_V(v) BM_CPM_CCR_CE_CPU | ||
112 | #define BP_CPM_CCR_CE_AHB0 21 | ||
113 | #define BM_CPM_CCR_CE_AHB0 0x200000 | ||
114 | #define BF_CPM_CCR_CE_AHB0(v) (((v) & 0x1) << 21) | ||
115 | #define BFM_CPM_CCR_CE_AHB0(v) BM_CPM_CCR_CE_AHB0 | ||
116 | #define BF_CPM_CCR_CE_AHB0_V(e) BF_CPM_CCR_CE_AHB0(BV_CPM_CCR_CE_AHB0__##e) | ||
117 | #define BFM_CPM_CCR_CE_AHB0_V(v) BM_CPM_CCR_CE_AHB0 | ||
118 | #define BP_CPM_CCR_CE_AHB2 20 | ||
119 | #define BM_CPM_CCR_CE_AHB2 0x100000 | ||
120 | #define BF_CPM_CCR_CE_AHB2(v) (((v) & 0x1) << 20) | ||
121 | #define BFM_CPM_CCR_CE_AHB2(v) BM_CPM_CCR_CE_AHB2 | ||
122 | #define BF_CPM_CCR_CE_AHB2_V(e) BF_CPM_CCR_CE_AHB2(BV_CPM_CCR_CE_AHB2__##e) | ||
123 | #define BFM_CPM_CCR_CE_AHB2_V(v) BM_CPM_CCR_CE_AHB2 | ||
124 | |||
125 | #define REG_CPM_CSR jz_reg(CPM_CSR) | ||
126 | #define JA_CPM_CSR (0xb0000000 + 0xd4) | ||
127 | #define JT_CPM_CSR JIO_32_RW | ||
128 | #define JN_CPM_CSR CPM_CSR | ||
129 | #define JI_CPM_CSR | ||
130 | #define BP_CPM_CSR_SRC_MUX 31 | ||
131 | #define BM_CPM_CSR_SRC_MUX 0x80000000 | ||
132 | #define BF_CPM_CSR_SRC_MUX(v) (((v) & 0x1) << 31) | ||
133 | #define BFM_CPM_CSR_SRC_MUX(v) BM_CPM_CSR_SRC_MUX | ||
134 | #define BF_CPM_CSR_SRC_MUX_V(e) BF_CPM_CSR_SRC_MUX(BV_CPM_CSR_SRC_MUX__##e) | ||
135 | #define BFM_CPM_CSR_SRC_MUX_V(v) BM_CPM_CSR_SRC_MUX | ||
136 | #define BP_CPM_CSR_CPU_MUX 30 | ||
137 | #define BM_CPM_CSR_CPU_MUX 0x40000000 | ||
138 | #define BF_CPM_CSR_CPU_MUX(v) (((v) & 0x1) << 30) | ||
139 | #define BFM_CPM_CSR_CPU_MUX(v) BM_CPM_CSR_CPU_MUX | ||
140 | #define BF_CPM_CSR_CPU_MUX_V(e) BF_CPM_CSR_CPU_MUX(BV_CPM_CSR_CPU_MUX__##e) | ||
141 | #define BFM_CPM_CSR_CPU_MUX_V(v) BM_CPM_CSR_CPU_MUX | ||
142 | #define BP_CPM_CSR_AHB0_MUX 29 | ||
143 | #define BM_CPM_CSR_AHB0_MUX 0x20000000 | ||
144 | #define BF_CPM_CSR_AHB0_MUX(v) (((v) & 0x1) << 29) | ||
145 | #define BFM_CPM_CSR_AHB0_MUX(v) BM_CPM_CSR_AHB0_MUX | ||
146 | #define BF_CPM_CSR_AHB0_MUX_V(e) BF_CPM_CSR_AHB0_MUX(BV_CPM_CSR_AHB0_MUX__##e) | ||
147 | #define BFM_CPM_CSR_AHB0_MUX_V(v) BM_CPM_CSR_AHB0_MUX | ||
148 | #define BP_CPM_CSR_AHB2_MUX 28 | ||
149 | #define BM_CPM_CSR_AHB2_MUX 0x10000000 | ||
150 | #define BF_CPM_CSR_AHB2_MUX(v) (((v) & 0x1) << 28) | ||
151 | #define BFM_CPM_CSR_AHB2_MUX(v) BM_CPM_CSR_AHB2_MUX | ||
152 | #define BF_CPM_CSR_AHB2_MUX_V(e) BF_CPM_CSR_AHB2_MUX(BV_CPM_CSR_AHB2_MUX__##e) | ||
153 | #define BFM_CPM_CSR_AHB2_MUX_V(v) BM_CPM_CSR_AHB2_MUX | ||
154 | #define BP_CPM_CSR_DDR_MUX 27 | ||
155 | #define BM_CPM_CSR_DDR_MUX 0x8000000 | ||
156 | #define BF_CPM_CSR_DDR_MUX(v) (((v) & 0x1) << 27) | ||
157 | #define BFM_CPM_CSR_DDR_MUX(v) BM_CPM_CSR_DDR_MUX | ||
158 | #define BF_CPM_CSR_DDR_MUX_V(e) BF_CPM_CSR_DDR_MUX(BV_CPM_CSR_DDR_MUX__##e) | ||
159 | #define BFM_CPM_CSR_DDR_MUX_V(v) BM_CPM_CSR_DDR_MUX | ||
160 | #define BP_CPM_CSR_H2DIV_BUSY 2 | ||
161 | #define BM_CPM_CSR_H2DIV_BUSY 0x4 | ||
162 | #define BF_CPM_CSR_H2DIV_BUSY(v) (((v) & 0x1) << 2) | ||
163 | #define BFM_CPM_CSR_H2DIV_BUSY(v) BM_CPM_CSR_H2DIV_BUSY | ||
164 | #define BF_CPM_CSR_H2DIV_BUSY_V(e) BF_CPM_CSR_H2DIV_BUSY(BV_CPM_CSR_H2DIV_BUSY__##e) | ||
165 | #define BFM_CPM_CSR_H2DIV_BUSY_V(v) BM_CPM_CSR_H2DIV_BUSY | ||
166 | #define BP_CPM_CSR_H0DIV_BUSY 1 | ||
167 | #define BM_CPM_CSR_H0DIV_BUSY 0x2 | ||
168 | #define BF_CPM_CSR_H0DIV_BUSY(v) (((v) & 0x1) << 1) | ||
169 | #define BFM_CPM_CSR_H0DIV_BUSY(v) BM_CPM_CSR_H0DIV_BUSY | ||
170 | #define BF_CPM_CSR_H0DIV_BUSY_V(e) BF_CPM_CSR_H0DIV_BUSY(BV_CPM_CSR_H0DIV_BUSY__##e) | ||
171 | #define BFM_CPM_CSR_H0DIV_BUSY_V(v) BM_CPM_CSR_H0DIV_BUSY | ||
172 | #define BP_CPM_CSR_CDIV_BUSY 0 | ||
173 | #define BM_CPM_CSR_CDIV_BUSY 0x1 | ||
174 | #define BF_CPM_CSR_CDIV_BUSY(v) (((v) & 0x1) << 0) | ||
175 | #define BFM_CPM_CSR_CDIV_BUSY(v) BM_CPM_CSR_CDIV_BUSY | ||
176 | #define BF_CPM_CSR_CDIV_BUSY_V(e) BF_CPM_CSR_CDIV_BUSY(BV_CPM_CSR_CDIV_BUSY__##e) | ||
177 | #define BFM_CPM_CSR_CDIV_BUSY_V(v) BM_CPM_CSR_CDIV_BUSY | ||
178 | |||
179 | #define REG_CPM_DDRCDR jz_reg(CPM_DDRCDR) | ||
180 | #define JA_CPM_DDRCDR (0xb0000000 + 0x2c) | ||
181 | #define JT_CPM_DDRCDR JIO_32_RW | ||
182 | #define JN_CPM_DDRCDR CPM_DDRCDR | ||
183 | #define JI_CPM_DDRCDR | ||
184 | #define BP_CPM_DDRCDR_CLKSRC 30 | ||
185 | #define BM_CPM_DDRCDR_CLKSRC 0xc0000000 | ||
186 | #define BV_CPM_DDRCDR_CLKSRC__STOP 0x0 | ||
187 | #define BV_CPM_DDRCDR_CLKSRC__SCLK_A 0x1 | ||
188 | #define BV_CPM_DDRCDR_CLKSRC__MPLL 0x2 | ||
189 | #define BF_CPM_DDRCDR_CLKSRC(v) (((v) & 0x3) << 30) | ||
190 | #define BFM_CPM_DDRCDR_CLKSRC(v) BM_CPM_DDRCDR_CLKSRC | ||
191 | #define BF_CPM_DDRCDR_CLKSRC_V(e) BF_CPM_DDRCDR_CLKSRC(BV_CPM_DDRCDR_CLKSRC__##e) | ||
192 | #define BFM_CPM_DDRCDR_CLKSRC_V(v) BM_CPM_DDRCDR_CLKSRC | ||
193 | #define BP_CPM_DDRCDR_CLKDIV 0 | ||
194 | #define BM_CPM_DDRCDR_CLKDIV 0xf | ||
195 | #define BF_CPM_DDRCDR_CLKDIV(v) (((v) & 0xf) << 0) | ||
196 | #define BFM_CPM_DDRCDR_CLKDIV(v) BM_CPM_DDRCDR_CLKDIV | ||
197 | #define BF_CPM_DDRCDR_CLKDIV_V(e) BF_CPM_DDRCDR_CLKDIV(BV_CPM_DDRCDR_CLKDIV__##e) | ||
198 | #define BFM_CPM_DDRCDR_CLKDIV_V(v) BM_CPM_DDRCDR_CLKDIV | ||
199 | #define BP_CPM_DDRCDR_CE 29 | ||
200 | #define BM_CPM_DDRCDR_CE 0x20000000 | ||
201 | #define BF_CPM_DDRCDR_CE(v) (((v) & 0x1) << 29) | ||
202 | #define BFM_CPM_DDRCDR_CE(v) BM_CPM_DDRCDR_CE | ||
203 | #define BF_CPM_DDRCDR_CE_V(e) BF_CPM_DDRCDR_CE(BV_CPM_DDRCDR_CE__##e) | ||
204 | #define BFM_CPM_DDRCDR_CE_V(v) BM_CPM_DDRCDR_CE | ||
205 | #define BP_CPM_DDRCDR_BUSY 28 | ||
206 | #define BM_CPM_DDRCDR_BUSY 0x10000000 | ||
207 | #define BF_CPM_DDRCDR_BUSY(v) (((v) & 0x1) << 28) | ||
208 | #define BFM_CPM_DDRCDR_BUSY(v) BM_CPM_DDRCDR_BUSY | ||
209 | #define BF_CPM_DDRCDR_BUSY_V(e) BF_CPM_DDRCDR_BUSY(BV_CPM_DDRCDR_BUSY__##e) | ||
210 | #define BFM_CPM_DDRCDR_BUSY_V(v) BM_CPM_DDRCDR_BUSY | ||
211 | #define BP_CPM_DDRCDR_STOP 27 | ||
212 | #define BM_CPM_DDRCDR_STOP 0x8000000 | ||
213 | #define BF_CPM_DDRCDR_STOP(v) (((v) & 0x1) << 27) | ||
214 | #define BFM_CPM_DDRCDR_STOP(v) BM_CPM_DDRCDR_STOP | ||
215 | #define BF_CPM_DDRCDR_STOP_V(e) BF_CPM_DDRCDR_STOP(BV_CPM_DDRCDR_STOP__##e) | ||
216 | #define BFM_CPM_DDRCDR_STOP_V(v) BM_CPM_DDRCDR_STOP | ||
217 | #define BP_CPM_DDRCDR_GATE_EN 26 | ||
218 | #define BM_CPM_DDRCDR_GATE_EN 0x4000000 | ||
219 | #define BF_CPM_DDRCDR_GATE_EN(v) (((v) & 0x1) << 26) | ||
220 | #define BFM_CPM_DDRCDR_GATE_EN(v) BM_CPM_DDRCDR_GATE_EN | ||
221 | #define BF_CPM_DDRCDR_GATE_EN_V(e) BF_CPM_DDRCDR_GATE_EN(BV_CPM_DDRCDR_GATE_EN__##e) | ||
222 | #define BFM_CPM_DDRCDR_GATE_EN_V(v) BM_CPM_DDRCDR_GATE_EN | ||
223 | #define BP_CPM_DDRCDR_CHANGE_EN 25 | ||
224 | #define BM_CPM_DDRCDR_CHANGE_EN 0x2000000 | ||
225 | #define BF_CPM_DDRCDR_CHANGE_EN(v) (((v) & 0x1) << 25) | ||
226 | #define BFM_CPM_DDRCDR_CHANGE_EN(v) BM_CPM_DDRCDR_CHANGE_EN | ||
227 | #define BF_CPM_DDRCDR_CHANGE_EN_V(e) BF_CPM_DDRCDR_CHANGE_EN(BV_CPM_DDRCDR_CHANGE_EN__##e) | ||
228 | #define BFM_CPM_DDRCDR_CHANGE_EN_V(v) BM_CPM_DDRCDR_CHANGE_EN | ||
229 | #define BP_CPM_DDRCDR_FLAG 24 | ||
230 | #define BM_CPM_DDRCDR_FLAG 0x1000000 | ||
231 | #define BF_CPM_DDRCDR_FLAG(v) (((v) & 0x1) << 24) | ||
232 | #define BFM_CPM_DDRCDR_FLAG(v) BM_CPM_DDRCDR_FLAG | ||
233 | #define BF_CPM_DDRCDR_FLAG_V(e) BF_CPM_DDRCDR_FLAG(BV_CPM_DDRCDR_FLAG__##e) | ||
234 | #define BFM_CPM_DDRCDR_FLAG_V(v) BM_CPM_DDRCDR_FLAG | ||
235 | |||
236 | #define REG_CPM_I2SCDR jz_reg(CPM_I2SCDR) | ||
237 | #define JA_CPM_I2SCDR (0xb0000000 + 0x60) | ||
238 | #define JT_CPM_I2SCDR JIO_32_RW | ||
239 | #define JN_CPM_I2SCDR CPM_I2SCDR | ||
240 | #define JI_CPM_I2SCDR | ||
241 | #define BP_CPM_I2SCDR_DIV_M 13 | ||
242 | #define BM_CPM_I2SCDR_DIV_M 0x3fe000 | ||
243 | #define BF_CPM_I2SCDR_DIV_M(v) (((v) & 0x1ff) << 13) | ||
244 | #define BFM_CPM_I2SCDR_DIV_M(v) BM_CPM_I2SCDR_DIV_M | ||
245 | #define BF_CPM_I2SCDR_DIV_M_V(e) BF_CPM_I2SCDR_DIV_M(BV_CPM_I2SCDR_DIV_M__##e) | ||
246 | #define BFM_CPM_I2SCDR_DIV_M_V(v) BM_CPM_I2SCDR_DIV_M | ||
247 | #define BP_CPM_I2SCDR_DIV_N 0 | ||
248 | #define BM_CPM_I2SCDR_DIV_N 0x1fff | ||
249 | #define BF_CPM_I2SCDR_DIV_N(v) (((v) & 0x1fff) << 0) | ||
250 | #define BFM_CPM_I2SCDR_DIV_N(v) BM_CPM_I2SCDR_DIV_N | ||
251 | #define BF_CPM_I2SCDR_DIV_N_V(e) BF_CPM_I2SCDR_DIV_N(BV_CPM_I2SCDR_DIV_N__##e) | ||
252 | #define BFM_CPM_I2SCDR_DIV_N_V(v) BM_CPM_I2SCDR_DIV_N | ||
253 | #define BP_CPM_I2SCDR_PCS 31 | ||
254 | #define BM_CPM_I2SCDR_PCS 0x80000000 | ||
255 | #define BV_CPM_I2SCDR_PCS__SCLK_A 0x0 | ||
256 | #define BV_CPM_I2SCDR_PCS__MPLL 0x1 | ||
257 | #define BF_CPM_I2SCDR_PCS(v) (((v) & 0x1) << 31) | ||
258 | #define BFM_CPM_I2SCDR_PCS(v) BM_CPM_I2SCDR_PCS | ||
259 | #define BF_CPM_I2SCDR_PCS_V(e) BF_CPM_I2SCDR_PCS(BV_CPM_I2SCDR_PCS__##e) | ||
260 | #define BFM_CPM_I2SCDR_PCS_V(v) BM_CPM_I2SCDR_PCS | ||
261 | #define BP_CPM_I2SCDR_CS 30 | ||
262 | #define BM_CPM_I2SCDR_CS 0x40000000 | ||
263 | #define BV_CPM_I2SCDR_CS__EXCLK 0x0 | ||
264 | #define BV_CPM_I2SCDR_CS__PLL 0x1 | ||
265 | #define BF_CPM_I2SCDR_CS(v) (((v) & 0x1) << 30) | ||
266 | #define BFM_CPM_I2SCDR_CS(v) BM_CPM_I2SCDR_CS | ||
267 | #define BF_CPM_I2SCDR_CS_V(e) BF_CPM_I2SCDR_CS(BV_CPM_I2SCDR_CS__##e) | ||
268 | #define BFM_CPM_I2SCDR_CS_V(v) BM_CPM_I2SCDR_CS | ||
269 | #define BP_CPM_I2SCDR_CE 29 | ||
270 | #define BM_CPM_I2SCDR_CE 0x20000000 | ||
271 | #define BF_CPM_I2SCDR_CE(v) (((v) & 0x1) << 29) | ||
272 | #define BFM_CPM_I2SCDR_CE(v) BM_CPM_I2SCDR_CE | ||
273 | #define BF_CPM_I2SCDR_CE_V(e) BF_CPM_I2SCDR_CE(BV_CPM_I2SCDR_CE__##e) | ||
274 | #define BFM_CPM_I2SCDR_CE_V(v) BM_CPM_I2SCDR_CE | ||
275 | |||
276 | #define REG_CPM_I2SCDR1 jz_reg(CPM_I2SCDR1) | ||
277 | #define JA_CPM_I2SCDR1 (0xb0000000 + 0x70) | ||
278 | #define JT_CPM_I2SCDR1 JIO_32_RW | ||
279 | #define JN_CPM_I2SCDR1 CPM_I2SCDR1 | ||
280 | #define JI_CPM_I2SCDR1 | ||
281 | |||
282 | #define REG_CPM_LPCDR jz_reg(CPM_LPCDR) | ||
283 | #define JA_CPM_LPCDR (0xb0000000 + 0x64) | ||
284 | #define JT_CPM_LPCDR JIO_32_RW | ||
285 | #define JN_CPM_LPCDR CPM_LPCDR | ||
286 | #define JI_CPM_LPCDR | ||
287 | #define BP_CPM_LPCDR_CLKDIV 0 | ||
288 | #define BM_CPM_LPCDR_CLKDIV 0xff | ||
289 | #define BF_CPM_LPCDR_CLKDIV(v) (((v) & 0xff) << 0) | ||
290 | #define BFM_CPM_LPCDR_CLKDIV(v) BM_CPM_LPCDR_CLKDIV | ||
291 | #define BF_CPM_LPCDR_CLKDIV_V(e) BF_CPM_LPCDR_CLKDIV(BV_CPM_LPCDR_CLKDIV__##e) | ||
292 | #define BFM_CPM_LPCDR_CLKDIV_V(v) BM_CPM_LPCDR_CLKDIV | ||
293 | #define BP_CPM_LPCDR_CLKSRC 31 | ||
294 | #define BM_CPM_LPCDR_CLKSRC 0x80000000 | ||
295 | #define BV_CPM_LPCDR_CLKSRC__SCLK_A 0x0 | ||
296 | #define BV_CPM_LPCDR_CLKSRC__MPLL 0x1 | ||
297 | #define BF_CPM_LPCDR_CLKSRC(v) (((v) & 0x1) << 31) | ||
298 | #define BFM_CPM_LPCDR_CLKSRC(v) BM_CPM_LPCDR_CLKSRC | ||
299 | #define BF_CPM_LPCDR_CLKSRC_V(e) BF_CPM_LPCDR_CLKSRC(BV_CPM_LPCDR_CLKSRC__##e) | ||
300 | #define BFM_CPM_LPCDR_CLKSRC_V(v) BM_CPM_LPCDR_CLKSRC | ||
301 | #define BP_CPM_LPCDR_CE 28 | ||
302 | #define BM_CPM_LPCDR_CE 0x10000000 | ||
303 | #define BF_CPM_LPCDR_CE(v) (((v) & 0x1) << 28) | ||
304 | #define BFM_CPM_LPCDR_CE(v) BM_CPM_LPCDR_CE | ||
305 | #define BF_CPM_LPCDR_CE_V(e) BF_CPM_LPCDR_CE(BV_CPM_LPCDR_CE__##e) | ||
306 | #define BFM_CPM_LPCDR_CE_V(v) BM_CPM_LPCDR_CE | ||
307 | #define BP_CPM_LPCDR_BUSY 27 | ||
308 | #define BM_CPM_LPCDR_BUSY 0x8000000 | ||
309 | #define BF_CPM_LPCDR_BUSY(v) (((v) & 0x1) << 27) | ||
310 | #define BFM_CPM_LPCDR_BUSY(v) BM_CPM_LPCDR_BUSY | ||
311 | #define BF_CPM_LPCDR_BUSY_V(e) BF_CPM_LPCDR_BUSY(BV_CPM_LPCDR_BUSY__##e) | ||
312 | #define BFM_CPM_LPCDR_BUSY_V(v) BM_CPM_LPCDR_BUSY | ||
313 | #define BP_CPM_LPCDR_STOP 26 | ||
314 | #define BM_CPM_LPCDR_STOP 0x4000000 | ||
315 | #define BF_CPM_LPCDR_STOP(v) (((v) & 0x1) << 26) | ||
316 | #define BFM_CPM_LPCDR_STOP(v) BM_CPM_LPCDR_STOP | ||
317 | #define BF_CPM_LPCDR_STOP_V(e) BF_CPM_LPCDR_STOP(BV_CPM_LPCDR_STOP__##e) | ||
318 | #define BFM_CPM_LPCDR_STOP_V(v) BM_CPM_LPCDR_STOP | ||
319 | |||
320 | #define REG_CPM_MSC0CDR jz_reg(CPM_MSC0CDR) | ||
321 | #define JA_CPM_MSC0CDR (0xb0000000 + 0x68) | ||
322 | #define JT_CPM_MSC0CDR JIO_32_RW | ||
323 | #define JN_CPM_MSC0CDR CPM_MSC0CDR | ||
324 | #define JI_CPM_MSC0CDR | ||
325 | #define BP_CPM_MSC0CDR_CLKDIV 0 | ||
326 | #define BM_CPM_MSC0CDR_CLKDIV 0xff | ||
327 | #define BF_CPM_MSC0CDR_CLKDIV(v) (((v) & 0xff) << 0) | ||
328 | #define BFM_CPM_MSC0CDR_CLKDIV(v) BM_CPM_MSC0CDR_CLKDIV | ||
329 | #define BF_CPM_MSC0CDR_CLKDIV_V(e) BF_CPM_MSC0CDR_CLKDIV(BV_CPM_MSC0CDR_CLKDIV__##e) | ||
330 | #define BFM_CPM_MSC0CDR_CLKDIV_V(v) BM_CPM_MSC0CDR_CLKDIV | ||
331 | #define BP_CPM_MSC0CDR_CLKSRC 31 | ||
332 | #define BM_CPM_MSC0CDR_CLKSRC 0x80000000 | ||
333 | #define BV_CPM_MSC0CDR_CLKSRC__SCLK_A 0x0 | ||
334 | #define BV_CPM_MSC0CDR_CLKSRC__MPLL 0x1 | ||
335 | #define BF_CPM_MSC0CDR_CLKSRC(v) (((v) & 0x1) << 31) | ||
336 | #define BFM_CPM_MSC0CDR_CLKSRC(v) BM_CPM_MSC0CDR_CLKSRC | ||
337 | #define BF_CPM_MSC0CDR_CLKSRC_V(e) BF_CPM_MSC0CDR_CLKSRC(BV_CPM_MSC0CDR_CLKSRC__##e) | ||
338 | #define BFM_CPM_MSC0CDR_CLKSRC_V(v) BM_CPM_MSC0CDR_CLKSRC | ||
339 | #define BP_CPM_MSC0CDR_CE 29 | ||
340 | #define BM_CPM_MSC0CDR_CE 0x20000000 | ||
341 | #define BF_CPM_MSC0CDR_CE(v) (((v) & 0x1) << 29) | ||
342 | #define BFM_CPM_MSC0CDR_CE(v) BM_CPM_MSC0CDR_CE | ||
343 | #define BF_CPM_MSC0CDR_CE_V(e) BF_CPM_MSC0CDR_CE(BV_CPM_MSC0CDR_CE__##e) | ||
344 | #define BFM_CPM_MSC0CDR_CE_V(v) BM_CPM_MSC0CDR_CE | ||
345 | #define BP_CPM_MSC0CDR_BUSY 28 | ||
346 | #define BM_CPM_MSC0CDR_BUSY 0x10000000 | ||
347 | #define BF_CPM_MSC0CDR_BUSY(v) (((v) & 0x1) << 28) | ||
348 | #define BFM_CPM_MSC0CDR_BUSY(v) BM_CPM_MSC0CDR_BUSY | ||
349 | #define BF_CPM_MSC0CDR_BUSY_V(e) BF_CPM_MSC0CDR_BUSY(BV_CPM_MSC0CDR_BUSY__##e) | ||
350 | #define BFM_CPM_MSC0CDR_BUSY_V(v) BM_CPM_MSC0CDR_BUSY | ||
351 | #define BP_CPM_MSC0CDR_STOP 27 | ||
352 | #define BM_CPM_MSC0CDR_STOP 0x8000000 | ||
353 | #define BF_CPM_MSC0CDR_STOP(v) (((v) & 0x1) << 27) | ||
354 | #define BFM_CPM_MSC0CDR_STOP(v) BM_CPM_MSC0CDR_STOP | ||
355 | #define BF_CPM_MSC0CDR_STOP_V(e) BF_CPM_MSC0CDR_STOP(BV_CPM_MSC0CDR_STOP__##e) | ||
356 | #define BFM_CPM_MSC0CDR_STOP_V(v) BM_CPM_MSC0CDR_STOP | ||
357 | #define BP_CPM_MSC0CDR_S_CLK0_SEL 15 | ||
358 | #define BM_CPM_MSC0CDR_S_CLK0_SEL 0x8000 | ||
359 | #define BV_CPM_MSC0CDR_S_CLK0_SEL__90DEG 0x0 | ||
360 | #define BV_CPM_MSC0CDR_S_CLK0_SEL__180DEG 0x1 | ||
361 | #define BF_CPM_MSC0CDR_S_CLK0_SEL(v) (((v) & 0x1) << 15) | ||
362 | #define BFM_CPM_MSC0CDR_S_CLK0_SEL(v) BM_CPM_MSC0CDR_S_CLK0_SEL | ||
363 | #define BF_CPM_MSC0CDR_S_CLK0_SEL_V(e) BF_CPM_MSC0CDR_S_CLK0_SEL(BV_CPM_MSC0CDR_S_CLK0_SEL__##e) | ||
364 | #define BFM_CPM_MSC0CDR_S_CLK0_SEL_V(v) BM_CPM_MSC0CDR_S_CLK0_SEL | ||
365 | |||
366 | #define REG_CPM_MSC1CDR jz_reg(CPM_MSC1CDR) | ||
367 | #define JA_CPM_MSC1CDR (0xb0000000 + 0xa4) | ||
368 | #define JT_CPM_MSC1CDR JIO_32_RW | ||
369 | #define JN_CPM_MSC1CDR CPM_MSC1CDR | ||
370 | #define JI_CPM_MSC1CDR | ||
371 | #define BP_CPM_MSC1CDR_CLKDIV 0 | ||
372 | #define BM_CPM_MSC1CDR_CLKDIV 0xff | ||
373 | #define BF_CPM_MSC1CDR_CLKDIV(v) (((v) & 0xff) << 0) | ||
374 | #define BFM_CPM_MSC1CDR_CLKDIV(v) BM_CPM_MSC1CDR_CLKDIV | ||
375 | #define BF_CPM_MSC1CDR_CLKDIV_V(e) BF_CPM_MSC1CDR_CLKDIV(BV_CPM_MSC1CDR_CLKDIV__##e) | ||
376 | #define BFM_CPM_MSC1CDR_CLKDIV_V(v) BM_CPM_MSC1CDR_CLKDIV | ||
377 | #define BP_CPM_MSC1CDR_CE 29 | ||
378 | #define BM_CPM_MSC1CDR_CE 0x20000000 | ||
379 | #define BF_CPM_MSC1CDR_CE(v) (((v) & 0x1) << 29) | ||
380 | #define BFM_CPM_MSC1CDR_CE(v) BM_CPM_MSC1CDR_CE | ||
381 | #define BF_CPM_MSC1CDR_CE_V(e) BF_CPM_MSC1CDR_CE(BV_CPM_MSC1CDR_CE__##e) | ||
382 | #define BFM_CPM_MSC1CDR_CE_V(v) BM_CPM_MSC1CDR_CE | ||
383 | #define BP_CPM_MSC1CDR_BUSY 28 | ||
384 | #define BM_CPM_MSC1CDR_BUSY 0x10000000 | ||
385 | #define BF_CPM_MSC1CDR_BUSY(v) (((v) & 0x1) << 28) | ||
386 | #define BFM_CPM_MSC1CDR_BUSY(v) BM_CPM_MSC1CDR_BUSY | ||
387 | #define BF_CPM_MSC1CDR_BUSY_V(e) BF_CPM_MSC1CDR_BUSY(BV_CPM_MSC1CDR_BUSY__##e) | ||
388 | #define BFM_CPM_MSC1CDR_BUSY_V(v) BM_CPM_MSC1CDR_BUSY | ||
389 | #define BP_CPM_MSC1CDR_STOP 27 | ||
390 | #define BM_CPM_MSC1CDR_STOP 0x8000000 | ||
391 | #define BF_CPM_MSC1CDR_STOP(v) (((v) & 0x1) << 27) | ||
392 | #define BFM_CPM_MSC1CDR_STOP(v) BM_CPM_MSC1CDR_STOP | ||
393 | #define BF_CPM_MSC1CDR_STOP_V(e) BF_CPM_MSC1CDR_STOP(BV_CPM_MSC1CDR_STOP__##e) | ||
394 | #define BFM_CPM_MSC1CDR_STOP_V(v) BM_CPM_MSC1CDR_STOP | ||
395 | #define BP_CPM_MSC1CDR_S_CLK1_SEL 15 | ||
396 | #define BM_CPM_MSC1CDR_S_CLK1_SEL 0x8000 | ||
397 | #define BV_CPM_MSC1CDR_S_CLK1_SEL__90DEG 0x0 | ||
398 | #define BV_CPM_MSC1CDR_S_CLK1_SEL__180DEG 0x1 | ||
399 | #define BF_CPM_MSC1CDR_S_CLK1_SEL(v) (((v) & 0x1) << 15) | ||
400 | #define BFM_CPM_MSC1CDR_S_CLK1_SEL(v) BM_CPM_MSC1CDR_S_CLK1_SEL | ||
401 | #define BF_CPM_MSC1CDR_S_CLK1_SEL_V(e) BF_CPM_MSC1CDR_S_CLK1_SEL(BV_CPM_MSC1CDR_S_CLK1_SEL__##e) | ||
402 | #define BFM_CPM_MSC1CDR_S_CLK1_SEL_V(v) BM_CPM_MSC1CDR_S_CLK1_SEL | ||
403 | |||
404 | #define REG_CPM_SSICDR jz_reg(CPM_SSICDR) | ||
405 | #define JA_CPM_SSICDR (0xb0000000 + 0x74) | ||
406 | #define JT_CPM_SSICDR JIO_32_RW | ||
407 | #define JN_CPM_SSICDR CPM_SSICDR | ||
408 | #define JI_CPM_SSICDR | ||
409 | #define BP_CPM_SSICDR_CLKDIV 0 | ||
410 | #define BM_CPM_SSICDR_CLKDIV 0xff | ||
411 | #define BF_CPM_SSICDR_CLKDIV(v) (((v) & 0xff) << 0) | ||
412 | #define BFM_CPM_SSICDR_CLKDIV(v) BM_CPM_SSICDR_CLKDIV | ||
413 | #define BF_CPM_SSICDR_CLKDIV_V(e) BF_CPM_SSICDR_CLKDIV(BV_CPM_SSICDR_CLKDIV__##e) | ||
414 | #define BFM_CPM_SSICDR_CLKDIV_V(v) BM_CPM_SSICDR_CLKDIV | ||
415 | #define BP_CPM_SSICDR_SFC_CS 31 | ||
416 | #define BM_CPM_SSICDR_SFC_CS 0x80000000 | ||
417 | #define BV_CPM_SSICDR_SFC_CS__SCLK_A 0x0 | ||
418 | #define BV_CPM_SSICDR_SFC_CS__MPLL 0x1 | ||
419 | #define BF_CPM_SSICDR_SFC_CS(v) (((v) & 0x1) << 31) | ||
420 | #define BFM_CPM_SSICDR_SFC_CS(v) BM_CPM_SSICDR_SFC_CS | ||
421 | #define BF_CPM_SSICDR_SFC_CS_V(e) BF_CPM_SSICDR_SFC_CS(BV_CPM_SSICDR_SFC_CS__##e) | ||
422 | #define BFM_CPM_SSICDR_SFC_CS_V(v) BM_CPM_SSICDR_SFC_CS | ||
423 | #define BP_CPM_SSICDR_SSI_CS 30 | ||
424 | #define BM_CPM_SSICDR_SSI_CS 0x40000000 | ||
425 | #define BV_CPM_SSICDR_SSI_CS__EXCLK 0x0 | ||
426 | #define BV_CPM_SSICDR_SSI_CS__HALF_SFC 0x1 | ||
427 | #define BF_CPM_SSICDR_SSI_CS(v) (((v) & 0x1) << 30) | ||
428 | #define BFM_CPM_SSICDR_SSI_CS(v) BM_CPM_SSICDR_SSI_CS | ||
429 | #define BF_CPM_SSICDR_SSI_CS_V(e) BF_CPM_SSICDR_SSI_CS(BV_CPM_SSICDR_SSI_CS__##e) | ||
430 | #define BFM_CPM_SSICDR_SSI_CS_V(v) BM_CPM_SSICDR_SSI_CS | ||
431 | #define BP_CPM_SSICDR_CE 29 | ||
432 | #define BM_CPM_SSICDR_CE 0x20000000 | ||
433 | #define BF_CPM_SSICDR_CE(v) (((v) & 0x1) << 29) | ||
434 | #define BFM_CPM_SSICDR_CE(v) BM_CPM_SSICDR_CE | ||
435 | #define BF_CPM_SSICDR_CE_V(e) BF_CPM_SSICDR_CE(BV_CPM_SSICDR_CE__##e) | ||
436 | #define BFM_CPM_SSICDR_CE_V(v) BM_CPM_SSICDR_CE | ||
437 | #define BP_CPM_SSICDR_BUSY 28 | ||
438 | #define BM_CPM_SSICDR_BUSY 0x10000000 | ||
439 | #define BF_CPM_SSICDR_BUSY(v) (((v) & 0x1) << 28) | ||
440 | #define BFM_CPM_SSICDR_BUSY(v) BM_CPM_SSICDR_BUSY | ||
441 | #define BF_CPM_SSICDR_BUSY_V(e) BF_CPM_SSICDR_BUSY(BV_CPM_SSICDR_BUSY__##e) | ||
442 | #define BFM_CPM_SSICDR_BUSY_V(v) BM_CPM_SSICDR_BUSY | ||
443 | #define BP_CPM_SSICDR_STOP 27 | ||
444 | #define BM_CPM_SSICDR_STOP 0x8000000 | ||
445 | #define BF_CPM_SSICDR_STOP(v) (((v) & 0x1) << 27) | ||
446 | #define BFM_CPM_SSICDR_STOP(v) BM_CPM_SSICDR_STOP | ||
447 | #define BF_CPM_SSICDR_STOP_V(e) BF_CPM_SSICDR_STOP(BV_CPM_SSICDR_STOP__##e) | ||
448 | #define BFM_CPM_SSICDR_STOP_V(v) BM_CPM_SSICDR_STOP | ||
449 | |||
450 | #define REG_CPM_DRCG jz_reg(CPM_DRCG) | ||
451 | #define JA_CPM_DRCG (0xb0000000 + 0xd0) | ||
452 | #define JT_CPM_DRCG JIO_32_RW | ||
453 | #define JN_CPM_DRCG CPM_DRCG | ||
454 | #define JI_CPM_DRCG | ||
455 | |||
456 | #define REG_CPM_APCR jz_reg(CPM_APCR) | ||
457 | #define JA_CPM_APCR (0xb0000000 + 0x10) | ||
458 | #define JT_CPM_APCR JIO_32_RW | ||
459 | #define JN_CPM_APCR CPM_APCR | ||
460 | #define JI_CPM_APCR | ||
461 | #define BP_CPM_APCR_PLLM 24 | ||
462 | #define BM_CPM_APCR_PLLM 0x7f000000 | ||
463 | #define BF_CPM_APCR_PLLM(v) (((v) & 0x7f) << 24) | ||
464 | #define BFM_CPM_APCR_PLLM(v) BM_CPM_APCR_PLLM | ||
465 | #define BF_CPM_APCR_PLLM_V(e) BF_CPM_APCR_PLLM(BV_CPM_APCR_PLLM__##e) | ||
466 | #define BFM_CPM_APCR_PLLM_V(v) BM_CPM_APCR_PLLM | ||
467 | #define BP_CPM_APCR_PLLN 18 | ||
468 | #define BM_CPM_APCR_PLLN 0x7c0000 | ||
469 | #define BF_CPM_APCR_PLLN(v) (((v) & 0x1f) << 18) | ||
470 | #define BFM_CPM_APCR_PLLN(v) BM_CPM_APCR_PLLN | ||
471 | #define BF_CPM_APCR_PLLN_V(e) BF_CPM_APCR_PLLN(BV_CPM_APCR_PLLN__##e) | ||
472 | #define BFM_CPM_APCR_PLLN_V(v) BM_CPM_APCR_PLLN | ||
473 | #define BP_CPM_APCR_PLLOD 16 | ||
474 | #define BM_CPM_APCR_PLLOD 0x30000 | ||
475 | #define BF_CPM_APCR_PLLOD(v) (((v) & 0x3) << 16) | ||
476 | #define BFM_CPM_APCR_PLLOD(v) BM_CPM_APCR_PLLOD | ||
477 | #define BF_CPM_APCR_PLLOD_V(e) BF_CPM_APCR_PLLOD(BV_CPM_APCR_PLLOD__##e) | ||
478 | #define BFM_CPM_APCR_PLLOD_V(v) BM_CPM_APCR_PLLOD | ||
479 | #define BP_CPM_APCR_PLLST 0 | ||
480 | #define BM_CPM_APCR_PLLST 0xff | ||
481 | #define BF_CPM_APCR_PLLST(v) (((v) & 0xff) << 0) | ||
482 | #define BFM_CPM_APCR_PLLST(v) BM_CPM_APCR_PLLST | ||
483 | #define BF_CPM_APCR_PLLST_V(e) BF_CPM_APCR_PLLST(BV_CPM_APCR_PLLST__##e) | ||
484 | #define BFM_CPM_APCR_PLLST_V(v) BM_CPM_APCR_PLLST | ||
485 | #define BP_CPM_APCR_BS 31 | ||
486 | #define BM_CPM_APCR_BS 0x80000000 | ||
487 | #define BF_CPM_APCR_BS(v) (((v) & 0x1) << 31) | ||
488 | #define BFM_CPM_APCR_BS(v) BM_CPM_APCR_BS | ||
489 | #define BF_CPM_APCR_BS_V(e) BF_CPM_APCR_BS(BV_CPM_APCR_BS__##e) | ||
490 | #define BFM_CPM_APCR_BS_V(v) BM_CPM_APCR_BS | ||
491 | #define BP_CPM_APCR_LOCK 15 | ||
492 | #define BM_CPM_APCR_LOCK 0x8000 | ||
493 | #define BF_CPM_APCR_LOCK(v) (((v) & 0x1) << 15) | ||
494 | #define BFM_CPM_APCR_LOCK(v) BM_CPM_APCR_LOCK | ||
495 | #define BF_CPM_APCR_LOCK_V(e) BF_CPM_APCR_LOCK(BV_CPM_APCR_LOCK__##e) | ||
496 | #define BFM_CPM_APCR_LOCK_V(v) BM_CPM_APCR_LOCK | ||
497 | #define BP_CPM_APCR_ON 10 | ||
498 | #define BM_CPM_APCR_ON 0x400 | ||
499 | #define BF_CPM_APCR_ON(v) (((v) & 0x1) << 10) | ||
500 | #define BFM_CPM_APCR_ON(v) BM_CPM_APCR_ON | ||
501 | #define BF_CPM_APCR_ON_V(e) BF_CPM_APCR_ON(BV_CPM_APCR_ON__##e) | ||
502 | #define BFM_CPM_APCR_ON_V(v) BM_CPM_APCR_ON | ||
503 | #define BP_CPM_APCR_BYPASS 9 | ||
504 | #define BM_CPM_APCR_BYPASS 0x200 | ||
505 | #define BF_CPM_APCR_BYPASS(v) (((v) & 0x1) << 9) | ||
506 | #define BFM_CPM_APCR_BYPASS(v) BM_CPM_APCR_BYPASS | ||
507 | #define BF_CPM_APCR_BYPASS_V(e) BF_CPM_APCR_BYPASS(BV_CPM_APCR_BYPASS__##e) | ||
508 | #define BFM_CPM_APCR_BYPASS_V(v) BM_CPM_APCR_BYPASS | ||
509 | #define BP_CPM_APCR_ENABLE 8 | ||
510 | #define BM_CPM_APCR_ENABLE 0x100 | ||
511 | #define BF_CPM_APCR_ENABLE(v) (((v) & 0x1) << 8) | ||
512 | #define BFM_CPM_APCR_ENABLE(v) BM_CPM_APCR_ENABLE | ||
513 | #define BF_CPM_APCR_ENABLE_V(e) BF_CPM_APCR_ENABLE(BV_CPM_APCR_ENABLE__##e) | ||
514 | #define BFM_CPM_APCR_ENABLE_V(v) BM_CPM_APCR_ENABLE | ||
515 | |||
516 | #define REG_CPM_MPCR jz_reg(CPM_MPCR) | ||
517 | #define JA_CPM_MPCR (0xb0000000 + 0x14) | ||
518 | #define JT_CPM_MPCR JIO_32_RW | ||
519 | #define JN_CPM_MPCR CPM_MPCR | ||
520 | #define JI_CPM_MPCR | ||
521 | #define BP_CPM_MPCR_PLLM 24 | ||
522 | #define BM_CPM_MPCR_PLLM 0x7f000000 | ||
523 | #define BF_CPM_MPCR_PLLM(v) (((v) & 0x7f) << 24) | ||
524 | #define BFM_CPM_MPCR_PLLM(v) BM_CPM_MPCR_PLLM | ||
525 | #define BF_CPM_MPCR_PLLM_V(e) BF_CPM_MPCR_PLLM(BV_CPM_MPCR_PLLM__##e) | ||
526 | #define BFM_CPM_MPCR_PLLM_V(v) BM_CPM_MPCR_PLLM | ||
527 | #define BP_CPM_MPCR_PLLN 18 | ||
528 | #define BM_CPM_MPCR_PLLN 0x7c0000 | ||
529 | #define BF_CPM_MPCR_PLLN(v) (((v) & 0x1f) << 18) | ||
530 | #define BFM_CPM_MPCR_PLLN(v) BM_CPM_MPCR_PLLN | ||
531 | #define BF_CPM_MPCR_PLLN_V(e) BF_CPM_MPCR_PLLN(BV_CPM_MPCR_PLLN__##e) | ||
532 | #define BFM_CPM_MPCR_PLLN_V(v) BM_CPM_MPCR_PLLN | ||
533 | #define BP_CPM_MPCR_PLLOD 16 | ||
534 | #define BM_CPM_MPCR_PLLOD 0x30000 | ||
535 | #define BF_CPM_MPCR_PLLOD(v) (((v) & 0x3) << 16) | ||
536 | #define BFM_CPM_MPCR_PLLOD(v) BM_CPM_MPCR_PLLOD | ||
537 | #define BF_CPM_MPCR_PLLOD_V(e) BF_CPM_MPCR_PLLOD(BV_CPM_MPCR_PLLOD__##e) | ||
538 | #define BFM_CPM_MPCR_PLLOD_V(v) BM_CPM_MPCR_PLLOD | ||
539 | #define BP_CPM_MPCR_BS 31 | ||
540 | #define BM_CPM_MPCR_BS 0x80000000 | ||
541 | #define BF_CPM_MPCR_BS(v) (((v) & 0x1) << 31) | ||
542 | #define BFM_CPM_MPCR_BS(v) BM_CPM_MPCR_BS | ||
543 | #define BF_CPM_MPCR_BS_V(e) BF_CPM_MPCR_BS(BV_CPM_MPCR_BS__##e) | ||
544 | #define BFM_CPM_MPCR_BS_V(v) BM_CPM_MPCR_BS | ||
545 | #define BP_CPM_MPCR_ENABLE 7 | ||
546 | #define BM_CPM_MPCR_ENABLE 0x80 | ||
547 | #define BF_CPM_MPCR_ENABLE(v) (((v) & 0x1) << 7) | ||
548 | #define BFM_CPM_MPCR_ENABLE(v) BM_CPM_MPCR_ENABLE | ||
549 | #define BF_CPM_MPCR_ENABLE_V(e) BF_CPM_MPCR_ENABLE(BV_CPM_MPCR_ENABLE__##e) | ||
550 | #define BFM_CPM_MPCR_ENABLE_V(v) BM_CPM_MPCR_ENABLE | ||
551 | #define BP_CPM_MPCR_BYPASS 6 | ||
552 | #define BM_CPM_MPCR_BYPASS 0x40 | ||
553 | #define BF_CPM_MPCR_BYPASS(v) (((v) & 0x1) << 6) | ||
554 | #define BFM_CPM_MPCR_BYPASS(v) BM_CPM_MPCR_BYPASS | ||
555 | #define BF_CPM_MPCR_BYPASS_V(e) BF_CPM_MPCR_BYPASS(BV_CPM_MPCR_BYPASS__##e) | ||
556 | #define BFM_CPM_MPCR_BYPASS_V(v) BM_CPM_MPCR_BYPASS | ||
557 | #define BP_CPM_MPCR_LOCK 1 | ||
558 | #define BM_CPM_MPCR_LOCK 0x2 | ||
559 | #define BF_CPM_MPCR_LOCK(v) (((v) & 0x1) << 1) | ||
560 | #define BFM_CPM_MPCR_LOCK(v) BM_CPM_MPCR_LOCK | ||
561 | #define BF_CPM_MPCR_LOCK_V(e) BF_CPM_MPCR_LOCK(BV_CPM_MPCR_LOCK__##e) | ||
562 | #define BFM_CPM_MPCR_LOCK_V(v) BM_CPM_MPCR_LOCK | ||
563 | #define BP_CPM_MPCR_ON 0 | ||
564 | #define BM_CPM_MPCR_ON 0x1 | ||
565 | #define BF_CPM_MPCR_ON(v) (((v) & 0x1) << 0) | ||
566 | #define BFM_CPM_MPCR_ON(v) BM_CPM_MPCR_ON | ||
567 | #define BF_CPM_MPCR_ON_V(e) BF_CPM_MPCR_ON(BV_CPM_MPCR_ON__##e) | ||
568 | #define BFM_CPM_MPCR_ON_V(v) BM_CPM_MPCR_ON | ||
569 | |||
570 | #define REG_CPM_LCR jz_reg(CPM_LCR) | ||
571 | #define JA_CPM_LCR (0xb0000000 + 0x4) | ||
572 | #define JT_CPM_LCR JIO_32_RW | ||
573 | #define JN_CPM_LCR CPM_LCR | ||
574 | #define JI_CPM_LCR | ||
575 | #define BP_CPM_LCR_PST 8 | ||
576 | #define BM_CPM_LCR_PST 0xfff00 | ||
577 | #define BF_CPM_LCR_PST(v) (((v) & 0xfff) << 8) | ||
578 | #define BFM_CPM_LCR_PST(v) BM_CPM_LCR_PST | ||
579 | #define BF_CPM_LCR_PST_V(e) BF_CPM_LCR_PST(BV_CPM_LCR_PST__##e) | ||
580 | #define BFM_CPM_LCR_PST_V(v) BM_CPM_LCR_PST | ||
581 | #define BP_CPM_LCR_LPM 0 | ||
582 | #define BM_CPM_LCR_LPM 0x3 | ||
583 | #define BV_CPM_LCR_LPM__IDLE 0x0 | ||
584 | #define BV_CPM_LCR_LPM__SLEEP 0x1 | ||
585 | #define BF_CPM_LCR_LPM(v) (((v) & 0x3) << 0) | ||
586 | #define BFM_CPM_LCR_LPM(v) BM_CPM_LCR_LPM | ||
587 | #define BF_CPM_LCR_LPM_V(e) BF_CPM_LCR_LPM(BV_CPM_LCR_LPM__##e) | ||
588 | #define BFM_CPM_LCR_LPM_V(v) BM_CPM_LCR_LPM | ||
589 | |||
590 | #define REG_CPM_PSWC0ST jz_reg(CPM_PSWC0ST) | ||
591 | #define JA_CPM_PSWC0ST (0xb0000000 + 0x90) | ||
592 | #define JT_CPM_PSWC0ST JIO_32_RW | ||
593 | #define JN_CPM_PSWC0ST CPM_PSWC0ST | ||
594 | #define JI_CPM_PSWC0ST | ||
595 | |||
596 | #define REG_CPM_PSWC1ST jz_reg(CPM_PSWC1ST) | ||
597 | #define JA_CPM_PSWC1ST (0xb0000000 + 0x94) | ||
598 | #define JT_CPM_PSWC1ST JIO_32_RW | ||
599 | #define JN_CPM_PSWC1ST CPM_PSWC1ST | ||
600 | #define JI_CPM_PSWC1ST | ||
601 | |||
602 | #define REG_CPM_PSWC2ST jz_reg(CPM_PSWC2ST) | ||
603 | #define JA_CPM_PSWC2ST (0xb0000000 + 0x98) | ||
604 | #define JT_CPM_PSWC2ST JIO_32_RW | ||
605 | #define JN_CPM_PSWC2ST CPM_PSWC2ST | ||
606 | #define JI_CPM_PSWC2ST | ||
607 | |||
608 | #define REG_CPM_PSWC3ST jz_reg(CPM_PSWC3ST) | ||
609 | #define JA_CPM_PSWC3ST (0xb0000000 + 0x9c) | ||
610 | #define JT_CPM_PSWC3ST JIO_32_RW | ||
611 | #define JN_CPM_PSWC3ST CPM_PSWC3ST | ||
612 | #define JI_CPM_PSWC3ST | ||
613 | |||
614 | #define REG_CPM_CLKGR jz_reg(CPM_CLKGR) | ||
615 | #define JA_CPM_CLKGR (0xb0000000 + 0x20) | ||
616 | #define JT_CPM_CLKGR JIO_32_RW | ||
617 | #define JN_CPM_CLKGR CPM_CLKGR | ||
618 | #define JI_CPM_CLKGR | ||
619 | #define BP_CPM_CLKGR_DDR 31 | ||
620 | #define BM_CPM_CLKGR_DDR 0x80000000 | ||
621 | #define BF_CPM_CLKGR_DDR(v) (((v) & 0x1) << 31) | ||
622 | #define BFM_CPM_CLKGR_DDR(v) BM_CPM_CLKGR_DDR | ||
623 | #define BF_CPM_CLKGR_DDR_V(e) BF_CPM_CLKGR_DDR(BV_CPM_CLKGR_DDR__##e) | ||
624 | #define BFM_CPM_CLKGR_DDR_V(v) BM_CPM_CLKGR_DDR | ||
625 | #define BP_CPM_CLKGR_CPU_BIT 30 | ||
626 | #define BM_CPM_CLKGR_CPU_BIT 0x40000000 | ||
627 | #define BF_CPM_CLKGR_CPU_BIT(v) (((v) & 0x1) << 30) | ||
628 | #define BFM_CPM_CLKGR_CPU_BIT(v) BM_CPM_CLKGR_CPU_BIT | ||
629 | #define BF_CPM_CLKGR_CPU_BIT_V(e) BF_CPM_CLKGR_CPU_BIT(BV_CPM_CLKGR_CPU_BIT__##e) | ||
630 | #define BFM_CPM_CLKGR_CPU_BIT_V(v) BM_CPM_CLKGR_CPU_BIT | ||
631 | #define BP_CPM_CLKGR_AHB0 29 | ||
632 | #define BM_CPM_CLKGR_AHB0 0x20000000 | ||
633 | #define BF_CPM_CLKGR_AHB0(v) (((v) & 0x1) << 29) | ||
634 | #define BFM_CPM_CLKGR_AHB0(v) BM_CPM_CLKGR_AHB0 | ||
635 | #define BF_CPM_CLKGR_AHB0_V(e) BF_CPM_CLKGR_AHB0(BV_CPM_CLKGR_AHB0__##e) | ||
636 | #define BFM_CPM_CLKGR_AHB0_V(v) BM_CPM_CLKGR_AHB0 | ||
637 | #define BP_CPM_CLKGR_APB0 28 | ||
638 | #define BM_CPM_CLKGR_APB0 0x10000000 | ||
639 | #define BF_CPM_CLKGR_APB0(v) (((v) & 0x1) << 28) | ||
640 | #define BFM_CPM_CLKGR_APB0(v) BM_CPM_CLKGR_APB0 | ||
641 | #define BF_CPM_CLKGR_APB0_V(e) BF_CPM_CLKGR_APB0(BV_CPM_CLKGR_APB0__##e) | ||
642 | #define BFM_CPM_CLKGR_APB0_V(v) BM_CPM_CLKGR_APB0 | ||
643 | #define BP_CPM_CLKGR_RTC 27 | ||
644 | #define BM_CPM_CLKGR_RTC 0x8000000 | ||
645 | #define BF_CPM_CLKGR_RTC(v) (((v) & 0x1) << 27) | ||
646 | #define BFM_CPM_CLKGR_RTC(v) BM_CPM_CLKGR_RTC | ||
647 | #define BF_CPM_CLKGR_RTC_V(e) BF_CPM_CLKGR_RTC(BV_CPM_CLKGR_RTC__##e) | ||
648 | #define BFM_CPM_CLKGR_RTC_V(v) BM_CPM_CLKGR_RTC | ||
649 | #define BP_CPM_CLKGR_PCM 26 | ||
650 | #define BM_CPM_CLKGR_PCM 0x4000000 | ||
651 | #define BF_CPM_CLKGR_PCM(v) (((v) & 0x1) << 26) | ||
652 | #define BFM_CPM_CLKGR_PCM(v) BM_CPM_CLKGR_PCM | ||
653 | #define BF_CPM_CLKGR_PCM_V(e) BF_CPM_CLKGR_PCM(BV_CPM_CLKGR_PCM__##e) | ||
654 | #define BFM_CPM_CLKGR_PCM_V(v) BM_CPM_CLKGR_PCM | ||
655 | #define BP_CPM_CLKGR_MAC 25 | ||
656 | #define BM_CPM_CLKGR_MAC 0x2000000 | ||
657 | #define BF_CPM_CLKGR_MAC(v) (((v) & 0x1) << 25) | ||
658 | #define BFM_CPM_CLKGR_MAC(v) BM_CPM_CLKGR_MAC | ||
659 | #define BF_CPM_CLKGR_MAC_V(e) BF_CPM_CLKGR_MAC(BV_CPM_CLKGR_MAC__##e) | ||
660 | #define BFM_CPM_CLKGR_MAC_V(v) BM_CPM_CLKGR_MAC | ||
661 | #define BP_CPM_CLKGR_AES 24 | ||
662 | #define BM_CPM_CLKGR_AES 0x1000000 | ||
663 | #define BF_CPM_CLKGR_AES(v) (((v) & 0x1) << 24) | ||
664 | #define BFM_CPM_CLKGR_AES(v) BM_CPM_CLKGR_AES | ||
665 | #define BF_CPM_CLKGR_AES_V(e) BF_CPM_CLKGR_AES(BV_CPM_CLKGR_AES__##e) | ||
666 | #define BFM_CPM_CLKGR_AES_V(v) BM_CPM_CLKGR_AES | ||
667 | #define BP_CPM_CLKGR_LCD 23 | ||
668 | #define BM_CPM_CLKGR_LCD 0x800000 | ||
669 | #define BF_CPM_CLKGR_LCD(v) (((v) & 0x1) << 23) | ||
670 | #define BFM_CPM_CLKGR_LCD(v) BM_CPM_CLKGR_LCD | ||
671 | #define BF_CPM_CLKGR_LCD_V(e) BF_CPM_CLKGR_LCD(BV_CPM_CLKGR_LCD__##e) | ||
672 | #define BFM_CPM_CLKGR_LCD_V(v) BM_CPM_CLKGR_LCD | ||
673 | #define BP_CPM_CLKGR_CIM 22 | ||
674 | #define BM_CPM_CLKGR_CIM 0x400000 | ||
675 | #define BF_CPM_CLKGR_CIM(v) (((v) & 0x1) << 22) | ||
676 | #define BFM_CPM_CLKGR_CIM(v) BM_CPM_CLKGR_CIM | ||
677 | #define BF_CPM_CLKGR_CIM_V(e) BF_CPM_CLKGR_CIM(BV_CPM_CLKGR_CIM__##e) | ||
678 | #define BFM_CPM_CLKGR_CIM_V(v) BM_CPM_CLKGR_CIM | ||
679 | #define BP_CPM_CLKGR_PDMA 21 | ||
680 | #define BM_CPM_CLKGR_PDMA 0x200000 | ||
681 | #define BF_CPM_CLKGR_PDMA(v) (((v) & 0x1) << 21) | ||
682 | #define BFM_CPM_CLKGR_PDMA(v) BM_CPM_CLKGR_PDMA | ||
683 | #define BF_CPM_CLKGR_PDMA_V(e) BF_CPM_CLKGR_PDMA(BV_CPM_CLKGR_PDMA__##e) | ||
684 | #define BFM_CPM_CLKGR_PDMA_V(v) BM_CPM_CLKGR_PDMA | ||
685 | #define BP_CPM_CLKGR_OST 20 | ||
686 | #define BM_CPM_CLKGR_OST 0x100000 | ||
687 | #define BF_CPM_CLKGR_OST(v) (((v) & 0x1) << 20) | ||
688 | #define BFM_CPM_CLKGR_OST(v) BM_CPM_CLKGR_OST | ||
689 | #define BF_CPM_CLKGR_OST_V(e) BF_CPM_CLKGR_OST(BV_CPM_CLKGR_OST__##e) | ||
690 | #define BFM_CPM_CLKGR_OST_V(v) BM_CPM_CLKGR_OST | ||
691 | #define BP_CPM_CLKGR_SSI 19 | ||
692 | #define BM_CPM_CLKGR_SSI 0x80000 | ||
693 | #define BF_CPM_CLKGR_SSI(v) (((v) & 0x1) << 19) | ||
694 | #define BFM_CPM_CLKGR_SSI(v) BM_CPM_CLKGR_SSI | ||
695 | #define BF_CPM_CLKGR_SSI_V(e) BF_CPM_CLKGR_SSI(BV_CPM_CLKGR_SSI__##e) | ||
696 | #define BFM_CPM_CLKGR_SSI_V(v) BM_CPM_CLKGR_SSI | ||
697 | #define BP_CPM_CLKGR_TCU 18 | ||
698 | #define BM_CPM_CLKGR_TCU 0x40000 | ||
699 | #define BF_CPM_CLKGR_TCU(v) (((v) & 0x1) << 18) | ||
700 | #define BFM_CPM_CLKGR_TCU(v) BM_CPM_CLKGR_TCU | ||
701 | #define BF_CPM_CLKGR_TCU_V(e) BF_CPM_CLKGR_TCU(BV_CPM_CLKGR_TCU__##e) | ||
702 | #define BFM_CPM_CLKGR_TCU_V(v) BM_CPM_CLKGR_TCU | ||
703 | #define BP_CPM_CLKGR_DMIC 17 | ||
704 | #define BM_CPM_CLKGR_DMIC 0x20000 | ||
705 | #define BF_CPM_CLKGR_DMIC(v) (((v) & 0x1) << 17) | ||
706 | #define BFM_CPM_CLKGR_DMIC(v) BM_CPM_CLKGR_DMIC | ||
707 | #define BF_CPM_CLKGR_DMIC_V(e) BF_CPM_CLKGR_DMIC(BV_CPM_CLKGR_DMIC__##e) | ||
708 | #define BFM_CPM_CLKGR_DMIC_V(v) BM_CPM_CLKGR_DMIC | ||
709 | #define BP_CPM_CLKGR_UART2 16 | ||
710 | #define BM_CPM_CLKGR_UART2 0x10000 | ||
711 | #define BF_CPM_CLKGR_UART2(v) (((v) & 0x1) << 16) | ||
712 | #define BFM_CPM_CLKGR_UART2(v) BM_CPM_CLKGR_UART2 | ||
713 | #define BF_CPM_CLKGR_UART2_V(e) BF_CPM_CLKGR_UART2(BV_CPM_CLKGR_UART2__##e) | ||
714 | #define BFM_CPM_CLKGR_UART2_V(v) BM_CPM_CLKGR_UART2 | ||
715 | #define BP_CPM_CLKGR_UART1 15 | ||
716 | #define BM_CPM_CLKGR_UART1 0x8000 | ||
717 | #define BF_CPM_CLKGR_UART1(v) (((v) & 0x1) << 15) | ||
718 | #define BFM_CPM_CLKGR_UART1(v) BM_CPM_CLKGR_UART1 | ||
719 | #define BF_CPM_CLKGR_UART1_V(e) BF_CPM_CLKGR_UART1(BV_CPM_CLKGR_UART1__##e) | ||
720 | #define BFM_CPM_CLKGR_UART1_V(v) BM_CPM_CLKGR_UART1 | ||
721 | #define BP_CPM_CLKGR_UART0 14 | ||
722 | #define BM_CPM_CLKGR_UART0 0x4000 | ||
723 | #define BF_CPM_CLKGR_UART0(v) (((v) & 0x1) << 14) | ||
724 | #define BFM_CPM_CLKGR_UART0(v) BM_CPM_CLKGR_UART0 | ||
725 | #define BF_CPM_CLKGR_UART0_V(e) BF_CPM_CLKGR_UART0(BV_CPM_CLKGR_UART0__##e) | ||
726 | #define BFM_CPM_CLKGR_UART0_V(v) BM_CPM_CLKGR_UART0 | ||
727 | #define BP_CPM_CLKGR_JPEG 12 | ||
728 | #define BM_CPM_CLKGR_JPEG 0x1000 | ||
729 | #define BF_CPM_CLKGR_JPEG(v) (((v) & 0x1) << 12) | ||
730 | #define BFM_CPM_CLKGR_JPEG(v) BM_CPM_CLKGR_JPEG | ||
731 | #define BF_CPM_CLKGR_JPEG_V(e) BF_CPM_CLKGR_JPEG(BV_CPM_CLKGR_JPEG__##e) | ||
732 | #define BFM_CPM_CLKGR_JPEG_V(v) BM_CPM_CLKGR_JPEG | ||
733 | #define BP_CPM_CLKGR_AIC 11 | ||
734 | #define BM_CPM_CLKGR_AIC 0x800 | ||
735 | #define BF_CPM_CLKGR_AIC(v) (((v) & 0x1) << 11) | ||
736 | #define BFM_CPM_CLKGR_AIC(v) BM_CPM_CLKGR_AIC | ||
737 | #define BF_CPM_CLKGR_AIC_V(e) BF_CPM_CLKGR_AIC(BV_CPM_CLKGR_AIC__##e) | ||
738 | #define BFM_CPM_CLKGR_AIC_V(v) BM_CPM_CLKGR_AIC | ||
739 | #define BP_CPM_CLKGR_I2C2 9 | ||
740 | #define BM_CPM_CLKGR_I2C2 0x200 | ||
741 | #define BF_CPM_CLKGR_I2C2(v) (((v) & 0x1) << 9) | ||
742 | #define BFM_CPM_CLKGR_I2C2(v) BM_CPM_CLKGR_I2C2 | ||
743 | #define BF_CPM_CLKGR_I2C2_V(e) BF_CPM_CLKGR_I2C2(BV_CPM_CLKGR_I2C2__##e) | ||
744 | #define BFM_CPM_CLKGR_I2C2_V(v) BM_CPM_CLKGR_I2C2 | ||
745 | #define BP_CPM_CLKGR_I2C1 8 | ||
746 | #define BM_CPM_CLKGR_I2C1 0x100 | ||
747 | #define BF_CPM_CLKGR_I2C1(v) (((v) & 0x1) << 8) | ||
748 | #define BFM_CPM_CLKGR_I2C1(v) BM_CPM_CLKGR_I2C1 | ||
749 | #define BF_CPM_CLKGR_I2C1_V(e) BF_CPM_CLKGR_I2C1(BV_CPM_CLKGR_I2C1__##e) | ||
750 | #define BFM_CPM_CLKGR_I2C1_V(v) BM_CPM_CLKGR_I2C1 | ||
751 | #define BP_CPM_CLKGR_I2C0 7 | ||
752 | #define BM_CPM_CLKGR_I2C0 0x80 | ||
753 | #define BF_CPM_CLKGR_I2C0(v) (((v) & 0x1) << 7) | ||
754 | #define BFM_CPM_CLKGR_I2C0(v) BM_CPM_CLKGR_I2C0 | ||
755 | #define BF_CPM_CLKGR_I2C0_V(e) BF_CPM_CLKGR_I2C0(BV_CPM_CLKGR_I2C0__##e) | ||
756 | #define BFM_CPM_CLKGR_I2C0_V(v) BM_CPM_CLKGR_I2C0 | ||
757 | #define BP_CPM_CLKGR_SCC 6 | ||
758 | #define BM_CPM_CLKGR_SCC 0x40 | ||
759 | #define BF_CPM_CLKGR_SCC(v) (((v) & 0x1) << 6) | ||
760 | #define BFM_CPM_CLKGR_SCC(v) BM_CPM_CLKGR_SCC | ||
761 | #define BF_CPM_CLKGR_SCC_V(e) BF_CPM_CLKGR_SCC(BV_CPM_CLKGR_SCC__##e) | ||
762 | #define BFM_CPM_CLKGR_SCC_V(v) BM_CPM_CLKGR_SCC | ||
763 | #define BP_CPM_CLKGR_MSC1 5 | ||
764 | #define BM_CPM_CLKGR_MSC1 0x20 | ||
765 | #define BF_CPM_CLKGR_MSC1(v) (((v) & 0x1) << 5) | ||
766 | #define BFM_CPM_CLKGR_MSC1(v) BM_CPM_CLKGR_MSC1 | ||
767 | #define BF_CPM_CLKGR_MSC1_V(e) BF_CPM_CLKGR_MSC1(BV_CPM_CLKGR_MSC1__##e) | ||
768 | #define BFM_CPM_CLKGR_MSC1_V(v) BM_CPM_CLKGR_MSC1 | ||
769 | #define BP_CPM_CLKGR_MSC0 4 | ||
770 | #define BM_CPM_CLKGR_MSC0 0x10 | ||
771 | #define BF_CPM_CLKGR_MSC0(v) (((v) & 0x1) << 4) | ||
772 | #define BFM_CPM_CLKGR_MSC0(v) BM_CPM_CLKGR_MSC0 | ||
773 | #define BF_CPM_CLKGR_MSC0_V(e) BF_CPM_CLKGR_MSC0(BV_CPM_CLKGR_MSC0__##e) | ||
774 | #define BFM_CPM_CLKGR_MSC0_V(v) BM_CPM_CLKGR_MSC0 | ||
775 | #define BP_CPM_CLKGR_OTG 3 | ||
776 | #define BM_CPM_CLKGR_OTG 0x8 | ||
777 | #define BF_CPM_CLKGR_OTG(v) (((v) & 0x1) << 3) | ||
778 | #define BFM_CPM_CLKGR_OTG(v) BM_CPM_CLKGR_OTG | ||
779 | #define BF_CPM_CLKGR_OTG_V(e) BF_CPM_CLKGR_OTG(BV_CPM_CLKGR_OTG__##e) | ||
780 | #define BFM_CPM_CLKGR_OTG_V(v) BM_CPM_CLKGR_OTG | ||
781 | #define BP_CPM_CLKGR_SFC 2 | ||
782 | #define BM_CPM_CLKGR_SFC 0x4 | ||
783 | #define BF_CPM_CLKGR_SFC(v) (((v) & 0x1) << 2) | ||
784 | #define BFM_CPM_CLKGR_SFC(v) BM_CPM_CLKGR_SFC | ||
785 | #define BF_CPM_CLKGR_SFC_V(e) BF_CPM_CLKGR_SFC(BV_CPM_CLKGR_SFC__##e) | ||
786 | #define BFM_CPM_CLKGR_SFC_V(v) BM_CPM_CLKGR_SFC | ||
787 | #define BP_CPM_CLKGR_EFUSE 1 | ||
788 | #define BM_CPM_CLKGR_EFUSE 0x2 | ||
789 | #define BF_CPM_CLKGR_EFUSE(v) (((v) & 0x1) << 1) | ||
790 | #define BFM_CPM_CLKGR_EFUSE(v) BM_CPM_CLKGR_EFUSE | ||
791 | #define BF_CPM_CLKGR_EFUSE_V(e) BF_CPM_CLKGR_EFUSE(BV_CPM_CLKGR_EFUSE__##e) | ||
792 | #define BFM_CPM_CLKGR_EFUSE_V(v) BM_CPM_CLKGR_EFUSE | ||
793 | |||
794 | #define REG_CPM_OPCR jz_reg(CPM_OPCR) | ||
795 | #define JA_CPM_OPCR (0xb0000000 + 0x24) | ||
796 | #define JT_CPM_OPCR JIO_32_RW | ||
797 | #define JN_CPM_OPCR CPM_OPCR | ||
798 | #define JI_CPM_OPCR | ||
799 | #define BP_CPM_OPCR_O1ST 8 | ||
800 | #define BM_CPM_OPCR_O1ST 0xfff00 | ||
801 | #define BF_CPM_OPCR_O1ST(v) (((v) & 0xfff) << 8) | ||
802 | #define BFM_CPM_OPCR_O1ST(v) BM_CPM_OPCR_O1ST | ||
803 | #define BF_CPM_OPCR_O1ST_V(e) BF_CPM_OPCR_O1ST(BV_CPM_OPCR_O1ST__##e) | ||
804 | #define BFM_CPM_OPCR_O1ST_V(v) BM_CPM_OPCR_O1ST | ||
805 | #define BP_CPM_OPCR_IDLE_DIS 31 | ||
806 | #define BM_CPM_OPCR_IDLE_DIS 0x80000000 | ||
807 | #define BF_CPM_OPCR_IDLE_DIS(v) (((v) & 0x1) << 31) | ||
808 | #define BFM_CPM_OPCR_IDLE_DIS(v) BM_CPM_OPCR_IDLE_DIS | ||
809 | #define BF_CPM_OPCR_IDLE_DIS_V(e) BF_CPM_OPCR_IDLE_DIS(BV_CPM_OPCR_IDLE_DIS__##e) | ||
810 | #define BFM_CPM_OPCR_IDLE_DIS_V(v) BM_CPM_OPCR_IDLE_DIS | ||
811 | #define BP_CPM_OPCR_MASK_INT 30 | ||
812 | #define BM_CPM_OPCR_MASK_INT 0x40000000 | ||
813 | #define BF_CPM_OPCR_MASK_INT(v) (((v) & 0x1) << 30) | ||
814 | #define BFM_CPM_OPCR_MASK_INT(v) BM_CPM_OPCR_MASK_INT | ||
815 | #define BF_CPM_OPCR_MASK_INT_V(e) BF_CPM_OPCR_MASK_INT(BV_CPM_OPCR_MASK_INT__##e) | ||
816 | #define BFM_CPM_OPCR_MASK_INT_V(v) BM_CPM_OPCR_MASK_INT | ||
817 | #define BP_CPM_OPCR_MASK_VPU 29 | ||
818 | #define BM_CPM_OPCR_MASK_VPU 0x20000000 | ||
819 | #define BF_CPM_OPCR_MASK_VPU(v) (((v) & 0x1) << 29) | ||
820 | #define BFM_CPM_OPCR_MASK_VPU(v) BM_CPM_OPCR_MASK_VPU | ||
821 | #define BF_CPM_OPCR_MASK_VPU_V(e) BF_CPM_OPCR_MASK_VPU(BV_CPM_OPCR_MASK_VPU__##e) | ||
822 | #define BFM_CPM_OPCR_MASK_VPU_V(v) BM_CPM_OPCR_MASK_VPU | ||
823 | #define BP_CPM_OPCR_GATE_SCLK_A_BUS 28 | ||
824 | #define BM_CPM_OPCR_GATE_SCLK_A_BUS 0x10000000 | ||
825 | #define BF_CPM_OPCR_GATE_SCLK_A_BUS(v) (((v) & 0x1) << 28) | ||
826 | #define BFM_CPM_OPCR_GATE_SCLK_A_BUS(v) BM_CPM_OPCR_GATE_SCLK_A_BUS | ||
827 | #define BF_CPM_OPCR_GATE_SCLK_A_BUS_V(e) BF_CPM_OPCR_GATE_SCLK_A_BUS(BV_CPM_OPCR_GATE_SCLK_A_BUS__##e) | ||
828 | #define BFM_CPM_OPCR_GATE_SCLK_A_BUS_V(v) BM_CPM_OPCR_GATE_SCLK_A_BUS | ||
829 | #define BP_CPM_OPCR_L2C_PD 25 | ||
830 | #define BM_CPM_OPCR_L2C_PD 0x2000000 | ||
831 | #define BF_CPM_OPCR_L2C_PD(v) (((v) & 0x1) << 25) | ||
832 | #define BFM_CPM_OPCR_L2C_PD(v) BM_CPM_OPCR_L2C_PD | ||
833 | #define BF_CPM_OPCR_L2C_PD_V(e) BF_CPM_OPCR_L2C_PD(BV_CPM_OPCR_L2C_PD__##e) | ||
834 | #define BFM_CPM_OPCR_L2C_PD_V(v) BM_CPM_OPCR_L2C_PD | ||
835 | #define BP_CPM_OPCR_REQ_MODE 24 | ||
836 | #define BM_CPM_OPCR_REQ_MODE 0x1000000 | ||
837 | #define BF_CPM_OPCR_REQ_MODE(v) (((v) & 0x1) << 24) | ||
838 | #define BFM_CPM_OPCR_REQ_MODE(v) BM_CPM_OPCR_REQ_MODE | ||
839 | #define BF_CPM_OPCR_REQ_MODE_V(e) BF_CPM_OPCR_REQ_MODE(BV_CPM_OPCR_REQ_MODE__##e) | ||
840 | #define BFM_CPM_OPCR_REQ_MODE_V(v) BM_CPM_OPCR_REQ_MODE | ||
841 | #define BP_CPM_OPCR_GATE_USBPHY_CLK 23 | ||
842 | #define BM_CPM_OPCR_GATE_USBPHY_CLK 0x800000 | ||
843 | #define BF_CPM_OPCR_GATE_USBPHY_CLK(v) (((v) & 0x1) << 23) | ||
844 | #define BFM_CPM_OPCR_GATE_USBPHY_CLK(v) BM_CPM_OPCR_GATE_USBPHY_CLK | ||
845 | #define BF_CPM_OPCR_GATE_USBPHY_CLK_V(e) BF_CPM_OPCR_GATE_USBPHY_CLK(BV_CPM_OPCR_GATE_USBPHY_CLK__##e) | ||
846 | #define BFM_CPM_OPCR_GATE_USBPHY_CLK_V(v) BM_CPM_OPCR_GATE_USBPHY_CLK | ||
847 | #define BP_CPM_OPCR_DIS_STOP_MUX 22 | ||
848 | #define BM_CPM_OPCR_DIS_STOP_MUX 0x400000 | ||
849 | #define BF_CPM_OPCR_DIS_STOP_MUX(v) (((v) & 0x1) << 22) | ||
850 | #define BFM_CPM_OPCR_DIS_STOP_MUX(v) BM_CPM_OPCR_DIS_STOP_MUX | ||
851 | #define BF_CPM_OPCR_DIS_STOP_MUX_V(e) BF_CPM_OPCR_DIS_STOP_MUX(BV_CPM_OPCR_DIS_STOP_MUX__##e) | ||
852 | #define BFM_CPM_OPCR_DIS_STOP_MUX_V(v) BM_CPM_OPCR_DIS_STOP_MUX | ||
853 | #define BP_CPM_OPCR_SPENDN0 7 | ||
854 | #define BM_CPM_OPCR_SPENDN0 0x80 | ||
855 | #define BF_CPM_OPCR_SPENDN0(v) (((v) & 0x1) << 7) | ||
856 | #define BFM_CPM_OPCR_SPENDN0(v) BM_CPM_OPCR_SPENDN0 | ||
857 | #define BF_CPM_OPCR_SPENDN0_V(e) BF_CPM_OPCR_SPENDN0(BV_CPM_OPCR_SPENDN0__##e) | ||
858 | #define BFM_CPM_OPCR_SPENDN0_V(v) BM_CPM_OPCR_SPENDN0 | ||
859 | #define BP_CPM_OPCR_SPENDN1 6 | ||
860 | #define BM_CPM_OPCR_SPENDN1 0x40 | ||
861 | #define BF_CPM_OPCR_SPENDN1(v) (((v) & 0x1) << 6) | ||
862 | #define BFM_CPM_OPCR_SPENDN1(v) BM_CPM_OPCR_SPENDN1 | ||
863 | #define BF_CPM_OPCR_SPENDN1_V(e) BF_CPM_OPCR_SPENDN1(BV_CPM_OPCR_SPENDN1__##e) | ||
864 | #define BFM_CPM_OPCR_SPENDN1_V(v) BM_CPM_OPCR_SPENDN1 | ||
865 | #define BP_CPM_OPCR_CPU_MODE 5 | ||
866 | #define BM_CPM_OPCR_CPU_MODE 0x20 | ||
867 | #define BF_CPM_OPCR_CPU_MODE(v) (((v) & 0x1) << 5) | ||
868 | #define BFM_CPM_OPCR_CPU_MODE(v) BM_CPM_OPCR_CPU_MODE | ||
869 | #define BF_CPM_OPCR_CPU_MODE_V(e) BF_CPM_OPCR_CPU_MODE(BV_CPM_OPCR_CPU_MODE__##e) | ||
870 | #define BFM_CPM_OPCR_CPU_MODE_V(v) BM_CPM_OPCR_CPU_MODE | ||
871 | #define BP_CPM_OPCR_O1SE 4 | ||
872 | #define BM_CPM_OPCR_O1SE 0x10 | ||
873 | #define BF_CPM_OPCR_O1SE(v) (((v) & 0x1) << 4) | ||
874 | #define BFM_CPM_OPCR_O1SE(v) BM_CPM_OPCR_O1SE | ||
875 | #define BF_CPM_OPCR_O1SE_V(e) BF_CPM_OPCR_O1SE(BV_CPM_OPCR_O1SE__##e) | ||
876 | #define BFM_CPM_OPCR_O1SE_V(v) BM_CPM_OPCR_O1SE | ||
877 | #define BP_CPM_OPCR_PD 3 | ||
878 | #define BM_CPM_OPCR_PD 0x8 | ||
879 | #define BF_CPM_OPCR_PD(v) (((v) & 0x1) << 3) | ||
880 | #define BFM_CPM_OPCR_PD(v) BM_CPM_OPCR_PD | ||
881 | #define BF_CPM_OPCR_PD_V(e) BF_CPM_OPCR_PD(BV_CPM_OPCR_PD__##e) | ||
882 | #define BFM_CPM_OPCR_PD_V(v) BM_CPM_OPCR_PD | ||
883 | #define BP_CPM_OPCR_ERCS 2 | ||
884 | #define BM_CPM_OPCR_ERCS 0x4 | ||
885 | #define BF_CPM_OPCR_ERCS(v) (((v) & 0x1) << 2) | ||
886 | #define BFM_CPM_OPCR_ERCS(v) BM_CPM_OPCR_ERCS | ||
887 | #define BF_CPM_OPCR_ERCS_V(e) BF_CPM_OPCR_ERCS(BV_CPM_OPCR_ERCS__##e) | ||
888 | #define BFM_CPM_OPCR_ERCS_V(v) BM_CPM_OPCR_ERCS | ||
889 | #define BP_CPM_OPCR_BUS_MODE 1 | ||
890 | #define BM_CPM_OPCR_BUS_MODE 0x2 | ||
891 | #define BF_CPM_OPCR_BUS_MODE(v) (((v) & 0x1) << 1) | ||
892 | #define BFM_CPM_OPCR_BUS_MODE(v) BM_CPM_OPCR_BUS_MODE | ||
893 | #define BF_CPM_OPCR_BUS_MODE_V(e) BF_CPM_OPCR_BUS_MODE(BV_CPM_OPCR_BUS_MODE__##e) | ||
894 | #define BFM_CPM_OPCR_BUS_MODE_V(v) BM_CPM_OPCR_BUS_MODE | ||
895 | |||
896 | #endif /* __HEADERGEN_CPM_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/ddrc.h b/firmware/target/mips/ingenic_x1000/x1000/ddrc.h new file mode 100644 index 0000000000..f482969a4e --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/ddrc.h | |||
@@ -0,0 +1,149 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_DDRC_H__ | ||
25 | #define __HEADERGEN_DDRC_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_DDRC_STATUS jz_reg(DDRC_STATUS) | ||
30 | #define JA_DDRC_STATUS (0xb34f0000 + 0x0) | ||
31 | #define JT_DDRC_STATUS JIO_32_RW | ||
32 | #define JN_DDRC_STATUS DDRC_STATUS | ||
33 | #define JI_DDRC_STATUS | ||
34 | |||
35 | #define REG_DDRC_CFG jz_reg(DDRC_CFG) | ||
36 | #define JA_DDRC_CFG (0xb34f0000 + 0x4) | ||
37 | #define JT_DDRC_CFG JIO_32_RW | ||
38 | #define JN_DDRC_CFG DDRC_CFG | ||
39 | #define JI_DDRC_CFG | ||
40 | |||
41 | #define REG_DDRC_CTRL jz_reg(DDRC_CTRL) | ||
42 | #define JA_DDRC_CTRL (0xb34f0000 + 0x8) | ||
43 | #define JT_DDRC_CTRL JIO_32_RW | ||
44 | #define JN_DDRC_CTRL DDRC_CTRL | ||
45 | #define JI_DDRC_CTRL | ||
46 | |||
47 | #define REG_DDRC_TIMING1 jz_reg(DDRC_TIMING1) | ||
48 | #define JA_DDRC_TIMING1 (0xb34f0000 + 0x60) | ||
49 | #define JT_DDRC_TIMING1 JIO_32_RW | ||
50 | #define JN_DDRC_TIMING1 DDRC_TIMING1 | ||
51 | #define JI_DDRC_TIMING1 | ||
52 | |||
53 | #define REG_DDRC_TIMING2 jz_reg(DDRC_TIMING2) | ||
54 | #define JA_DDRC_TIMING2 (0xb34f0000 + 0x64) | ||
55 | #define JT_DDRC_TIMING2 JIO_32_RW | ||
56 | #define JN_DDRC_TIMING2 DDRC_TIMING2 | ||
57 | #define JI_DDRC_TIMING2 | ||
58 | |||
59 | #define REG_DDRC_TIMING3 jz_reg(DDRC_TIMING3) | ||
60 | #define JA_DDRC_TIMING3 (0xb34f0000 + 0x68) | ||
61 | #define JT_DDRC_TIMING3 JIO_32_RW | ||
62 | #define JN_DDRC_TIMING3 DDRC_TIMING3 | ||
63 | #define JI_DDRC_TIMING3 | ||
64 | |||
65 | #define REG_DDRC_TIMING4 jz_reg(DDRC_TIMING4) | ||
66 | #define JA_DDRC_TIMING4 (0xb34f0000 + 0x6c) | ||
67 | #define JT_DDRC_TIMING4 JIO_32_RW | ||
68 | #define JN_DDRC_TIMING4 DDRC_TIMING4 | ||
69 | #define JI_DDRC_TIMING4 | ||
70 | |||
71 | #define REG_DDRC_TIMING5 jz_reg(DDRC_TIMING5) | ||
72 | #define JA_DDRC_TIMING5 (0xb34f0000 + 0x70) | ||
73 | #define JT_DDRC_TIMING5 JIO_32_RW | ||
74 | #define JN_DDRC_TIMING5 DDRC_TIMING5 | ||
75 | #define JI_DDRC_TIMING5 | ||
76 | |||
77 | #define REG_DDRC_TIMING6 jz_reg(DDRC_TIMING6) | ||
78 | #define JA_DDRC_TIMING6 (0xb34f0000 + 0x74) | ||
79 | #define JT_DDRC_TIMING6 JIO_32_RW | ||
80 | #define JN_DDRC_TIMING6 DDRC_TIMING6 | ||
81 | #define JI_DDRC_TIMING6 | ||
82 | |||
83 | #define REG_DDRC_REFCNT jz_reg(DDRC_REFCNT) | ||
84 | #define JA_DDRC_REFCNT (0xb34f0000 + 0x18) | ||
85 | #define JT_DDRC_REFCNT JIO_32_RW | ||
86 | #define JN_DDRC_REFCNT DDRC_REFCNT | ||
87 | #define JI_DDRC_REFCNT | ||
88 | |||
89 | #define REG_DDRC_MMAP0 jz_reg(DDRC_MMAP0) | ||
90 | #define JA_DDRC_MMAP0 (0xb34f0000 + 0x24) | ||
91 | #define JT_DDRC_MMAP0 JIO_32_RW | ||
92 | #define JN_DDRC_MMAP0 DDRC_MMAP0 | ||
93 | #define JI_DDRC_MMAP0 | ||
94 | |||
95 | #define REG_DDRC_MMAP1 jz_reg(DDRC_MMAP1) | ||
96 | #define JA_DDRC_MMAP1 (0xb34f0000 + 0x28) | ||
97 | #define JT_DDRC_MMAP1 JIO_32_RW | ||
98 | #define JN_DDRC_MMAP1 DDRC_MMAP1 | ||
99 | #define JI_DDRC_MMAP1 | ||
100 | |||
101 | #define REG_DDRC_DLP jz_reg(DDRC_DLP) | ||
102 | #define JA_DDRC_DLP (0xb34f0000 + 0xbc) | ||
103 | #define JT_DDRC_DLP JIO_32_RW | ||
104 | #define JN_DDRC_DLP DDRC_DLP | ||
105 | #define JI_DDRC_DLP | ||
106 | |||
107 | #define REG_DDRC_REMAP1 jz_reg(DDRC_REMAP1) | ||
108 | #define JA_DDRC_REMAP1 (0xb34f0000 + 0x9c) | ||
109 | #define JT_DDRC_REMAP1 JIO_32_RW | ||
110 | #define JN_DDRC_REMAP1 DDRC_REMAP1 | ||
111 | #define JI_DDRC_REMAP1 | ||
112 | |||
113 | #define REG_DDRC_REMAP2 jz_reg(DDRC_REMAP2) | ||
114 | #define JA_DDRC_REMAP2 (0xb34f0000 + 0xa0) | ||
115 | #define JT_DDRC_REMAP2 JIO_32_RW | ||
116 | #define JN_DDRC_REMAP2 DDRC_REMAP2 | ||
117 | #define JI_DDRC_REMAP2 | ||
118 | |||
119 | #define REG_DDRC_REMAP3 jz_reg(DDRC_REMAP3) | ||
120 | #define JA_DDRC_REMAP3 (0xb34f0000 + 0xa4) | ||
121 | #define JT_DDRC_REMAP3 JIO_32_RW | ||
122 | #define JN_DDRC_REMAP3 DDRC_REMAP3 | ||
123 | #define JI_DDRC_REMAP3 | ||
124 | |||
125 | #define REG_DDRC_REMAP4 jz_reg(DDRC_REMAP4) | ||
126 | #define JA_DDRC_REMAP4 (0xb34f0000 + 0xa8) | ||
127 | #define JT_DDRC_REMAP4 JIO_32_RW | ||
128 | #define JN_DDRC_REMAP4 DDRC_REMAP4 | ||
129 | #define JI_DDRC_REMAP4 | ||
130 | |||
131 | #define REG_DDRC_REMAP5 jz_reg(DDRC_REMAP5) | ||
132 | #define JA_DDRC_REMAP5 (0xb34f0000 + 0xac) | ||
133 | #define JT_DDRC_REMAP5 JIO_32_RW | ||
134 | #define JN_DDRC_REMAP5 DDRC_REMAP5 | ||
135 | #define JI_DDRC_REMAP5 | ||
136 | |||
137 | #define REG_DDRC_AUTOSR_CNT jz_reg(DDRC_AUTOSR_CNT) | ||
138 | #define JA_DDRC_AUTOSR_CNT (0xb34f0000 + 0x308) | ||
139 | #define JT_DDRC_AUTOSR_CNT JIO_32_RW | ||
140 | #define JN_DDRC_AUTOSR_CNT DDRC_AUTOSR_CNT | ||
141 | #define JI_DDRC_AUTOSR_CNT | ||
142 | |||
143 | #define REG_DDRC_AUTOSR_EN jz_reg(DDRC_AUTOSR_EN) | ||
144 | #define JA_DDRC_AUTOSR_EN (0xb34f0000 + 0x304) | ||
145 | #define JT_DDRC_AUTOSR_EN JIO_32_RW | ||
146 | #define JN_DDRC_AUTOSR_EN DDRC_AUTOSR_EN | ||
147 | #define JI_DDRC_AUTOSR_EN | ||
148 | |||
149 | #endif /* __HEADERGEN_DDRC_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/ddrc_apb.h b/firmware/target/mips/ingenic_x1000/x1000/ddrc_apb.h new file mode 100644 index 0000000000..bcb880624f --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/ddrc_apb.h | |||
@@ -0,0 +1,41 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_DDRC_APB_H__ | ||
25 | #define __HEADERGEN_DDRC_APB_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_DDRC_APB_CLKSTP_CFG jz_reg(DDRC_APB_CLKSTP_CFG) | ||
30 | #define JA_DDRC_APB_CLKSTP_CFG (0xb3012000 + 0x68) | ||
31 | #define JT_DDRC_APB_CLKSTP_CFG JIO_32_RW | ||
32 | #define JN_DDRC_APB_CLKSTP_CFG DDRC_APB_CLKSTP_CFG | ||
33 | #define JI_DDRC_APB_CLKSTP_CFG | ||
34 | |||
35 | #define REG_DDRC_APB_PHYRST_CFG jz_reg(DDRC_APB_PHYRST_CFG) | ||
36 | #define JA_DDRC_APB_PHYRST_CFG (0xb3012000 + 0x80) | ||
37 | #define JT_DDRC_APB_PHYRST_CFG JIO_32_RW | ||
38 | #define JN_DDRC_APB_PHYRST_CFG DDRC_APB_PHYRST_CFG | ||
39 | #define JI_DDRC_APB_PHYRST_CFG | ||
40 | |||
41 | #endif /* __HEADERGEN_DDRC_APB_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/ddrphy.h b/firmware/target/mips/ingenic_x1000/x1000/ddrphy.h new file mode 100644 index 0000000000..2ac0563090 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/ddrphy.h | |||
@@ -0,0 +1,155 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_DDRPHY_H__ | ||
25 | #define __HEADERGEN_DDRPHY_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_DDRPHY_PIR jz_reg(DDRPHY_PIR) | ||
30 | #define JA_DDRPHY_PIR (0xb3011000 + 0x4) | ||
31 | #define JT_DDRPHY_PIR JIO_32_RW | ||
32 | #define JN_DDRPHY_PIR DDRPHY_PIR | ||
33 | #define JI_DDRPHY_PIR | ||
34 | |||
35 | #define REG_DDRPHY_PGCR jz_reg(DDRPHY_PGCR) | ||
36 | #define JA_DDRPHY_PGCR (0xb3011000 + 0x8) | ||
37 | #define JT_DDRPHY_PGCR JIO_32_RW | ||
38 | #define JN_DDRPHY_PGCR DDRPHY_PGCR | ||
39 | #define JI_DDRPHY_PGCR | ||
40 | |||
41 | #define REG_DDRPHY_PGSR jz_reg(DDRPHY_PGSR) | ||
42 | #define JA_DDRPHY_PGSR (0xb3011000 + 0xc) | ||
43 | #define JT_DDRPHY_PGSR JIO_32_RW | ||
44 | #define JN_DDRPHY_PGSR DDRPHY_PGSR | ||
45 | #define JI_DDRPHY_PGSR | ||
46 | |||
47 | #define REG_DDRPHY_DLLGCR jz_reg(DDRPHY_DLLGCR) | ||
48 | #define JA_DDRPHY_DLLGCR (0xb3011000 + 0x10) | ||
49 | #define JT_DDRPHY_DLLGCR JIO_32_RW | ||
50 | #define JN_DDRPHY_DLLGCR DDRPHY_DLLGCR | ||
51 | #define JI_DDRPHY_DLLGCR | ||
52 | |||
53 | #define REG_DDRPHY_ACDLLCR jz_reg(DDRPHY_ACDLLCR) | ||
54 | #define JA_DDRPHY_ACDLLCR (0xb3011000 + 0x14) | ||
55 | #define JT_DDRPHY_ACDLLCR JIO_32_RW | ||
56 | #define JN_DDRPHY_ACDLLCR DDRPHY_ACDLLCR | ||
57 | #define JI_DDRPHY_ACDLLCR | ||
58 | |||
59 | #define REG_DDRPHY_PTR0 jz_reg(DDRPHY_PTR0) | ||
60 | #define JA_DDRPHY_PTR0 (0xb3011000 + 0x18) | ||
61 | #define JT_DDRPHY_PTR0 JIO_32_RW | ||
62 | #define JN_DDRPHY_PTR0 DDRPHY_PTR0 | ||
63 | #define JI_DDRPHY_PTR0 | ||
64 | |||
65 | #define REG_DDRPHY_PTR1 jz_reg(DDRPHY_PTR1) | ||
66 | #define JA_DDRPHY_PTR1 (0xb3011000 + 0x1c) | ||
67 | #define JT_DDRPHY_PTR1 JIO_32_RW | ||
68 | #define JN_DDRPHY_PTR1 DDRPHY_PTR1 | ||
69 | #define JI_DDRPHY_PTR1 | ||
70 | |||
71 | #define REG_DDRPHY_PTR2 jz_reg(DDRPHY_PTR2) | ||
72 | #define JA_DDRPHY_PTR2 (0xb3011000 + 0x20) | ||
73 | #define JT_DDRPHY_PTR2 JIO_32_RW | ||
74 | #define JN_DDRPHY_PTR2 DDRPHY_PTR2 | ||
75 | #define JI_DDRPHY_PTR2 | ||
76 | |||
77 | #define REG_DDRPHY_ACIOCR jz_reg(DDRPHY_ACIOCR) | ||
78 | #define JA_DDRPHY_ACIOCR (0xb3011000 + 0x24) | ||
79 | #define JT_DDRPHY_ACIOCR JIO_32_RW | ||
80 | #define JN_DDRPHY_ACIOCR DDRPHY_ACIOCR | ||
81 | #define JI_DDRPHY_ACIOCR | ||
82 | |||
83 | #define REG_DDRPHY_DXCCR jz_reg(DDRPHY_DXCCR) | ||
84 | #define JA_DDRPHY_DXCCR (0xb3011000 + 0x28) | ||
85 | #define JT_DDRPHY_DXCCR JIO_32_RW | ||
86 | #define JN_DDRPHY_DXCCR DDRPHY_DXCCR | ||
87 | #define JI_DDRPHY_DXCCR | ||
88 | |||
89 | #define REG_DDRPHY_DSGCR jz_reg(DDRPHY_DSGCR) | ||
90 | #define JA_DDRPHY_DSGCR (0xb3011000 + 0x2c) | ||
91 | #define JT_DDRPHY_DSGCR JIO_32_RW | ||
92 | #define JN_DDRPHY_DSGCR DDRPHY_DSGCR | ||
93 | #define JI_DDRPHY_DSGCR | ||
94 | |||
95 | #define REG_DDRPHY_DCR jz_reg(DDRPHY_DCR) | ||
96 | #define JA_DDRPHY_DCR (0xb3011000 + 0x30) | ||
97 | #define JT_DDRPHY_DCR JIO_32_RW | ||
98 | #define JN_DDRPHY_DCR DDRPHY_DCR | ||
99 | #define JI_DDRPHY_DCR | ||
100 | |||
101 | #define REG_DDRPHY_DTPR0 jz_reg(DDRPHY_DTPR0) | ||
102 | #define JA_DDRPHY_DTPR0 (0xb3011000 + 0x34) | ||
103 | #define JT_DDRPHY_DTPR0 JIO_32_RW | ||
104 | #define JN_DDRPHY_DTPR0 DDRPHY_DTPR0 | ||
105 | #define JI_DDRPHY_DTPR0 | ||
106 | |||
107 | #define REG_DDRPHY_DTPR1 jz_reg(DDRPHY_DTPR1) | ||
108 | #define JA_DDRPHY_DTPR1 (0xb3011000 + 0x38) | ||
109 | #define JT_DDRPHY_DTPR1 JIO_32_RW | ||
110 | #define JN_DDRPHY_DTPR1 DDRPHY_DTPR1 | ||
111 | #define JI_DDRPHY_DTPR1 | ||
112 | |||
113 | #define REG_DDRPHY_DTPR2 jz_reg(DDRPHY_DTPR2) | ||
114 | #define JA_DDRPHY_DTPR2 (0xb3011000 + 0x3c) | ||
115 | #define JT_DDRPHY_DTPR2 JIO_32_RW | ||
116 | #define JN_DDRPHY_DTPR2 DDRPHY_DTPR2 | ||
117 | #define JI_DDRPHY_DTPR2 | ||
118 | |||
119 | #define REG_DDRPHY_MR0 jz_reg(DDRPHY_MR0) | ||
120 | #define JA_DDRPHY_MR0 (0xb3011000 + 0x40) | ||
121 | #define JT_DDRPHY_MR0 JIO_32_RW | ||
122 | #define JN_DDRPHY_MR0 DDRPHY_MR0 | ||
123 | #define JI_DDRPHY_MR0 | ||
124 | |||
125 | #define REG_DDRPHY_MR1 jz_reg(DDRPHY_MR1) | ||
126 | #define JA_DDRPHY_MR1 (0xb3011000 + 0x44) | ||
127 | #define JT_DDRPHY_MR1 JIO_32_RW | ||
128 | #define JN_DDRPHY_MR1 DDRPHY_MR1 | ||
129 | #define JI_DDRPHY_MR1 | ||
130 | |||
131 | #define REG_DDRPHY_MR2 jz_reg(DDRPHY_MR2) | ||
132 | #define JA_DDRPHY_MR2 (0xb3011000 + 0x48) | ||
133 | #define JT_DDRPHY_MR2 JIO_32_RW | ||
134 | #define JN_DDRPHY_MR2 DDRPHY_MR2 | ||
135 | #define JI_DDRPHY_MR2 | ||
136 | |||
137 | #define REG_DDRPHY_MR3 jz_reg(DDRPHY_MR3) | ||
138 | #define JA_DDRPHY_MR3 (0xb3011000 + 0x4c) | ||
139 | #define JT_DDRPHY_MR3 JIO_32_RW | ||
140 | #define JN_DDRPHY_MR3 DDRPHY_MR3 | ||
141 | #define JI_DDRPHY_MR3 | ||
142 | |||
143 | #define REG_DDRPHY_DTAR jz_reg(DDRPHY_DTAR) | ||
144 | #define JA_DDRPHY_DTAR (0xb3011000 + 0x54) | ||
145 | #define JT_DDRPHY_DTAR JIO_32_RW | ||
146 | #define JN_DDRPHY_DTAR DDRPHY_DTAR | ||
147 | #define JI_DDRPHY_DTAR | ||
148 | |||
149 | #define REG_DDRPHY_DXGCR(_n1) jz_reg(DDRPHY_DXGCR(_n1)) | ||
150 | #define JA_DDRPHY_DXGCR(_n1) (0xb3011000 + 0x1c0 + (_n1) * 0x40) | ||
151 | #define JT_DDRPHY_DXGCR(_n1) JIO_32_RW | ||
152 | #define JN_DDRPHY_DXGCR(_n1) DDRPHY_DXGCR | ||
153 | #define JI_DDRPHY_DXGCR(_n1) (_n1) | ||
154 | |||
155 | #endif /* __HEADERGEN_DDRPHY_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/dma.h b/firmware/target/mips/ingenic_x1000/x1000/dma.h new file mode 100644 index 0000000000..516c6e6849 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/dma.h | |||
@@ -0,0 +1,112 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_DMA_H__ | ||
25 | #define __HEADERGEN_DMA_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_DMA_CTRL jz_reg(DMA_CTRL) | ||
30 | #define JA_DMA_CTRL (0xb3421000 + 0x0) | ||
31 | #define JT_DMA_CTRL JIO_32_RW | ||
32 | #define JN_DMA_CTRL DMA_CTRL | ||
33 | #define JI_DMA_CTRL | ||
34 | #define BP_DMA_CTRL_FMSC 31 | ||
35 | #define BM_DMA_CTRL_FMSC 0x80000000 | ||
36 | #define BF_DMA_CTRL_FMSC(v) (((v) & 0x1) << 31) | ||
37 | #define BFM_DMA_CTRL_FMSC(v) BM_DMA_CTRL_FMSC | ||
38 | #define BF_DMA_CTRL_FMSC_V(e) BF_DMA_CTRL_FMSC(BV_DMA_CTRL_FMSC__##e) | ||
39 | #define BFM_DMA_CTRL_FMSC_V(v) BM_DMA_CTRL_FMSC | ||
40 | #define BP_DMA_CTRL_FSSI 30 | ||
41 | #define BM_DMA_CTRL_FSSI 0x40000000 | ||
42 | #define BF_DMA_CTRL_FSSI(v) (((v) & 0x1) << 30) | ||
43 | #define BFM_DMA_CTRL_FSSI(v) BM_DMA_CTRL_FSSI | ||
44 | #define BF_DMA_CTRL_FSSI_V(e) BF_DMA_CTRL_FSSI(BV_DMA_CTRL_FSSI__##e) | ||
45 | #define BFM_DMA_CTRL_FSSI_V(v) BM_DMA_CTRL_FSSI | ||
46 | #define BP_DMA_CTRL_FTSSI 29 | ||
47 | #define BM_DMA_CTRL_FTSSI 0x20000000 | ||
48 | #define BF_DMA_CTRL_FTSSI(v) (((v) & 0x1) << 29) | ||
49 | #define BFM_DMA_CTRL_FTSSI(v) BM_DMA_CTRL_FTSSI | ||
50 | #define BF_DMA_CTRL_FTSSI_V(e) BF_DMA_CTRL_FTSSI(BV_DMA_CTRL_FTSSI__##e) | ||
51 | #define BFM_DMA_CTRL_FTSSI_V(v) BM_DMA_CTRL_FTSSI | ||
52 | #define BP_DMA_CTRL_FUART 28 | ||
53 | #define BM_DMA_CTRL_FUART 0x10000000 | ||
54 | #define BF_DMA_CTRL_FUART(v) (((v) & 0x1) << 28) | ||
55 | #define BFM_DMA_CTRL_FUART(v) BM_DMA_CTRL_FUART | ||
56 | #define BF_DMA_CTRL_FUART_V(e) BF_DMA_CTRL_FUART(BV_DMA_CTRL_FUART__##e) | ||
57 | #define BFM_DMA_CTRL_FUART_V(v) BM_DMA_CTRL_FUART | ||
58 | #define BP_DMA_CTRL_FAIC 27 | ||
59 | #define BM_DMA_CTRL_FAIC 0x8000000 | ||
60 | #define BF_DMA_CTRL_FAIC(v) (((v) & 0x1) << 27) | ||
61 | #define BFM_DMA_CTRL_FAIC(v) BM_DMA_CTRL_FAIC | ||
62 | #define BF_DMA_CTRL_FAIC_V(e) BF_DMA_CTRL_FAIC(BV_DMA_CTRL_FAIC__##e) | ||
63 | #define BFM_DMA_CTRL_FAIC_V(v) BM_DMA_CTRL_FAIC | ||
64 | #define BP_DMA_CTRL_HALT 3 | ||
65 | #define BM_DMA_CTRL_HALT 0x8 | ||
66 | #define BF_DMA_CTRL_HALT(v) (((v) & 0x1) << 3) | ||
67 | #define BFM_DMA_CTRL_HALT(v) BM_DMA_CTRL_HALT | ||
68 | #define BF_DMA_CTRL_HALT_V(e) BF_DMA_CTRL_HALT(BV_DMA_CTRL_HALT__##e) | ||
69 | #define BFM_DMA_CTRL_HALT_V(v) BM_DMA_CTRL_HALT | ||
70 | #define BP_DMA_CTRL_AR 2 | ||
71 | #define BM_DMA_CTRL_AR 0x4 | ||
72 | #define BF_DMA_CTRL_AR(v) (((v) & 0x1) << 2) | ||
73 | #define BFM_DMA_CTRL_AR(v) BM_DMA_CTRL_AR | ||
74 | #define BF_DMA_CTRL_AR_V(e) BF_DMA_CTRL_AR(BV_DMA_CTRL_AR__##e) | ||
75 | #define BFM_DMA_CTRL_AR_V(v) BM_DMA_CTRL_AR | ||
76 | #define BP_DMA_CTRL_ENABLE 0 | ||
77 | #define BM_DMA_CTRL_ENABLE 0x1 | ||
78 | #define BF_DMA_CTRL_ENABLE(v) (((v) & 0x1) << 0) | ||
79 | #define BFM_DMA_CTRL_ENABLE(v) BM_DMA_CTRL_ENABLE | ||
80 | #define BF_DMA_CTRL_ENABLE_V(e) BF_DMA_CTRL_ENABLE(BV_DMA_CTRL_ENABLE__##e) | ||
81 | #define BFM_DMA_CTRL_ENABLE_V(v) BM_DMA_CTRL_ENABLE | ||
82 | |||
83 | #define REG_DMA_IRQP jz_reg(DMA_IRQP) | ||
84 | #define JA_DMA_IRQP (0xb3421000 + 0x4) | ||
85 | #define JT_DMA_IRQP JIO_32_RW | ||
86 | #define JN_DMA_IRQP DMA_IRQP | ||
87 | #define JI_DMA_IRQP | ||
88 | |||
89 | #define REG_DMA_DB jz_reg(DMA_DB) | ||
90 | #define JA_DMA_DB (0xb3421000 + 0x8) | ||
91 | #define JT_DMA_DB JIO_32_RW | ||
92 | #define JN_DMA_DB DMA_DB | ||
93 | #define JI_DMA_DB | ||
94 | #define REG_DMA_DB_SET jz_reg(DMA_DB_SET) | ||
95 | #define JA_DMA_DB_SET (JA_DMA_DB + 0x4) | ||
96 | #define JT_DMA_DB_SET JIO_32_WO | ||
97 | #define JN_DMA_DB_SET DMA_DB | ||
98 | #define JI_DMA_DB_SET | ||
99 | |||
100 | #define REG_DMA_DIP jz_reg(DMA_DIP) | ||
101 | #define JA_DMA_DIP (0xb3421000 + 0x10) | ||
102 | #define JT_DMA_DIP JIO_32_RW | ||
103 | #define JN_DMA_DIP DMA_DIP | ||
104 | #define JI_DMA_DIP | ||
105 | |||
106 | #define REG_DMA_DIC jz_reg(DMA_DIC) | ||
107 | #define JA_DMA_DIC (0xb3421000 + 0x14) | ||
108 | #define JT_DMA_DIC JIO_32_RW | ||
109 | #define JN_DMA_DIC DMA_DIC | ||
110 | #define JI_DMA_DIC | ||
111 | |||
112 | #endif /* __HEADERGEN_DMA_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/dma_chn.h b/firmware/target/mips/ingenic_x1000/x1000/dma_chn.h new file mode 100644 index 0000000000..56eb2a8cc1 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/dma_chn.h | |||
@@ -0,0 +1,253 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_DMA_CHN_H__ | ||
25 | #define __HEADERGEN_DMA_CHN_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_DMA_CHN_SA(_n1) jz_reg(DMA_CHN_SA(_n1)) | ||
30 | #define JA_DMA_CHN_SA(_n1) (0xb3420000 + (_n1) * 0x20 + 0x0) | ||
31 | #define JT_DMA_CHN_SA(_n1) JIO_32_RW | ||
32 | #define JN_DMA_CHN_SA(_n1) DMA_CHN_SA | ||
33 | #define JI_DMA_CHN_SA(_n1) (_n1) | ||
34 | |||
35 | #define REG_DMA_CHN_TA(_n1) jz_reg(DMA_CHN_TA(_n1)) | ||
36 | #define JA_DMA_CHN_TA(_n1) (0xb3420000 + (_n1) * 0x20 + 0x4) | ||
37 | #define JT_DMA_CHN_TA(_n1) JIO_32_RW | ||
38 | #define JN_DMA_CHN_TA(_n1) DMA_CHN_TA | ||
39 | #define JI_DMA_CHN_TA(_n1) (_n1) | ||
40 | |||
41 | #define REG_DMA_CHN_TC(_n1) jz_reg(DMA_CHN_TC(_n1)) | ||
42 | #define JA_DMA_CHN_TC(_n1) (0xb3420000 + (_n1) * 0x20 + 0x8) | ||
43 | #define JT_DMA_CHN_TC(_n1) JIO_32_RW | ||
44 | #define JN_DMA_CHN_TC(_n1) DMA_CHN_TC | ||
45 | #define JI_DMA_CHN_TC(_n1) (_n1) | ||
46 | #define BP_DMA_CHN_TC_DOA 24 | ||
47 | #define BM_DMA_CHN_TC_DOA 0xff000000 | ||
48 | #define BF_DMA_CHN_TC_DOA(v) (((v) & 0xff) << 24) | ||
49 | #define BFM_DMA_CHN_TC_DOA(v) BM_DMA_CHN_TC_DOA | ||
50 | #define BF_DMA_CHN_TC_DOA_V(e) BF_DMA_CHN_TC_DOA(BV_DMA_CHN_TC_DOA__##e) | ||
51 | #define BFM_DMA_CHN_TC_DOA_V(v) BM_DMA_CHN_TC_DOA | ||
52 | #define BP_DMA_CHN_TC_CNT 0 | ||
53 | #define BM_DMA_CHN_TC_CNT 0xffffff | ||
54 | #define BF_DMA_CHN_TC_CNT(v) (((v) & 0xffffff) << 0) | ||
55 | #define BFM_DMA_CHN_TC_CNT(v) BM_DMA_CHN_TC_CNT | ||
56 | #define BF_DMA_CHN_TC_CNT_V(e) BF_DMA_CHN_TC_CNT(BV_DMA_CHN_TC_CNT__##e) | ||
57 | #define BFM_DMA_CHN_TC_CNT_V(v) BM_DMA_CHN_TC_CNT | ||
58 | |||
59 | #define REG_DMA_CHN_RT(_n1) jz_reg(DMA_CHN_RT(_n1)) | ||
60 | #define JA_DMA_CHN_RT(_n1) (0xb3420000 + (_n1) * 0x20 + 0xc) | ||
61 | #define JT_DMA_CHN_RT(_n1) JIO_32_RW | ||
62 | #define JN_DMA_CHN_RT(_n1) DMA_CHN_RT | ||
63 | #define JI_DMA_CHN_RT(_n1) (_n1) | ||
64 | #define BP_DMA_CHN_RT_TYPE 0 | ||
65 | #define BM_DMA_CHN_RT_TYPE 0x3f | ||
66 | #define BV_DMA_CHN_RT_TYPE__DMIC_RX 0x5 | ||
67 | #define BV_DMA_CHN_RT_TYPE__I2S_TX 0x6 | ||
68 | #define BV_DMA_CHN_RT_TYPE__I2S_RX 0x7 | ||
69 | #define BV_DMA_CHN_RT_TYPE__AUTO 0x8 | ||
70 | #define BV_DMA_CHN_RT_TYPE__UART2_TX 0x10 | ||
71 | #define BV_DMA_CHN_RT_TYPE__UART2_RX 0x11 | ||
72 | #define BV_DMA_CHN_RT_TYPE__UART1_TX 0x12 | ||
73 | #define BV_DMA_CHN_RT_TYPE__UART1_RX 0x13 | ||
74 | #define BV_DMA_CHN_RT_TYPE__UART0_TX 0x14 | ||
75 | #define BV_DMA_CHN_RT_TYPE__UART0_RX 0x15 | ||
76 | #define BV_DMA_CHN_RT_TYPE__SSI_TX 0x16 | ||
77 | #define BV_DMA_CHN_RT_TYPE__SSI_RX 0x17 | ||
78 | #define BV_DMA_CHN_RT_TYPE__MSC0_TX 0x1a | ||
79 | #define BV_DMA_CHN_RT_TYPE__MSC0_RX 0x1b | ||
80 | #define BV_DMA_CHN_RT_TYPE__MSC1_TX 0x1c | ||
81 | #define BV_DMA_CHN_RT_TYPE__MSC1_RX 0x1d | ||
82 | #define BV_DMA_CHN_RT_TYPE__PCM_TX 0x20 | ||
83 | #define BV_DMA_CHN_RT_TYPE__PCM_RX 0x21 | ||
84 | #define BV_DMA_CHN_RT_TYPE__I2C0_TX 0x24 | ||
85 | #define BV_DMA_CHN_RT_TYPE__I2C0_RX 0x25 | ||
86 | #define BV_DMA_CHN_RT_TYPE__I2C1_TX 0x26 | ||
87 | #define BV_DMA_CHN_RT_TYPE__I2C1_RX 0x27 | ||
88 | #define BV_DMA_CHN_RT_TYPE__I2C2_TX 0x28 | ||
89 | #define BV_DMA_CHN_RT_TYPE__I2C2_RX 0x29 | ||
90 | #define BF_DMA_CHN_RT_TYPE(v) (((v) & 0x3f) << 0) | ||
91 | #define BFM_DMA_CHN_RT_TYPE(v) BM_DMA_CHN_RT_TYPE | ||
92 | #define BF_DMA_CHN_RT_TYPE_V(e) BF_DMA_CHN_RT_TYPE(BV_DMA_CHN_RT_TYPE__##e) | ||
93 | #define BFM_DMA_CHN_RT_TYPE_V(v) BM_DMA_CHN_RT_TYPE | ||
94 | |||
95 | #define REG_DMA_CHN_CS(_n1) jz_reg(DMA_CHN_CS(_n1)) | ||
96 | #define JA_DMA_CHN_CS(_n1) (0xb3420000 + (_n1) * 0x20 + 0x10) | ||
97 | #define JT_DMA_CHN_CS(_n1) JIO_32_RW | ||
98 | #define JN_DMA_CHN_CS(_n1) DMA_CHN_CS | ||
99 | #define JI_DMA_CHN_CS(_n1) (_n1) | ||
100 | #define BP_DMA_CHN_CS_CDOA 8 | ||
101 | #define BM_DMA_CHN_CS_CDOA 0xff00 | ||
102 | #define BF_DMA_CHN_CS_CDOA(v) (((v) & 0xff) << 8) | ||
103 | #define BFM_DMA_CHN_CS_CDOA(v) BM_DMA_CHN_CS_CDOA | ||
104 | #define BF_DMA_CHN_CS_CDOA_V(e) BF_DMA_CHN_CS_CDOA(BV_DMA_CHN_CS_CDOA__##e) | ||
105 | #define BFM_DMA_CHN_CS_CDOA_V(v) BM_DMA_CHN_CS_CDOA | ||
106 | #define BP_DMA_CHN_CS_NDES 31 | ||
107 | #define BM_DMA_CHN_CS_NDES 0x80000000 | ||
108 | #define BF_DMA_CHN_CS_NDES(v) (((v) & 0x1) << 31) | ||
109 | #define BFM_DMA_CHN_CS_NDES(v) BM_DMA_CHN_CS_NDES | ||
110 | #define BF_DMA_CHN_CS_NDES_V(e) BF_DMA_CHN_CS_NDES(BV_DMA_CHN_CS_NDES__##e) | ||
111 | #define BFM_DMA_CHN_CS_NDES_V(v) BM_DMA_CHN_CS_NDES | ||
112 | #define BP_DMA_CHN_CS_DES8 30 | ||
113 | #define BM_DMA_CHN_CS_DES8 0x40000000 | ||
114 | #define BF_DMA_CHN_CS_DES8(v) (((v) & 0x1) << 30) | ||
115 | #define BFM_DMA_CHN_CS_DES8(v) BM_DMA_CHN_CS_DES8 | ||
116 | #define BF_DMA_CHN_CS_DES8_V(e) BF_DMA_CHN_CS_DES8(BV_DMA_CHN_CS_DES8__##e) | ||
117 | #define BFM_DMA_CHN_CS_DES8_V(v) BM_DMA_CHN_CS_DES8 | ||
118 | #define BP_DMA_CHN_CS_AR 4 | ||
119 | #define BM_DMA_CHN_CS_AR 0x10 | ||
120 | #define BF_DMA_CHN_CS_AR(v) (((v) & 0x1) << 4) | ||
121 | #define BFM_DMA_CHN_CS_AR(v) BM_DMA_CHN_CS_AR | ||
122 | #define BF_DMA_CHN_CS_AR_V(e) BF_DMA_CHN_CS_AR(BV_DMA_CHN_CS_AR__##e) | ||
123 | #define BFM_DMA_CHN_CS_AR_V(v) BM_DMA_CHN_CS_AR | ||
124 | #define BP_DMA_CHN_CS_TT 3 | ||
125 | #define BM_DMA_CHN_CS_TT 0x8 | ||
126 | #define BF_DMA_CHN_CS_TT(v) (((v) & 0x1) << 3) | ||
127 | #define BFM_DMA_CHN_CS_TT(v) BM_DMA_CHN_CS_TT | ||
128 | #define BF_DMA_CHN_CS_TT_V(e) BF_DMA_CHN_CS_TT(BV_DMA_CHN_CS_TT__##e) | ||
129 | #define BFM_DMA_CHN_CS_TT_V(v) BM_DMA_CHN_CS_TT | ||
130 | #define BP_DMA_CHN_CS_HLT 2 | ||
131 | #define BM_DMA_CHN_CS_HLT 0x4 | ||
132 | #define BF_DMA_CHN_CS_HLT(v) (((v) & 0x1) << 2) | ||
133 | #define BFM_DMA_CHN_CS_HLT(v) BM_DMA_CHN_CS_HLT | ||
134 | #define BF_DMA_CHN_CS_HLT_V(e) BF_DMA_CHN_CS_HLT(BV_DMA_CHN_CS_HLT__##e) | ||
135 | #define BFM_DMA_CHN_CS_HLT_V(v) BM_DMA_CHN_CS_HLT | ||
136 | #define BP_DMA_CHN_CS_CTE 0 | ||
137 | #define BM_DMA_CHN_CS_CTE 0x1 | ||
138 | #define BF_DMA_CHN_CS_CTE(v) (((v) & 0x1) << 0) | ||
139 | #define BFM_DMA_CHN_CS_CTE(v) BM_DMA_CHN_CS_CTE | ||
140 | #define BF_DMA_CHN_CS_CTE_V(e) BF_DMA_CHN_CS_CTE(BV_DMA_CHN_CS_CTE__##e) | ||
141 | #define BFM_DMA_CHN_CS_CTE_V(v) BM_DMA_CHN_CS_CTE | ||
142 | |||
143 | #define REG_DMA_CHN_CM(_n1) jz_reg(DMA_CHN_CM(_n1)) | ||
144 | #define JA_DMA_CHN_CM(_n1) (0xb3420000 + (_n1) * 0x20 + 0x14) | ||
145 | #define JT_DMA_CHN_CM(_n1) JIO_32_RW | ||
146 | #define JN_DMA_CHN_CM(_n1) DMA_CHN_CM | ||
147 | #define JI_DMA_CHN_CM(_n1) (_n1) | ||
148 | #define BP_DMA_CHN_CM_RDIL 16 | ||
149 | #define BM_DMA_CHN_CM_RDIL 0xf0000 | ||
150 | #define BF_DMA_CHN_CM_RDIL(v) (((v) & 0xf) << 16) | ||
151 | #define BFM_DMA_CHN_CM_RDIL(v) BM_DMA_CHN_CM_RDIL | ||
152 | #define BF_DMA_CHN_CM_RDIL_V(e) BF_DMA_CHN_CM_RDIL(BV_DMA_CHN_CM_RDIL__##e) | ||
153 | #define BFM_DMA_CHN_CM_RDIL_V(v) BM_DMA_CHN_CM_RDIL | ||
154 | #define BP_DMA_CHN_CM_SP 14 | ||
155 | #define BM_DMA_CHN_CM_SP 0xc000 | ||
156 | #define BV_DMA_CHN_CM_SP__32BIT 0x0 | ||
157 | #define BV_DMA_CHN_CM_SP__8BIT 0x1 | ||
158 | #define BV_DMA_CHN_CM_SP__16BIT 0x2 | ||
159 | #define BF_DMA_CHN_CM_SP(v) (((v) & 0x3) << 14) | ||
160 | #define BFM_DMA_CHN_CM_SP(v) BM_DMA_CHN_CM_SP | ||
161 | #define BF_DMA_CHN_CM_SP_V(e) BF_DMA_CHN_CM_SP(BV_DMA_CHN_CM_SP__##e) | ||
162 | #define BFM_DMA_CHN_CM_SP_V(v) BM_DMA_CHN_CM_SP | ||
163 | #define BP_DMA_CHN_CM_DP 12 | ||
164 | #define BM_DMA_CHN_CM_DP 0x3000 | ||
165 | #define BV_DMA_CHN_CM_DP__32BIT 0x0 | ||
166 | #define BV_DMA_CHN_CM_DP__8BIT 0x1 | ||
167 | #define BV_DMA_CHN_CM_DP__16BIT 0x2 | ||
168 | #define BF_DMA_CHN_CM_DP(v) (((v) & 0x3) << 12) | ||
169 | #define BFM_DMA_CHN_CM_DP(v) BM_DMA_CHN_CM_DP | ||
170 | #define BF_DMA_CHN_CM_DP_V(e) BF_DMA_CHN_CM_DP(BV_DMA_CHN_CM_DP__##e) | ||
171 | #define BFM_DMA_CHN_CM_DP_V(v) BM_DMA_CHN_CM_DP | ||
172 | #define BP_DMA_CHN_CM_TSZ 8 | ||
173 | #define BM_DMA_CHN_CM_TSZ 0x700 | ||
174 | #define BV_DMA_CHN_CM_TSZ__32BIT 0x0 | ||
175 | #define BV_DMA_CHN_CM_TSZ__8BIT 0x1 | ||
176 | #define BV_DMA_CHN_CM_TSZ__16BIT 0x2 | ||
177 | #define BV_DMA_CHN_CM_TSZ__16BYTE 0x3 | ||
178 | #define BV_DMA_CHN_CM_TSZ__32BYTE 0x4 | ||
179 | #define BV_DMA_CHN_CM_TSZ__64BYTE 0x5 | ||
180 | #define BV_DMA_CHN_CM_TSZ__128BYTE 0x6 | ||
181 | #define BV_DMA_CHN_CM_TSZ__AUTO 0x7 | ||
182 | #define BF_DMA_CHN_CM_TSZ(v) (((v) & 0x7) << 8) | ||
183 | #define BFM_DMA_CHN_CM_TSZ(v) BM_DMA_CHN_CM_TSZ | ||
184 | #define BF_DMA_CHN_CM_TSZ_V(e) BF_DMA_CHN_CM_TSZ(BV_DMA_CHN_CM_TSZ__##e) | ||
185 | #define BFM_DMA_CHN_CM_TSZ_V(v) BM_DMA_CHN_CM_TSZ | ||
186 | #define BP_DMA_CHN_CM_SAI 23 | ||
187 | #define BM_DMA_CHN_CM_SAI 0x800000 | ||
188 | #define BF_DMA_CHN_CM_SAI(v) (((v) & 0x1) << 23) | ||
189 | #define BFM_DMA_CHN_CM_SAI(v) BM_DMA_CHN_CM_SAI | ||
190 | #define BF_DMA_CHN_CM_SAI_V(e) BF_DMA_CHN_CM_SAI(BV_DMA_CHN_CM_SAI__##e) | ||
191 | #define BFM_DMA_CHN_CM_SAI_V(v) BM_DMA_CHN_CM_SAI | ||
192 | #define BP_DMA_CHN_CM_DAI 22 | ||
193 | #define BM_DMA_CHN_CM_DAI 0x400000 | ||
194 | #define BF_DMA_CHN_CM_DAI(v) (((v) & 0x1) << 22) | ||
195 | #define BFM_DMA_CHN_CM_DAI(v) BM_DMA_CHN_CM_DAI | ||
196 | #define BF_DMA_CHN_CM_DAI_V(e) BF_DMA_CHN_CM_DAI(BV_DMA_CHN_CM_DAI__##e) | ||
197 | #define BFM_DMA_CHN_CM_DAI_V(v) BM_DMA_CHN_CM_DAI | ||
198 | #define BP_DMA_CHN_CM_STDE 2 | ||
199 | #define BM_DMA_CHN_CM_STDE 0x4 | ||
200 | #define BF_DMA_CHN_CM_STDE(v) (((v) & 0x1) << 2) | ||
201 | #define BFM_DMA_CHN_CM_STDE(v) BM_DMA_CHN_CM_STDE | ||
202 | #define BF_DMA_CHN_CM_STDE_V(e) BF_DMA_CHN_CM_STDE(BV_DMA_CHN_CM_STDE__##e) | ||
203 | #define BFM_DMA_CHN_CM_STDE_V(v) BM_DMA_CHN_CM_STDE | ||
204 | #define BP_DMA_CHN_CM_TIE 1 | ||
205 | #define BM_DMA_CHN_CM_TIE 0x2 | ||
206 | #define BF_DMA_CHN_CM_TIE(v) (((v) & 0x1) << 1) | ||
207 | #define BFM_DMA_CHN_CM_TIE(v) BM_DMA_CHN_CM_TIE | ||
208 | #define BF_DMA_CHN_CM_TIE_V(e) BF_DMA_CHN_CM_TIE(BV_DMA_CHN_CM_TIE__##e) | ||
209 | #define BFM_DMA_CHN_CM_TIE_V(v) BM_DMA_CHN_CM_TIE | ||
210 | #define BP_DMA_CHN_CM_LINK 0 | ||
211 | #define BM_DMA_CHN_CM_LINK 0x1 | ||
212 | #define BF_DMA_CHN_CM_LINK(v) (((v) & 0x1) << 0) | ||
213 | #define BFM_DMA_CHN_CM_LINK(v) BM_DMA_CHN_CM_LINK | ||
214 | #define BF_DMA_CHN_CM_LINK_V(e) BF_DMA_CHN_CM_LINK(BV_DMA_CHN_CM_LINK__##e) | ||
215 | #define BFM_DMA_CHN_CM_LINK_V(v) BM_DMA_CHN_CM_LINK | ||
216 | |||
217 | #define REG_DMA_CHN_DA(_n1) jz_reg(DMA_CHN_DA(_n1)) | ||
218 | #define JA_DMA_CHN_DA(_n1) (0xb3420000 + (_n1) * 0x20 + 0x18) | ||
219 | #define JT_DMA_CHN_DA(_n1) JIO_32_RW | ||
220 | #define JN_DMA_CHN_DA(_n1) DMA_CHN_DA | ||
221 | #define JI_DMA_CHN_DA(_n1) (_n1) | ||
222 | #define BP_DMA_CHN_DA_DBA 12 | ||
223 | #define BM_DMA_CHN_DA_DBA 0xfffff000 | ||
224 | #define BF_DMA_CHN_DA_DBA(v) (((v) & 0xfffff) << 12) | ||
225 | #define BFM_DMA_CHN_DA_DBA(v) BM_DMA_CHN_DA_DBA | ||
226 | #define BF_DMA_CHN_DA_DBA_V(e) BF_DMA_CHN_DA_DBA(BV_DMA_CHN_DA_DBA__##e) | ||
227 | #define BFM_DMA_CHN_DA_DBA_V(v) BM_DMA_CHN_DA_DBA | ||
228 | #define BP_DMA_CHN_DA_DOA 4 | ||
229 | #define BM_DMA_CHN_DA_DOA 0xff0 | ||
230 | #define BF_DMA_CHN_DA_DOA(v) (((v) & 0xff) << 4) | ||
231 | #define BFM_DMA_CHN_DA_DOA(v) BM_DMA_CHN_DA_DOA | ||
232 | #define BF_DMA_CHN_DA_DOA_V(e) BF_DMA_CHN_DA_DOA(BV_DMA_CHN_DA_DOA__##e) | ||
233 | #define BFM_DMA_CHN_DA_DOA_V(v) BM_DMA_CHN_DA_DOA | ||
234 | |||
235 | #define REG_DMA_CHN_SD(_n1) jz_reg(DMA_CHN_SD(_n1)) | ||
236 | #define JA_DMA_CHN_SD(_n1) (0xb3420000 + (_n1) * 0x20 + 0x1c) | ||
237 | #define JT_DMA_CHN_SD(_n1) JIO_32_RW | ||
238 | #define JN_DMA_CHN_SD(_n1) DMA_CHN_SD | ||
239 | #define JI_DMA_CHN_SD(_n1) (_n1) | ||
240 | #define BP_DMA_CHN_SD_TSD 16 | ||
241 | #define BM_DMA_CHN_SD_TSD 0xffff0000 | ||
242 | #define BF_DMA_CHN_SD_TSD(v) (((v) & 0xffff) << 16) | ||
243 | #define BFM_DMA_CHN_SD_TSD(v) BM_DMA_CHN_SD_TSD | ||
244 | #define BF_DMA_CHN_SD_TSD_V(e) BF_DMA_CHN_SD_TSD(BV_DMA_CHN_SD_TSD__##e) | ||
245 | #define BFM_DMA_CHN_SD_TSD_V(v) BM_DMA_CHN_SD_TSD | ||
246 | #define BP_DMA_CHN_SD_SSD 0 | ||
247 | #define BM_DMA_CHN_SD_SSD 0xffff | ||
248 | #define BF_DMA_CHN_SD_SSD(v) (((v) & 0xffff) << 0) | ||
249 | #define BFM_DMA_CHN_SD_SSD(v) BM_DMA_CHN_SD_SSD | ||
250 | #define BF_DMA_CHN_SD_SSD_V(e) BF_DMA_CHN_SD_SSD(BV_DMA_CHN_SD_SSD__##e) | ||
251 | #define BFM_DMA_CHN_SD_SSD_V(v) BM_DMA_CHN_SD_SSD | ||
252 | |||
253 | #endif /* __HEADERGEN_DMA_CHN_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/gpio.h b/firmware/target/mips/ingenic_x1000/x1000/gpio.h new file mode 100644 index 0000000000..6bba343cf6 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/gpio.h | |||
@@ -0,0 +1,196 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_GPIO_H__ | ||
25 | #define __HEADERGEN_GPIO_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_GPIO_C_GLITCH_CFG0 jz_reg(GPIO_C_GLITCH_CFG0) | ||
30 | #define JA_GPIO_C_GLITCH_CFG0 (0xb0010000 + 0x200 + 0x800) | ||
31 | #define JT_GPIO_C_GLITCH_CFG0 JIO_32_RW | ||
32 | #define JN_GPIO_C_GLITCH_CFG0 GPIO_C_GLITCH_CFG0 | ||
33 | #define JI_GPIO_C_GLITCH_CFG0 | ||
34 | #define REG_GPIO_C_GLITCH_CFG0_SET jz_reg(GPIO_C_GLITCH_CFG0_SET) | ||
35 | #define JA_GPIO_C_GLITCH_CFG0_SET (JA_GPIO_C_GLITCH_CFG0 + 0x4) | ||
36 | #define JT_GPIO_C_GLITCH_CFG0_SET JIO_32_WO | ||
37 | #define JN_GPIO_C_GLITCH_CFG0_SET GPIO_C_GLITCH_CFG0 | ||
38 | #define JI_GPIO_C_GLITCH_CFG0_SET | ||
39 | #define REG_GPIO_C_GLITCH_CFG0_CLR jz_reg(GPIO_C_GLITCH_CFG0_CLR) | ||
40 | #define JA_GPIO_C_GLITCH_CFG0_CLR (JA_GPIO_C_GLITCH_CFG0 + 0x8) | ||
41 | #define JT_GPIO_C_GLITCH_CFG0_CLR JIO_32_WO | ||
42 | #define JN_GPIO_C_GLITCH_CFG0_CLR GPIO_C_GLITCH_CFG0 | ||
43 | #define JI_GPIO_C_GLITCH_CFG0_CLR | ||
44 | |||
45 | #define REG_GPIO_C_GLITCH_CFG1 jz_reg(GPIO_C_GLITCH_CFG1) | ||
46 | #define JA_GPIO_C_GLITCH_CFG1 (0xb0010000 + 0x200 + 0x810) | ||
47 | #define JT_GPIO_C_GLITCH_CFG1 JIO_32_RW | ||
48 | #define JN_GPIO_C_GLITCH_CFG1 GPIO_C_GLITCH_CFG1 | ||
49 | #define JI_GPIO_C_GLITCH_CFG1 | ||
50 | #define REG_GPIO_C_GLITCH_CFG1_SET jz_reg(GPIO_C_GLITCH_CFG1_SET) | ||
51 | #define JA_GPIO_C_GLITCH_CFG1_SET (JA_GPIO_C_GLITCH_CFG1 + 0x4) | ||
52 | #define JT_GPIO_C_GLITCH_CFG1_SET JIO_32_WO | ||
53 | #define JN_GPIO_C_GLITCH_CFG1_SET GPIO_C_GLITCH_CFG1 | ||
54 | #define JI_GPIO_C_GLITCH_CFG1_SET | ||
55 | #define REG_GPIO_C_GLITCH_CFG1_CLR jz_reg(GPIO_C_GLITCH_CFG1_CLR) | ||
56 | #define JA_GPIO_C_GLITCH_CFG1_CLR (JA_GPIO_C_GLITCH_CFG1 + 0x8) | ||
57 | #define JT_GPIO_C_GLITCH_CFG1_CLR JIO_32_WO | ||
58 | #define JN_GPIO_C_GLITCH_CFG1_CLR GPIO_C_GLITCH_CFG1 | ||
59 | #define JI_GPIO_C_GLITCH_CFG1_CLR | ||
60 | |||
61 | #define REG_GPIO_C_GLITCH_CFG2 jz_reg(GPIO_C_GLITCH_CFG2) | ||
62 | #define JA_GPIO_C_GLITCH_CFG2 (0xb0010000 + 0x200 + 0x820) | ||
63 | #define JT_GPIO_C_GLITCH_CFG2 JIO_32_RW | ||
64 | #define JN_GPIO_C_GLITCH_CFG2 GPIO_C_GLITCH_CFG2 | ||
65 | #define JI_GPIO_C_GLITCH_CFG2 | ||
66 | #define REG_GPIO_C_GLITCH_CFG2_SET jz_reg(GPIO_C_GLITCH_CFG2_SET) | ||
67 | #define JA_GPIO_C_GLITCH_CFG2_SET (JA_GPIO_C_GLITCH_CFG2 + 0x4) | ||
68 | #define JT_GPIO_C_GLITCH_CFG2_SET JIO_32_WO | ||
69 | #define JN_GPIO_C_GLITCH_CFG2_SET GPIO_C_GLITCH_CFG2 | ||
70 | #define JI_GPIO_C_GLITCH_CFG2_SET | ||
71 | #define REG_GPIO_C_GLITCH_CFG2_CLR jz_reg(GPIO_C_GLITCH_CFG2_CLR) | ||
72 | #define JA_GPIO_C_GLITCH_CFG2_CLR (JA_GPIO_C_GLITCH_CFG2 + 0x8) | ||
73 | #define JT_GPIO_C_GLITCH_CFG2_CLR JIO_32_WO | ||
74 | #define JN_GPIO_C_GLITCH_CFG2_CLR GPIO_C_GLITCH_CFG2 | ||
75 | #define JI_GPIO_C_GLITCH_CFG2_CLR | ||
76 | |||
77 | #define REG_GPIO_C_GLITCH_CFG3 jz_reg(GPIO_C_GLITCH_CFG3) | ||
78 | #define JA_GPIO_C_GLITCH_CFG3 (0xb0010000 + 0x200 + 0x830) | ||
79 | #define JT_GPIO_C_GLITCH_CFG3 JIO_32_RW | ||
80 | #define JN_GPIO_C_GLITCH_CFG3 GPIO_C_GLITCH_CFG3 | ||
81 | #define JI_GPIO_C_GLITCH_CFG3 | ||
82 | #define REG_GPIO_C_GLITCH_CFG3_SET jz_reg(GPIO_C_GLITCH_CFG3_SET) | ||
83 | #define JA_GPIO_C_GLITCH_CFG3_SET (JA_GPIO_C_GLITCH_CFG3 + 0x4) | ||
84 | #define JT_GPIO_C_GLITCH_CFG3_SET JIO_32_WO | ||
85 | #define JN_GPIO_C_GLITCH_CFG3_SET GPIO_C_GLITCH_CFG3 | ||
86 | #define JI_GPIO_C_GLITCH_CFG3_SET | ||
87 | #define REG_GPIO_C_GLITCH_CFG3_CLR jz_reg(GPIO_C_GLITCH_CFG3_CLR) | ||
88 | #define JA_GPIO_C_GLITCH_CFG3_CLR (JA_GPIO_C_GLITCH_CFG3 + 0x8) | ||
89 | #define JT_GPIO_C_GLITCH_CFG3_CLR JIO_32_WO | ||
90 | #define JN_GPIO_C_GLITCH_CFG3_CLR GPIO_C_GLITCH_CFG3 | ||
91 | #define JI_GPIO_C_GLITCH_CFG3_CLR | ||
92 | |||
93 | #define REG_GPIO_PIN(_n1) jz_reg(GPIO_PIN(_n1)) | ||
94 | #define JA_GPIO_PIN(_n1) (0xb0010000 + 0x0 + (_n1) * 0x100) | ||
95 | #define JT_GPIO_PIN(_n1) JIO_32_RW | ||
96 | #define JN_GPIO_PIN(_n1) GPIO_PIN | ||
97 | #define JI_GPIO_PIN(_n1) (_n1) | ||
98 | |||
99 | #define REG_GPIO_INT(_n1) jz_reg(GPIO_INT(_n1)) | ||
100 | #define JA_GPIO_INT(_n1) (0xb0010000 + 0x10 + (_n1) * 0x100) | ||
101 | #define JT_GPIO_INT(_n1) JIO_32_RW | ||
102 | #define JN_GPIO_INT(_n1) GPIO_INT | ||
103 | #define JI_GPIO_INT(_n1) (_n1) | ||
104 | #define REG_GPIO_INT_SET(_n1) jz_reg(GPIO_INT_SET(_n1)) | ||
105 | #define JA_GPIO_INT_SET(_n1) (JA_GPIO_INT(_n1) + 0x4) | ||
106 | #define JT_GPIO_INT_SET(_n1) JIO_32_WO | ||
107 | #define JN_GPIO_INT_SET(_n1) GPIO_INT | ||
108 | #define JI_GPIO_INT_SET(_n1) (_n1) | ||
109 | #define REG_GPIO_INT_CLR(_n1) jz_reg(GPIO_INT_CLR(_n1)) | ||
110 | #define JA_GPIO_INT_CLR(_n1) (JA_GPIO_INT(_n1) + 0x8) | ||
111 | #define JT_GPIO_INT_CLR(_n1) JIO_32_WO | ||
112 | #define JN_GPIO_INT_CLR(_n1) GPIO_INT | ||
113 | #define JI_GPIO_INT_CLR(_n1) (_n1) | ||
114 | |||
115 | #define REG_GPIO_MSK(_n1) jz_reg(GPIO_MSK(_n1)) | ||
116 | #define JA_GPIO_MSK(_n1) (0xb0010000 + 0x20 + (_n1) * 0x100) | ||
117 | #define JT_GPIO_MSK(_n1) JIO_32_RW | ||
118 | #define JN_GPIO_MSK(_n1) GPIO_MSK | ||
119 | #define JI_GPIO_MSK(_n1) (_n1) | ||
120 | #define REG_GPIO_MSK_SET(_n1) jz_reg(GPIO_MSK_SET(_n1)) | ||
121 | #define JA_GPIO_MSK_SET(_n1) (JA_GPIO_MSK(_n1) + 0x4) | ||
122 | #define JT_GPIO_MSK_SET(_n1) JIO_32_WO | ||
123 | #define JN_GPIO_MSK_SET(_n1) GPIO_MSK | ||
124 | #define JI_GPIO_MSK_SET(_n1) (_n1) | ||
125 | #define REG_GPIO_MSK_CLR(_n1) jz_reg(GPIO_MSK_CLR(_n1)) | ||
126 | #define JA_GPIO_MSK_CLR(_n1) (JA_GPIO_MSK(_n1) + 0x8) | ||
127 | #define JT_GPIO_MSK_CLR(_n1) JIO_32_WO | ||
128 | #define JN_GPIO_MSK_CLR(_n1) GPIO_MSK | ||
129 | #define JI_GPIO_MSK_CLR(_n1) (_n1) | ||
130 | |||
131 | #define REG_GPIO_PAT1(_n1) jz_reg(GPIO_PAT1(_n1)) | ||
132 | #define JA_GPIO_PAT1(_n1) (0xb0010000 + 0x30 + (_n1) * 0x100) | ||
133 | #define JT_GPIO_PAT1(_n1) JIO_32_RW | ||
134 | #define JN_GPIO_PAT1(_n1) GPIO_PAT1 | ||
135 | #define JI_GPIO_PAT1(_n1) (_n1) | ||
136 | #define REG_GPIO_PAT1_SET(_n1) jz_reg(GPIO_PAT1_SET(_n1)) | ||
137 | #define JA_GPIO_PAT1_SET(_n1) (JA_GPIO_PAT1(_n1) + 0x4) | ||
138 | #define JT_GPIO_PAT1_SET(_n1) JIO_32_WO | ||
139 | #define JN_GPIO_PAT1_SET(_n1) GPIO_PAT1 | ||
140 | #define JI_GPIO_PAT1_SET(_n1) (_n1) | ||
141 | #define REG_GPIO_PAT1_CLR(_n1) jz_reg(GPIO_PAT1_CLR(_n1)) | ||
142 | #define JA_GPIO_PAT1_CLR(_n1) (JA_GPIO_PAT1(_n1) + 0x8) | ||
143 | #define JT_GPIO_PAT1_CLR(_n1) JIO_32_WO | ||
144 | #define JN_GPIO_PAT1_CLR(_n1) GPIO_PAT1 | ||
145 | #define JI_GPIO_PAT1_CLR(_n1) (_n1) | ||
146 | |||
147 | #define REG_GPIO_PAT0(_n1) jz_reg(GPIO_PAT0(_n1)) | ||
148 | #define JA_GPIO_PAT0(_n1) (0xb0010000 + 0x40 + (_n1) * 0x100) | ||
149 | #define JT_GPIO_PAT0(_n1) JIO_32_RW | ||
150 | #define JN_GPIO_PAT0(_n1) GPIO_PAT0 | ||
151 | #define JI_GPIO_PAT0(_n1) (_n1) | ||
152 | #define REG_GPIO_PAT0_SET(_n1) jz_reg(GPIO_PAT0_SET(_n1)) | ||
153 | #define JA_GPIO_PAT0_SET(_n1) (JA_GPIO_PAT0(_n1) + 0x4) | ||
154 | #define JT_GPIO_PAT0_SET(_n1) JIO_32_WO | ||
155 | #define JN_GPIO_PAT0_SET(_n1) GPIO_PAT0 | ||
156 | #define JI_GPIO_PAT0_SET(_n1) (_n1) | ||
157 | #define REG_GPIO_PAT0_CLR(_n1) jz_reg(GPIO_PAT0_CLR(_n1)) | ||
158 | #define JA_GPIO_PAT0_CLR(_n1) (JA_GPIO_PAT0(_n1) + 0x8) | ||
159 | #define JT_GPIO_PAT0_CLR(_n1) JIO_32_WO | ||
160 | #define JN_GPIO_PAT0_CLR(_n1) GPIO_PAT0 | ||
161 | #define JI_GPIO_PAT0_CLR(_n1) (_n1) | ||
162 | |||
163 | #define REG_GPIO_FLAG(_n1) jz_reg(GPIO_FLAG(_n1)) | ||
164 | #define JA_GPIO_FLAG(_n1) (0xb0010000 + 0x50 + (_n1) * 0x100) | ||
165 | #define JT_GPIO_FLAG(_n1) JIO_32_RW | ||
166 | #define JN_GPIO_FLAG(_n1) GPIO_FLAG | ||
167 | #define JI_GPIO_FLAG(_n1) (_n1) | ||
168 | #define REG_GPIO_FLAG_CLR(_n1) jz_reg(GPIO_FLAG_CLR(_n1)) | ||
169 | #define JA_GPIO_FLAG_CLR(_n1) (JA_GPIO_FLAG(_n1) + 0x8) | ||
170 | #define JT_GPIO_FLAG_CLR(_n1) JIO_32_WO | ||
171 | #define JN_GPIO_FLAG_CLR(_n1) GPIO_FLAG | ||
172 | #define JI_GPIO_FLAG_CLR(_n1) (_n1) | ||
173 | |||
174 | #define REG_GPIO_PULL(_n1) jz_reg(GPIO_PULL(_n1)) | ||
175 | #define JA_GPIO_PULL(_n1) (0xb0010000 + 0x70 + (_n1) * 0x100) | ||
176 | #define JT_GPIO_PULL(_n1) JIO_32_RW | ||
177 | #define JN_GPIO_PULL(_n1) GPIO_PULL | ||
178 | #define JI_GPIO_PULL(_n1) (_n1) | ||
179 | #define REG_GPIO_PULL_SET(_n1) jz_reg(GPIO_PULL_SET(_n1)) | ||
180 | #define JA_GPIO_PULL_SET(_n1) (JA_GPIO_PULL(_n1) + 0x4) | ||
181 | #define JT_GPIO_PULL_SET(_n1) JIO_32_WO | ||
182 | #define JN_GPIO_PULL_SET(_n1) GPIO_PULL | ||
183 | #define JI_GPIO_PULL_SET(_n1) (_n1) | ||
184 | #define REG_GPIO_PULL_CLR(_n1) jz_reg(GPIO_PULL_CLR(_n1)) | ||
185 | #define JA_GPIO_PULL_CLR(_n1) (JA_GPIO_PULL(_n1) + 0x8) | ||
186 | #define JT_GPIO_PULL_CLR(_n1) JIO_32_WO | ||
187 | #define JN_GPIO_PULL_CLR(_n1) GPIO_PULL | ||
188 | #define JI_GPIO_PULL_CLR(_n1) (_n1) | ||
189 | |||
190 | #define REG_GPIO_Z_GID2LD jz_reg(GPIO_Z_GID2LD) | ||
191 | #define JA_GPIO_Z_GID2LD (0xb0010000 + 0x7f0) | ||
192 | #define JT_GPIO_Z_GID2LD JIO_32_RW | ||
193 | #define JN_GPIO_Z_GID2LD GPIO_Z_GID2LD | ||
194 | #define JI_GPIO_Z_GID2LD | ||
195 | |||
196 | #endif /* __HEADERGEN_GPIO_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/i2c.h b/firmware/target/mips/ingenic_x1000/x1000/i2c.h new file mode 100644 index 0000000000..29f24bf82e --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/i2c.h | |||
@@ -0,0 +1,625 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_I2C_H__ | ||
25 | #define __HEADERGEN_I2C_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_I2C_CON(_n1) jz_reg(I2C_CON(_n1)) | ||
30 | #define JA_I2C_CON(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x0) | ||
31 | #define JT_I2C_CON(_n1) JIO_32_RW | ||
32 | #define JN_I2C_CON(_n1) I2C_CON | ||
33 | #define JI_I2C_CON(_n1) (_n1) | ||
34 | #define BP_I2C_CON_SPEED 1 | ||
35 | #define BM_I2C_CON_SPEED 0x6 | ||
36 | #define BV_I2C_CON_SPEED__100K 0x1 | ||
37 | #define BV_I2C_CON_SPEED__400K 0x2 | ||
38 | #define BF_I2C_CON_SPEED(v) (((v) & 0x3) << 1) | ||
39 | #define BFM_I2C_CON_SPEED(v) BM_I2C_CON_SPEED | ||
40 | #define BF_I2C_CON_SPEED_V(e) BF_I2C_CON_SPEED(BV_I2C_CON_SPEED__##e) | ||
41 | #define BFM_I2C_CON_SPEED_V(v) BM_I2C_CON_SPEED | ||
42 | #define BP_I2C_CON_SLVDIS 6 | ||
43 | #define BM_I2C_CON_SLVDIS 0x40 | ||
44 | #define BF_I2C_CON_SLVDIS(v) (((v) & 0x1) << 6) | ||
45 | #define BFM_I2C_CON_SLVDIS(v) BM_I2C_CON_SLVDIS | ||
46 | #define BF_I2C_CON_SLVDIS_V(e) BF_I2C_CON_SLVDIS(BV_I2C_CON_SLVDIS__##e) | ||
47 | #define BFM_I2C_CON_SLVDIS_V(v) BM_I2C_CON_SLVDIS | ||
48 | #define BP_I2C_CON_RESTART 5 | ||
49 | #define BM_I2C_CON_RESTART 0x20 | ||
50 | #define BF_I2C_CON_RESTART(v) (((v) & 0x1) << 5) | ||
51 | #define BFM_I2C_CON_RESTART(v) BM_I2C_CON_RESTART | ||
52 | #define BF_I2C_CON_RESTART_V(e) BF_I2C_CON_RESTART(BV_I2C_CON_RESTART__##e) | ||
53 | #define BFM_I2C_CON_RESTART_V(v) BM_I2C_CON_RESTART | ||
54 | #define BP_I2C_CON_MATP 4 | ||
55 | #define BM_I2C_CON_MATP 0x10 | ||
56 | #define BF_I2C_CON_MATP(v) (((v) & 0x1) << 4) | ||
57 | #define BFM_I2C_CON_MATP(v) BM_I2C_CON_MATP | ||
58 | #define BF_I2C_CON_MATP_V(e) BF_I2C_CON_MATP(BV_I2C_CON_MATP__##e) | ||
59 | #define BFM_I2C_CON_MATP_V(v) BM_I2C_CON_MATP | ||
60 | #define BP_I2C_CON_SATP 3 | ||
61 | #define BM_I2C_CON_SATP 0x8 | ||
62 | #define BF_I2C_CON_SATP(v) (((v) & 0x1) << 3) | ||
63 | #define BFM_I2C_CON_SATP(v) BM_I2C_CON_SATP | ||
64 | #define BF_I2C_CON_SATP_V(e) BF_I2C_CON_SATP(BV_I2C_CON_SATP__##e) | ||
65 | #define BFM_I2C_CON_SATP_V(v) BM_I2C_CON_SATP | ||
66 | #define BP_I2C_CON_MD 0 | ||
67 | #define BM_I2C_CON_MD 0x1 | ||
68 | #define BF_I2C_CON_MD(v) (((v) & 0x1) << 0) | ||
69 | #define BFM_I2C_CON_MD(v) BM_I2C_CON_MD | ||
70 | #define BF_I2C_CON_MD_V(e) BF_I2C_CON_MD(BV_I2C_CON_MD__##e) | ||
71 | #define BFM_I2C_CON_MD_V(v) BM_I2C_CON_MD | ||
72 | |||
73 | #define REG_I2C_DC(_n1) jz_reg(I2C_DC(_n1)) | ||
74 | #define JA_I2C_DC(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x10) | ||
75 | #define JT_I2C_DC(_n1) JIO_32_RW | ||
76 | #define JN_I2C_DC(_n1) I2C_DC | ||
77 | #define JI_I2C_DC(_n1) (_n1) | ||
78 | #define BP_I2C_DC_DAT 0 | ||
79 | #define BM_I2C_DC_DAT 0xff | ||
80 | #define BF_I2C_DC_DAT(v) (((v) & 0xff) << 0) | ||
81 | #define BFM_I2C_DC_DAT(v) BM_I2C_DC_DAT | ||
82 | #define BF_I2C_DC_DAT_V(e) BF_I2C_DC_DAT(BV_I2C_DC_DAT__##e) | ||
83 | #define BFM_I2C_DC_DAT_V(v) BM_I2C_DC_DAT | ||
84 | #define BP_I2C_DC_RESTART 10 | ||
85 | #define BM_I2C_DC_RESTART 0x400 | ||
86 | #define BF_I2C_DC_RESTART(v) (((v) & 0x1) << 10) | ||
87 | #define BFM_I2C_DC_RESTART(v) BM_I2C_DC_RESTART | ||
88 | #define BF_I2C_DC_RESTART_V(e) BF_I2C_DC_RESTART(BV_I2C_DC_RESTART__##e) | ||
89 | #define BFM_I2C_DC_RESTART_V(v) BM_I2C_DC_RESTART | ||
90 | #define BP_I2C_DC_STOP 9 | ||
91 | #define BM_I2C_DC_STOP 0x200 | ||
92 | #define BF_I2C_DC_STOP(v) (((v) & 0x1) << 9) | ||
93 | #define BFM_I2C_DC_STOP(v) BM_I2C_DC_STOP | ||
94 | #define BF_I2C_DC_STOP_V(e) BF_I2C_DC_STOP(BV_I2C_DC_STOP__##e) | ||
95 | #define BFM_I2C_DC_STOP_V(v) BM_I2C_DC_STOP | ||
96 | #define BP_I2C_DC_CMD 8 | ||
97 | #define BM_I2C_DC_CMD 0x100 | ||
98 | #define BF_I2C_DC_CMD(v) (((v) & 0x1) << 8) | ||
99 | #define BFM_I2C_DC_CMD(v) BM_I2C_DC_CMD | ||
100 | #define BF_I2C_DC_CMD_V(e) BF_I2C_DC_CMD(BV_I2C_DC_CMD__##e) | ||
101 | #define BFM_I2C_DC_CMD_V(v) BM_I2C_DC_CMD | ||
102 | |||
103 | #define REG_I2C_INTST(_n1) jz_reg(I2C_INTST(_n1)) | ||
104 | #define JA_I2C_INTST(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x2c) | ||
105 | #define JT_I2C_INTST(_n1) JIO_32_RW | ||
106 | #define JN_I2C_INTST(_n1) I2C_INTST | ||
107 | #define JI_I2C_INTST(_n1) (_n1) | ||
108 | #define BP_I2C_INTST_GC 11 | ||
109 | #define BM_I2C_INTST_GC 0x800 | ||
110 | #define BF_I2C_INTST_GC(v) (((v) & 0x1) << 11) | ||
111 | #define BFM_I2C_INTST_GC(v) BM_I2C_INTST_GC | ||
112 | #define BF_I2C_INTST_GC_V(e) BF_I2C_INTST_GC(BV_I2C_INTST_GC__##e) | ||
113 | #define BFM_I2C_INTST_GC_V(v) BM_I2C_INTST_GC | ||
114 | #define BP_I2C_INTST_STT 10 | ||
115 | #define BM_I2C_INTST_STT 0x400 | ||
116 | #define BF_I2C_INTST_STT(v) (((v) & 0x1) << 10) | ||
117 | #define BFM_I2C_INTST_STT(v) BM_I2C_INTST_STT | ||
118 | #define BF_I2C_INTST_STT_V(e) BF_I2C_INTST_STT(BV_I2C_INTST_STT__##e) | ||
119 | #define BFM_I2C_INTST_STT_V(v) BM_I2C_INTST_STT | ||
120 | #define BP_I2C_INTST_STP 9 | ||
121 | #define BM_I2C_INTST_STP 0x200 | ||
122 | #define BF_I2C_INTST_STP(v) (((v) & 0x1) << 9) | ||
123 | #define BFM_I2C_INTST_STP(v) BM_I2C_INTST_STP | ||
124 | #define BF_I2C_INTST_STP_V(e) BF_I2C_INTST_STP(BV_I2C_INTST_STP__##e) | ||
125 | #define BFM_I2C_INTST_STP_V(v) BM_I2C_INTST_STP | ||
126 | #define BP_I2C_INTST_ACT 8 | ||
127 | #define BM_I2C_INTST_ACT 0x100 | ||
128 | #define BF_I2C_INTST_ACT(v) (((v) & 0x1) << 8) | ||
129 | #define BFM_I2C_INTST_ACT(v) BM_I2C_INTST_ACT | ||
130 | #define BF_I2C_INTST_ACT_V(e) BF_I2C_INTST_ACT(BV_I2C_INTST_ACT__##e) | ||
131 | #define BFM_I2C_INTST_ACT_V(v) BM_I2C_INTST_ACT | ||
132 | #define BP_I2C_INTST_RXDN 7 | ||
133 | #define BM_I2C_INTST_RXDN 0x80 | ||
134 | #define BF_I2C_INTST_RXDN(v) (((v) & 0x1) << 7) | ||
135 | #define BFM_I2C_INTST_RXDN(v) BM_I2C_INTST_RXDN | ||
136 | #define BF_I2C_INTST_RXDN_V(e) BF_I2C_INTST_RXDN(BV_I2C_INTST_RXDN__##e) | ||
137 | #define BFM_I2C_INTST_RXDN_V(v) BM_I2C_INTST_RXDN | ||
138 | #define BP_I2C_INTST_TXABT 6 | ||
139 | #define BM_I2C_INTST_TXABT 0x40 | ||
140 | #define BF_I2C_INTST_TXABT(v) (((v) & 0x1) << 6) | ||
141 | #define BFM_I2C_INTST_TXABT(v) BM_I2C_INTST_TXABT | ||
142 | #define BF_I2C_INTST_TXABT_V(e) BF_I2C_INTST_TXABT(BV_I2C_INTST_TXABT__##e) | ||
143 | #define BFM_I2C_INTST_TXABT_V(v) BM_I2C_INTST_TXABT | ||
144 | #define BP_I2C_INTST_RDREQ 5 | ||
145 | #define BM_I2C_INTST_RDREQ 0x20 | ||
146 | #define BF_I2C_INTST_RDREQ(v) (((v) & 0x1) << 5) | ||
147 | #define BFM_I2C_INTST_RDREQ(v) BM_I2C_INTST_RDREQ | ||
148 | #define BF_I2C_INTST_RDREQ_V(e) BF_I2C_INTST_RDREQ(BV_I2C_INTST_RDREQ__##e) | ||
149 | #define BFM_I2C_INTST_RDREQ_V(v) BM_I2C_INTST_RDREQ | ||
150 | #define BP_I2C_INTST_TXEMP 4 | ||
151 | #define BM_I2C_INTST_TXEMP 0x10 | ||
152 | #define BF_I2C_INTST_TXEMP(v) (((v) & 0x1) << 4) | ||
153 | #define BFM_I2C_INTST_TXEMP(v) BM_I2C_INTST_TXEMP | ||
154 | #define BF_I2C_INTST_TXEMP_V(e) BF_I2C_INTST_TXEMP(BV_I2C_INTST_TXEMP__##e) | ||
155 | #define BFM_I2C_INTST_TXEMP_V(v) BM_I2C_INTST_TXEMP | ||
156 | #define BP_I2C_INTST_TXOF 3 | ||
157 | #define BM_I2C_INTST_TXOF 0x8 | ||
158 | #define BF_I2C_INTST_TXOF(v) (((v) & 0x1) << 3) | ||
159 | #define BFM_I2C_INTST_TXOF(v) BM_I2C_INTST_TXOF | ||
160 | #define BF_I2C_INTST_TXOF_V(e) BF_I2C_INTST_TXOF(BV_I2C_INTST_TXOF__##e) | ||
161 | #define BFM_I2C_INTST_TXOF_V(v) BM_I2C_INTST_TXOF | ||
162 | #define BP_I2C_INTST_RXFL 2 | ||
163 | #define BM_I2C_INTST_RXFL 0x4 | ||
164 | #define BF_I2C_INTST_RXFL(v) (((v) & 0x1) << 2) | ||
165 | #define BFM_I2C_INTST_RXFL(v) BM_I2C_INTST_RXFL | ||
166 | #define BF_I2C_INTST_RXFL_V(e) BF_I2C_INTST_RXFL(BV_I2C_INTST_RXFL__##e) | ||
167 | #define BFM_I2C_INTST_RXFL_V(v) BM_I2C_INTST_RXFL | ||
168 | #define BP_I2C_INTST_RXOF 1 | ||
169 | #define BM_I2C_INTST_RXOF 0x2 | ||
170 | #define BF_I2C_INTST_RXOF(v) (((v) & 0x1) << 1) | ||
171 | #define BFM_I2C_INTST_RXOF(v) BM_I2C_INTST_RXOF | ||
172 | #define BF_I2C_INTST_RXOF_V(e) BF_I2C_INTST_RXOF(BV_I2C_INTST_RXOF__##e) | ||
173 | #define BFM_I2C_INTST_RXOF_V(v) BM_I2C_INTST_RXOF | ||
174 | #define BP_I2C_INTST_RXUF 0 | ||
175 | #define BM_I2C_INTST_RXUF 0x1 | ||
176 | #define BF_I2C_INTST_RXUF(v) (((v) & 0x1) << 0) | ||
177 | #define BFM_I2C_INTST_RXUF(v) BM_I2C_INTST_RXUF | ||
178 | #define BF_I2C_INTST_RXUF_V(e) BF_I2C_INTST_RXUF(BV_I2C_INTST_RXUF__##e) | ||
179 | #define BFM_I2C_INTST_RXUF_V(v) BM_I2C_INTST_RXUF | ||
180 | |||
181 | #define REG_I2C_INTMSK(_n1) jz_reg(I2C_INTMSK(_n1)) | ||
182 | #define JA_I2C_INTMSK(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x30) | ||
183 | #define JT_I2C_INTMSK(_n1) JIO_32_RW | ||
184 | #define JN_I2C_INTMSK(_n1) I2C_INTMSK | ||
185 | #define JI_I2C_INTMSK(_n1) (_n1) | ||
186 | #define BP_I2C_INTMSK_GC 11 | ||
187 | #define BM_I2C_INTMSK_GC 0x800 | ||
188 | #define BF_I2C_INTMSK_GC(v) (((v) & 0x1) << 11) | ||
189 | #define BFM_I2C_INTMSK_GC(v) BM_I2C_INTMSK_GC | ||
190 | #define BF_I2C_INTMSK_GC_V(e) BF_I2C_INTMSK_GC(BV_I2C_INTMSK_GC__##e) | ||
191 | #define BFM_I2C_INTMSK_GC_V(v) BM_I2C_INTMSK_GC | ||
192 | #define BP_I2C_INTMSK_STT 10 | ||
193 | #define BM_I2C_INTMSK_STT 0x400 | ||
194 | #define BF_I2C_INTMSK_STT(v) (((v) & 0x1) << 10) | ||
195 | #define BFM_I2C_INTMSK_STT(v) BM_I2C_INTMSK_STT | ||
196 | #define BF_I2C_INTMSK_STT_V(e) BF_I2C_INTMSK_STT(BV_I2C_INTMSK_STT__##e) | ||
197 | #define BFM_I2C_INTMSK_STT_V(v) BM_I2C_INTMSK_STT | ||
198 | #define BP_I2C_INTMSK_STP 9 | ||
199 | #define BM_I2C_INTMSK_STP 0x200 | ||
200 | #define BF_I2C_INTMSK_STP(v) (((v) & 0x1) << 9) | ||
201 | #define BFM_I2C_INTMSK_STP(v) BM_I2C_INTMSK_STP | ||
202 | #define BF_I2C_INTMSK_STP_V(e) BF_I2C_INTMSK_STP(BV_I2C_INTMSK_STP__##e) | ||
203 | #define BFM_I2C_INTMSK_STP_V(v) BM_I2C_INTMSK_STP | ||
204 | #define BP_I2C_INTMSK_ACT 8 | ||
205 | #define BM_I2C_INTMSK_ACT 0x100 | ||
206 | #define BF_I2C_INTMSK_ACT(v) (((v) & 0x1) << 8) | ||
207 | #define BFM_I2C_INTMSK_ACT(v) BM_I2C_INTMSK_ACT | ||
208 | #define BF_I2C_INTMSK_ACT_V(e) BF_I2C_INTMSK_ACT(BV_I2C_INTMSK_ACT__##e) | ||
209 | #define BFM_I2C_INTMSK_ACT_V(v) BM_I2C_INTMSK_ACT | ||
210 | #define BP_I2C_INTMSK_RXDN 7 | ||
211 | #define BM_I2C_INTMSK_RXDN 0x80 | ||
212 | #define BF_I2C_INTMSK_RXDN(v) (((v) & 0x1) << 7) | ||
213 | #define BFM_I2C_INTMSK_RXDN(v) BM_I2C_INTMSK_RXDN | ||
214 | #define BF_I2C_INTMSK_RXDN_V(e) BF_I2C_INTMSK_RXDN(BV_I2C_INTMSK_RXDN__##e) | ||
215 | #define BFM_I2C_INTMSK_RXDN_V(v) BM_I2C_INTMSK_RXDN | ||
216 | #define BP_I2C_INTMSK_TXABT 6 | ||
217 | #define BM_I2C_INTMSK_TXABT 0x40 | ||
218 | #define BF_I2C_INTMSK_TXABT(v) (((v) & 0x1) << 6) | ||
219 | #define BFM_I2C_INTMSK_TXABT(v) BM_I2C_INTMSK_TXABT | ||
220 | #define BF_I2C_INTMSK_TXABT_V(e) BF_I2C_INTMSK_TXABT(BV_I2C_INTMSK_TXABT__##e) | ||
221 | #define BFM_I2C_INTMSK_TXABT_V(v) BM_I2C_INTMSK_TXABT | ||
222 | #define BP_I2C_INTMSK_RDREQ 5 | ||
223 | #define BM_I2C_INTMSK_RDREQ 0x20 | ||
224 | #define BF_I2C_INTMSK_RDREQ(v) (((v) & 0x1) << 5) | ||
225 | #define BFM_I2C_INTMSK_RDREQ(v) BM_I2C_INTMSK_RDREQ | ||
226 | #define BF_I2C_INTMSK_RDREQ_V(e) BF_I2C_INTMSK_RDREQ(BV_I2C_INTMSK_RDREQ__##e) | ||
227 | #define BFM_I2C_INTMSK_RDREQ_V(v) BM_I2C_INTMSK_RDREQ | ||
228 | #define BP_I2C_INTMSK_TXEMP 4 | ||
229 | #define BM_I2C_INTMSK_TXEMP 0x10 | ||
230 | #define BF_I2C_INTMSK_TXEMP(v) (((v) & 0x1) << 4) | ||
231 | #define BFM_I2C_INTMSK_TXEMP(v) BM_I2C_INTMSK_TXEMP | ||
232 | #define BF_I2C_INTMSK_TXEMP_V(e) BF_I2C_INTMSK_TXEMP(BV_I2C_INTMSK_TXEMP__##e) | ||
233 | #define BFM_I2C_INTMSK_TXEMP_V(v) BM_I2C_INTMSK_TXEMP | ||
234 | #define BP_I2C_INTMSK_TXOF 3 | ||
235 | #define BM_I2C_INTMSK_TXOF 0x8 | ||
236 | #define BF_I2C_INTMSK_TXOF(v) (((v) & 0x1) << 3) | ||
237 | #define BFM_I2C_INTMSK_TXOF(v) BM_I2C_INTMSK_TXOF | ||
238 | #define BF_I2C_INTMSK_TXOF_V(e) BF_I2C_INTMSK_TXOF(BV_I2C_INTMSK_TXOF__##e) | ||
239 | #define BFM_I2C_INTMSK_TXOF_V(v) BM_I2C_INTMSK_TXOF | ||
240 | #define BP_I2C_INTMSK_RXFL 2 | ||
241 | #define BM_I2C_INTMSK_RXFL 0x4 | ||
242 | #define BF_I2C_INTMSK_RXFL(v) (((v) & 0x1) << 2) | ||
243 | #define BFM_I2C_INTMSK_RXFL(v) BM_I2C_INTMSK_RXFL | ||
244 | #define BF_I2C_INTMSK_RXFL_V(e) BF_I2C_INTMSK_RXFL(BV_I2C_INTMSK_RXFL__##e) | ||
245 | #define BFM_I2C_INTMSK_RXFL_V(v) BM_I2C_INTMSK_RXFL | ||
246 | #define BP_I2C_INTMSK_RXOF 1 | ||
247 | #define BM_I2C_INTMSK_RXOF 0x2 | ||
248 | #define BF_I2C_INTMSK_RXOF(v) (((v) & 0x1) << 1) | ||
249 | #define BFM_I2C_INTMSK_RXOF(v) BM_I2C_INTMSK_RXOF | ||
250 | #define BF_I2C_INTMSK_RXOF_V(e) BF_I2C_INTMSK_RXOF(BV_I2C_INTMSK_RXOF__##e) | ||
251 | #define BFM_I2C_INTMSK_RXOF_V(v) BM_I2C_INTMSK_RXOF | ||
252 | #define BP_I2C_INTMSK_RXUF 0 | ||
253 | #define BM_I2C_INTMSK_RXUF 0x1 | ||
254 | #define BF_I2C_INTMSK_RXUF(v) (((v) & 0x1) << 0) | ||
255 | #define BFM_I2C_INTMSK_RXUF(v) BM_I2C_INTMSK_RXUF | ||
256 | #define BF_I2C_INTMSK_RXUF_V(e) BF_I2C_INTMSK_RXUF(BV_I2C_INTMSK_RXUF__##e) | ||
257 | #define BFM_I2C_INTMSK_RXUF_V(v) BM_I2C_INTMSK_RXUF | ||
258 | |||
259 | #define REG_I2C_RINTST(_n1) jz_reg(I2C_RINTST(_n1)) | ||
260 | #define JA_I2C_RINTST(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x34) | ||
261 | #define JT_I2C_RINTST(_n1) JIO_32_RW | ||
262 | #define JN_I2C_RINTST(_n1) I2C_RINTST | ||
263 | #define JI_I2C_RINTST(_n1) (_n1) | ||
264 | #define BP_I2C_RINTST_GC 11 | ||
265 | #define BM_I2C_RINTST_GC 0x800 | ||
266 | #define BF_I2C_RINTST_GC(v) (((v) & 0x1) << 11) | ||
267 | #define BFM_I2C_RINTST_GC(v) BM_I2C_RINTST_GC | ||
268 | #define BF_I2C_RINTST_GC_V(e) BF_I2C_RINTST_GC(BV_I2C_RINTST_GC__##e) | ||
269 | #define BFM_I2C_RINTST_GC_V(v) BM_I2C_RINTST_GC | ||
270 | #define BP_I2C_RINTST_STT 10 | ||
271 | #define BM_I2C_RINTST_STT 0x400 | ||
272 | #define BF_I2C_RINTST_STT(v) (((v) & 0x1) << 10) | ||
273 | #define BFM_I2C_RINTST_STT(v) BM_I2C_RINTST_STT | ||
274 | #define BF_I2C_RINTST_STT_V(e) BF_I2C_RINTST_STT(BV_I2C_RINTST_STT__##e) | ||
275 | #define BFM_I2C_RINTST_STT_V(v) BM_I2C_RINTST_STT | ||
276 | #define BP_I2C_RINTST_STP 9 | ||
277 | #define BM_I2C_RINTST_STP 0x200 | ||
278 | #define BF_I2C_RINTST_STP(v) (((v) & 0x1) << 9) | ||
279 | #define BFM_I2C_RINTST_STP(v) BM_I2C_RINTST_STP | ||
280 | #define BF_I2C_RINTST_STP_V(e) BF_I2C_RINTST_STP(BV_I2C_RINTST_STP__##e) | ||
281 | #define BFM_I2C_RINTST_STP_V(v) BM_I2C_RINTST_STP | ||
282 | #define BP_I2C_RINTST_ACT 8 | ||
283 | #define BM_I2C_RINTST_ACT 0x100 | ||
284 | #define BF_I2C_RINTST_ACT(v) (((v) & 0x1) << 8) | ||
285 | #define BFM_I2C_RINTST_ACT(v) BM_I2C_RINTST_ACT | ||
286 | #define BF_I2C_RINTST_ACT_V(e) BF_I2C_RINTST_ACT(BV_I2C_RINTST_ACT__##e) | ||
287 | #define BFM_I2C_RINTST_ACT_V(v) BM_I2C_RINTST_ACT | ||
288 | #define BP_I2C_RINTST_RXDN 7 | ||
289 | #define BM_I2C_RINTST_RXDN 0x80 | ||
290 | #define BF_I2C_RINTST_RXDN(v) (((v) & 0x1) << 7) | ||
291 | #define BFM_I2C_RINTST_RXDN(v) BM_I2C_RINTST_RXDN | ||
292 | #define BF_I2C_RINTST_RXDN_V(e) BF_I2C_RINTST_RXDN(BV_I2C_RINTST_RXDN__##e) | ||
293 | #define BFM_I2C_RINTST_RXDN_V(v) BM_I2C_RINTST_RXDN | ||
294 | #define BP_I2C_RINTST_TXABT 6 | ||
295 | #define BM_I2C_RINTST_TXABT 0x40 | ||
296 | #define BF_I2C_RINTST_TXABT(v) (((v) & 0x1) << 6) | ||
297 | #define BFM_I2C_RINTST_TXABT(v) BM_I2C_RINTST_TXABT | ||
298 | #define BF_I2C_RINTST_TXABT_V(e) BF_I2C_RINTST_TXABT(BV_I2C_RINTST_TXABT__##e) | ||
299 | #define BFM_I2C_RINTST_TXABT_V(v) BM_I2C_RINTST_TXABT | ||
300 | #define BP_I2C_RINTST_RDREQ 5 | ||
301 | #define BM_I2C_RINTST_RDREQ 0x20 | ||
302 | #define BF_I2C_RINTST_RDREQ(v) (((v) & 0x1) << 5) | ||
303 | #define BFM_I2C_RINTST_RDREQ(v) BM_I2C_RINTST_RDREQ | ||
304 | #define BF_I2C_RINTST_RDREQ_V(e) BF_I2C_RINTST_RDREQ(BV_I2C_RINTST_RDREQ__##e) | ||
305 | #define BFM_I2C_RINTST_RDREQ_V(v) BM_I2C_RINTST_RDREQ | ||
306 | #define BP_I2C_RINTST_TXEMP 4 | ||
307 | #define BM_I2C_RINTST_TXEMP 0x10 | ||
308 | #define BF_I2C_RINTST_TXEMP(v) (((v) & 0x1) << 4) | ||
309 | #define BFM_I2C_RINTST_TXEMP(v) BM_I2C_RINTST_TXEMP | ||
310 | #define BF_I2C_RINTST_TXEMP_V(e) BF_I2C_RINTST_TXEMP(BV_I2C_RINTST_TXEMP__##e) | ||
311 | #define BFM_I2C_RINTST_TXEMP_V(v) BM_I2C_RINTST_TXEMP | ||
312 | #define BP_I2C_RINTST_TXOF 3 | ||
313 | #define BM_I2C_RINTST_TXOF 0x8 | ||
314 | #define BF_I2C_RINTST_TXOF(v) (((v) & 0x1) << 3) | ||
315 | #define BFM_I2C_RINTST_TXOF(v) BM_I2C_RINTST_TXOF | ||
316 | #define BF_I2C_RINTST_TXOF_V(e) BF_I2C_RINTST_TXOF(BV_I2C_RINTST_TXOF__##e) | ||
317 | #define BFM_I2C_RINTST_TXOF_V(v) BM_I2C_RINTST_TXOF | ||
318 | #define BP_I2C_RINTST_RXFL 2 | ||
319 | #define BM_I2C_RINTST_RXFL 0x4 | ||
320 | #define BF_I2C_RINTST_RXFL(v) (((v) & 0x1) << 2) | ||
321 | #define BFM_I2C_RINTST_RXFL(v) BM_I2C_RINTST_RXFL | ||
322 | #define BF_I2C_RINTST_RXFL_V(e) BF_I2C_RINTST_RXFL(BV_I2C_RINTST_RXFL__##e) | ||
323 | #define BFM_I2C_RINTST_RXFL_V(v) BM_I2C_RINTST_RXFL | ||
324 | #define BP_I2C_RINTST_RXOF 1 | ||
325 | #define BM_I2C_RINTST_RXOF 0x2 | ||
326 | #define BF_I2C_RINTST_RXOF(v) (((v) & 0x1) << 1) | ||
327 | #define BFM_I2C_RINTST_RXOF(v) BM_I2C_RINTST_RXOF | ||
328 | #define BF_I2C_RINTST_RXOF_V(e) BF_I2C_RINTST_RXOF(BV_I2C_RINTST_RXOF__##e) | ||
329 | #define BFM_I2C_RINTST_RXOF_V(v) BM_I2C_RINTST_RXOF | ||
330 | #define BP_I2C_RINTST_RXUF 0 | ||
331 | #define BM_I2C_RINTST_RXUF 0x1 | ||
332 | #define BF_I2C_RINTST_RXUF(v) (((v) & 0x1) << 0) | ||
333 | #define BFM_I2C_RINTST_RXUF(v) BM_I2C_RINTST_RXUF | ||
334 | #define BF_I2C_RINTST_RXUF_V(e) BF_I2C_RINTST_RXUF(BV_I2C_RINTST_RXUF__##e) | ||
335 | #define BFM_I2C_RINTST_RXUF_V(v) BM_I2C_RINTST_RXUF | ||
336 | |||
337 | #define REG_I2C_ENABLE(_n1) jz_reg(I2C_ENABLE(_n1)) | ||
338 | #define JA_I2C_ENABLE(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x6c) | ||
339 | #define JT_I2C_ENABLE(_n1) JIO_32_RW | ||
340 | #define JN_I2C_ENABLE(_n1) I2C_ENABLE | ||
341 | #define JI_I2C_ENABLE(_n1) (_n1) | ||
342 | #define BP_I2C_ENABLE_ABORT 1 | ||
343 | #define BM_I2C_ENABLE_ABORT 0x2 | ||
344 | #define BF_I2C_ENABLE_ABORT(v) (((v) & 0x1) << 1) | ||
345 | #define BFM_I2C_ENABLE_ABORT(v) BM_I2C_ENABLE_ABORT | ||
346 | #define BF_I2C_ENABLE_ABORT_V(e) BF_I2C_ENABLE_ABORT(BV_I2C_ENABLE_ABORT__##e) | ||
347 | #define BFM_I2C_ENABLE_ABORT_V(v) BM_I2C_ENABLE_ABORT | ||
348 | #define BP_I2C_ENABLE_ACTIVE 0 | ||
349 | #define BM_I2C_ENABLE_ACTIVE 0x1 | ||
350 | #define BF_I2C_ENABLE_ACTIVE(v) (((v) & 0x1) << 0) | ||
351 | #define BFM_I2C_ENABLE_ACTIVE(v) BM_I2C_ENABLE_ACTIVE | ||
352 | #define BF_I2C_ENABLE_ACTIVE_V(e) BF_I2C_ENABLE_ACTIVE(BV_I2C_ENABLE_ACTIVE__##e) | ||
353 | #define BFM_I2C_ENABLE_ACTIVE_V(v) BM_I2C_ENABLE_ACTIVE | ||
354 | |||
355 | #define REG_I2C_STATUS(_n1) jz_reg(I2C_STATUS(_n1)) | ||
356 | #define JA_I2C_STATUS(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x70) | ||
357 | #define JT_I2C_STATUS(_n1) JIO_32_RW | ||
358 | #define JN_I2C_STATUS(_n1) I2C_STATUS | ||
359 | #define JI_I2C_STATUS(_n1) (_n1) | ||
360 | #define BP_I2C_STATUS_SLVACT 6 | ||
361 | #define BM_I2C_STATUS_SLVACT 0x40 | ||
362 | #define BF_I2C_STATUS_SLVACT(v) (((v) & 0x1) << 6) | ||
363 | #define BFM_I2C_STATUS_SLVACT(v) BM_I2C_STATUS_SLVACT | ||
364 | #define BF_I2C_STATUS_SLVACT_V(e) BF_I2C_STATUS_SLVACT(BV_I2C_STATUS_SLVACT__##e) | ||
365 | #define BFM_I2C_STATUS_SLVACT_V(v) BM_I2C_STATUS_SLVACT | ||
366 | #define BP_I2C_STATUS_MSTACT 5 | ||
367 | #define BM_I2C_STATUS_MSTACT 0x20 | ||
368 | #define BF_I2C_STATUS_MSTACT(v) (((v) & 0x1) << 5) | ||
369 | #define BFM_I2C_STATUS_MSTACT(v) BM_I2C_STATUS_MSTACT | ||
370 | #define BF_I2C_STATUS_MSTACT_V(e) BF_I2C_STATUS_MSTACT(BV_I2C_STATUS_MSTACT__##e) | ||
371 | #define BFM_I2C_STATUS_MSTACT_V(v) BM_I2C_STATUS_MSTACT | ||
372 | #define BP_I2C_STATUS_RFF 4 | ||
373 | #define BM_I2C_STATUS_RFF 0x10 | ||
374 | #define BF_I2C_STATUS_RFF(v) (((v) & 0x1) << 4) | ||
375 | #define BFM_I2C_STATUS_RFF(v) BM_I2C_STATUS_RFF | ||
376 | #define BF_I2C_STATUS_RFF_V(e) BF_I2C_STATUS_RFF(BV_I2C_STATUS_RFF__##e) | ||
377 | #define BFM_I2C_STATUS_RFF_V(v) BM_I2C_STATUS_RFF | ||
378 | #define BP_I2C_STATUS_RFNE 3 | ||
379 | #define BM_I2C_STATUS_RFNE 0x8 | ||
380 | #define BF_I2C_STATUS_RFNE(v) (((v) & 0x1) << 3) | ||
381 | #define BFM_I2C_STATUS_RFNE(v) BM_I2C_STATUS_RFNE | ||
382 | #define BF_I2C_STATUS_RFNE_V(e) BF_I2C_STATUS_RFNE(BV_I2C_STATUS_RFNE__##e) | ||
383 | #define BFM_I2C_STATUS_RFNE_V(v) BM_I2C_STATUS_RFNE | ||
384 | #define BP_I2C_STATUS_TFE 2 | ||
385 | #define BM_I2C_STATUS_TFE 0x4 | ||
386 | #define BF_I2C_STATUS_TFE(v) (((v) & 0x1) << 2) | ||
387 | #define BFM_I2C_STATUS_TFE(v) BM_I2C_STATUS_TFE | ||
388 | #define BF_I2C_STATUS_TFE_V(e) BF_I2C_STATUS_TFE(BV_I2C_STATUS_TFE__##e) | ||
389 | #define BFM_I2C_STATUS_TFE_V(v) BM_I2C_STATUS_TFE | ||
390 | #define BP_I2C_STATUS_TFNF 1 | ||
391 | #define BM_I2C_STATUS_TFNF 0x2 | ||
392 | #define BF_I2C_STATUS_TFNF(v) (((v) & 0x1) << 1) | ||
393 | #define BFM_I2C_STATUS_TFNF(v) BM_I2C_STATUS_TFNF | ||
394 | #define BF_I2C_STATUS_TFNF_V(e) BF_I2C_STATUS_TFNF(BV_I2C_STATUS_TFNF__##e) | ||
395 | #define BFM_I2C_STATUS_TFNF_V(v) BM_I2C_STATUS_TFNF | ||
396 | #define BP_I2C_STATUS_ACT 0 | ||
397 | #define BM_I2C_STATUS_ACT 0x1 | ||
398 | #define BF_I2C_STATUS_ACT(v) (((v) & 0x1) << 0) | ||
399 | #define BFM_I2C_STATUS_ACT(v) BM_I2C_STATUS_ACT | ||
400 | #define BF_I2C_STATUS_ACT_V(e) BF_I2C_STATUS_ACT(BV_I2C_STATUS_ACT__##e) | ||
401 | #define BFM_I2C_STATUS_ACT_V(v) BM_I2C_STATUS_ACT | ||
402 | |||
403 | #define REG_I2C_ENBST(_n1) jz_reg(I2C_ENBST(_n1)) | ||
404 | #define JA_I2C_ENBST(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x9c) | ||
405 | #define JT_I2C_ENBST(_n1) JIO_32_RW | ||
406 | #define JN_I2C_ENBST(_n1) I2C_ENBST | ||
407 | #define JI_I2C_ENBST(_n1) (_n1) | ||
408 | #define BP_I2C_ENBST_SLVRDLST 2 | ||
409 | #define BM_I2C_ENBST_SLVRDLST 0x4 | ||
410 | #define BF_I2C_ENBST_SLVRDLST(v) (((v) & 0x1) << 2) | ||
411 | #define BFM_I2C_ENBST_SLVRDLST(v) BM_I2C_ENBST_SLVRDLST | ||
412 | #define BF_I2C_ENBST_SLVRDLST_V(e) BF_I2C_ENBST_SLVRDLST(BV_I2C_ENBST_SLVRDLST__##e) | ||
413 | #define BFM_I2C_ENBST_SLVRDLST_V(v) BM_I2C_ENBST_SLVRDLST | ||
414 | #define BP_I2C_ENBST_SLVDISB 1 | ||
415 | #define BM_I2C_ENBST_SLVDISB 0x2 | ||
416 | #define BF_I2C_ENBST_SLVDISB(v) (((v) & 0x1) << 1) | ||
417 | #define BFM_I2C_ENBST_SLVDISB(v) BM_I2C_ENBST_SLVDISB | ||
418 | #define BF_I2C_ENBST_SLVDISB_V(e) BF_I2C_ENBST_SLVDISB(BV_I2C_ENBST_SLVDISB__##e) | ||
419 | #define BFM_I2C_ENBST_SLVDISB_V(v) BM_I2C_ENBST_SLVDISB | ||
420 | #define BP_I2C_ENBST_ACTIVE 0 | ||
421 | #define BM_I2C_ENBST_ACTIVE 0x1 | ||
422 | #define BF_I2C_ENBST_ACTIVE(v) (((v) & 0x1) << 0) | ||
423 | #define BFM_I2C_ENBST_ACTIVE(v) BM_I2C_ENBST_ACTIVE | ||
424 | #define BF_I2C_ENBST_ACTIVE_V(e) BF_I2C_ENBST_ACTIVE(BV_I2C_ENBST_ACTIVE__##e) | ||
425 | #define BFM_I2C_ENBST_ACTIVE_V(v) BM_I2C_ENBST_ACTIVE | ||
426 | |||
427 | #define REG_I2C_TAR(_n1) jz_reg(I2C_TAR(_n1)) | ||
428 | #define JA_I2C_TAR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x4) | ||
429 | #define JT_I2C_TAR(_n1) JIO_32_RW | ||
430 | #define JN_I2C_TAR(_n1) I2C_TAR | ||
431 | #define JI_I2C_TAR(_n1) (_n1) | ||
432 | #define BP_I2C_TAR_ADDR 0 | ||
433 | #define BM_I2C_TAR_ADDR 0x3ff | ||
434 | #define BF_I2C_TAR_ADDR(v) (((v) & 0x3ff) << 0) | ||
435 | #define BFM_I2C_TAR_ADDR(v) BM_I2C_TAR_ADDR | ||
436 | #define BF_I2C_TAR_ADDR_V(e) BF_I2C_TAR_ADDR(BV_I2C_TAR_ADDR__##e) | ||
437 | #define BFM_I2C_TAR_ADDR_V(v) BM_I2C_TAR_ADDR | ||
438 | #define BP_I2C_TAR_10BITS 12 | ||
439 | #define BM_I2C_TAR_10BITS 0x1000 | ||
440 | #define BF_I2C_TAR_10BITS(v) (((v) & 0x1) << 12) | ||
441 | #define BFM_I2C_TAR_10BITS(v) BM_I2C_TAR_10BITS | ||
442 | #define BF_I2C_TAR_10BITS_V(e) BF_I2C_TAR_10BITS(BV_I2C_TAR_10BITS__##e) | ||
443 | #define BFM_I2C_TAR_10BITS_V(v) BM_I2C_TAR_10BITS | ||
444 | #define BP_I2C_TAR_SPECIAL 11 | ||
445 | #define BM_I2C_TAR_SPECIAL 0x800 | ||
446 | #define BF_I2C_TAR_SPECIAL(v) (((v) & 0x1) << 11) | ||
447 | #define BFM_I2C_TAR_SPECIAL(v) BM_I2C_TAR_SPECIAL | ||
448 | #define BF_I2C_TAR_SPECIAL_V(e) BF_I2C_TAR_SPECIAL(BV_I2C_TAR_SPECIAL__##e) | ||
449 | #define BFM_I2C_TAR_SPECIAL_V(v) BM_I2C_TAR_SPECIAL | ||
450 | #define BP_I2C_TAR_GC_OR_START 10 | ||
451 | #define BM_I2C_TAR_GC_OR_START 0x400 | ||
452 | #define BF_I2C_TAR_GC_OR_START(v) (((v) & 0x1) << 10) | ||
453 | #define BFM_I2C_TAR_GC_OR_START(v) BM_I2C_TAR_GC_OR_START | ||
454 | #define BF_I2C_TAR_GC_OR_START_V(e) BF_I2C_TAR_GC_OR_START(BV_I2C_TAR_GC_OR_START__##e) | ||
455 | #define BFM_I2C_TAR_GC_OR_START_V(v) BM_I2C_TAR_GC_OR_START | ||
456 | |||
457 | #define REG_I2C_SAR(_n1) jz_reg(I2C_SAR(_n1)) | ||
458 | #define JA_I2C_SAR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x8) | ||
459 | #define JT_I2C_SAR(_n1) JIO_32_RW | ||
460 | #define JN_I2C_SAR(_n1) I2C_SAR | ||
461 | #define JI_I2C_SAR(_n1) (_n1) | ||
462 | |||
463 | #define REG_I2C_SHCNT(_n1) jz_reg(I2C_SHCNT(_n1)) | ||
464 | #define JA_I2C_SHCNT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x14) | ||
465 | #define JT_I2C_SHCNT(_n1) JIO_32_RW | ||
466 | #define JN_I2C_SHCNT(_n1) I2C_SHCNT | ||
467 | #define JI_I2C_SHCNT(_n1) (_n1) | ||
468 | |||
469 | #define REG_I2C_SLCNT(_n1) jz_reg(I2C_SLCNT(_n1)) | ||
470 | #define JA_I2C_SLCNT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x18) | ||
471 | #define JT_I2C_SLCNT(_n1) JIO_32_RW | ||
472 | #define JN_I2C_SLCNT(_n1) I2C_SLCNT | ||
473 | #define JI_I2C_SLCNT(_n1) (_n1) | ||
474 | |||
475 | #define REG_I2C_FHCNT(_n1) jz_reg(I2C_FHCNT(_n1)) | ||
476 | #define JA_I2C_FHCNT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x1c) | ||
477 | #define JT_I2C_FHCNT(_n1) JIO_32_RW | ||
478 | #define JN_I2C_FHCNT(_n1) I2C_FHCNT | ||
479 | #define JI_I2C_FHCNT(_n1) (_n1) | ||
480 | |||
481 | #define REG_I2C_FLCNT(_n1) jz_reg(I2C_FLCNT(_n1)) | ||
482 | #define JA_I2C_FLCNT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x20) | ||
483 | #define JT_I2C_FLCNT(_n1) JIO_32_RW | ||
484 | #define JN_I2C_FLCNT(_n1) I2C_FLCNT | ||
485 | #define JI_I2C_FLCNT(_n1) (_n1) | ||
486 | |||
487 | #define REG_I2C_RXTL(_n1) jz_reg(I2C_RXTL(_n1)) | ||
488 | #define JA_I2C_RXTL(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x38) | ||
489 | #define JT_I2C_RXTL(_n1) JIO_32_RW | ||
490 | #define JN_I2C_RXTL(_n1) I2C_RXTL | ||
491 | #define JI_I2C_RXTL(_n1) (_n1) | ||
492 | |||
493 | #define REG_I2C_TXTL(_n1) jz_reg(I2C_TXTL(_n1)) | ||
494 | #define JA_I2C_TXTL(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x3c) | ||
495 | #define JT_I2C_TXTL(_n1) JIO_32_RW | ||
496 | #define JN_I2C_TXTL(_n1) I2C_TXTL | ||
497 | #define JI_I2C_TXTL(_n1) (_n1) | ||
498 | |||
499 | #define REG_I2C_TXFLR(_n1) jz_reg(I2C_TXFLR(_n1)) | ||
500 | #define JA_I2C_TXFLR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x74) | ||
501 | #define JT_I2C_TXFLR(_n1) JIO_32_RW | ||
502 | #define JN_I2C_TXFLR(_n1) I2C_TXFLR | ||
503 | #define JI_I2C_TXFLR(_n1) (_n1) | ||
504 | |||
505 | #define REG_I2C_RXFLR(_n1) jz_reg(I2C_RXFLR(_n1)) | ||
506 | #define JA_I2C_RXFLR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x78) | ||
507 | #define JT_I2C_RXFLR(_n1) JIO_32_RW | ||
508 | #define JN_I2C_RXFLR(_n1) I2C_RXFLR | ||
509 | #define JI_I2C_RXFLR(_n1) (_n1) | ||
510 | |||
511 | #define REG_I2C_SDAHD(_n1) jz_reg(I2C_SDAHD(_n1)) | ||
512 | #define JA_I2C_SDAHD(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x7c) | ||
513 | #define JT_I2C_SDAHD(_n1) JIO_32_RW | ||
514 | #define JN_I2C_SDAHD(_n1) I2C_SDAHD | ||
515 | #define JI_I2C_SDAHD(_n1) (_n1) | ||
516 | |||
517 | #define REG_I2C_ABTSRC(_n1) jz_reg(I2C_ABTSRC(_n1)) | ||
518 | #define JA_I2C_ABTSRC(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x80) | ||
519 | #define JT_I2C_ABTSRC(_n1) JIO_32_RW | ||
520 | #define JN_I2C_ABTSRC(_n1) I2C_ABTSRC | ||
521 | #define JI_I2C_ABTSRC(_n1) (_n1) | ||
522 | |||
523 | #define REG_I2C_DMACR(_n1) jz_reg(I2C_DMACR(_n1)) | ||
524 | #define JA_I2C_DMACR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x88) | ||
525 | #define JT_I2C_DMACR(_n1) JIO_32_RW | ||
526 | #define JN_I2C_DMACR(_n1) I2C_DMACR | ||
527 | #define JI_I2C_DMACR(_n1) (_n1) | ||
528 | |||
529 | #define REG_I2C_DMATDLR(_n1) jz_reg(I2C_DMATDLR(_n1)) | ||
530 | #define JA_I2C_DMATDLR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x8c) | ||
531 | #define JT_I2C_DMATDLR(_n1) JIO_32_RW | ||
532 | #define JN_I2C_DMATDLR(_n1) I2C_DMATDLR | ||
533 | #define JI_I2C_DMATDLR(_n1) (_n1) | ||
534 | |||
535 | #define REG_I2C_DMARDLR(_n1) jz_reg(I2C_DMARDLR(_n1)) | ||
536 | #define JA_I2C_DMARDLR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x90) | ||
537 | #define JT_I2C_DMARDLR(_n1) JIO_32_RW | ||
538 | #define JN_I2C_DMARDLR(_n1) I2C_DMARDLR | ||
539 | #define JI_I2C_DMARDLR(_n1) (_n1) | ||
540 | |||
541 | #define REG_I2C_SDASU(_n1) jz_reg(I2C_SDASU(_n1)) | ||
542 | #define JA_I2C_SDASU(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x94) | ||
543 | #define JT_I2C_SDASU(_n1) JIO_32_RW | ||
544 | #define JN_I2C_SDASU(_n1) I2C_SDASU | ||
545 | #define JI_I2C_SDASU(_n1) (_n1) | ||
546 | |||
547 | #define REG_I2C_ACKGC(_n1) jz_reg(I2C_ACKGC(_n1)) | ||
548 | #define JA_I2C_ACKGC(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x98) | ||
549 | #define JT_I2C_ACKGC(_n1) JIO_32_RW | ||
550 | #define JN_I2C_ACKGC(_n1) I2C_ACKGC | ||
551 | #define JI_I2C_ACKGC(_n1) (_n1) | ||
552 | |||
553 | #define REG_I2C_FLT(_n1) jz_reg(I2C_FLT(_n1)) | ||
554 | #define JA_I2C_FLT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0xa0) | ||
555 | #define JT_I2C_FLT(_n1) JIO_32_RW | ||
556 | #define JN_I2C_FLT(_n1) I2C_FLT | ||
557 | #define JI_I2C_FLT(_n1) (_n1) | ||
558 | |||
559 | #define REG_I2C_CINT(_n1) jz_reg(I2C_CINT(_n1)) | ||
560 | #define JA_I2C_CINT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x40) | ||
561 | #define JT_I2C_CINT(_n1) JIO_32_RW | ||
562 | #define JN_I2C_CINT(_n1) I2C_CINT | ||
563 | #define JI_I2C_CINT(_n1) (_n1) | ||
564 | |||
565 | #define REG_I2C_CRXUF(_n1) jz_reg(I2C_CRXUF(_n1)) | ||
566 | #define JA_I2C_CRXUF(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x44) | ||
567 | #define JT_I2C_CRXUF(_n1) JIO_32_RW | ||
568 | #define JN_I2C_CRXUF(_n1) I2C_CRXUF | ||
569 | #define JI_I2C_CRXUF(_n1) (_n1) | ||
570 | |||
571 | #define REG_I2C_CRXOF(_n1) jz_reg(I2C_CRXOF(_n1)) | ||
572 | #define JA_I2C_CRXOF(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x48) | ||
573 | #define JT_I2C_CRXOF(_n1) JIO_32_RW | ||
574 | #define JN_I2C_CRXOF(_n1) I2C_CRXOF | ||
575 | #define JI_I2C_CRXOF(_n1) (_n1) | ||
576 | |||
577 | #define REG_I2C_CTXOF(_n1) jz_reg(I2C_CTXOF(_n1)) | ||
578 | #define JA_I2C_CTXOF(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x4c) | ||
579 | #define JT_I2C_CTXOF(_n1) JIO_32_RW | ||
580 | #define JN_I2C_CTXOF(_n1) I2C_CTXOF | ||
581 | #define JI_I2C_CTXOF(_n1) (_n1) | ||
582 | |||
583 | #define REG_I2C_CRXREQ(_n1) jz_reg(I2C_CRXREQ(_n1)) | ||
584 | #define JA_I2C_CRXREQ(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x50) | ||
585 | #define JT_I2C_CRXREQ(_n1) JIO_32_RW | ||
586 | #define JN_I2C_CRXREQ(_n1) I2C_CRXREQ | ||
587 | #define JI_I2C_CRXREQ(_n1) (_n1) | ||
588 | |||
589 | #define REG_I2C_CTXABT(_n1) jz_reg(I2C_CTXABT(_n1)) | ||
590 | #define JA_I2C_CTXABT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x54) | ||
591 | #define JT_I2C_CTXABT(_n1) JIO_32_RW | ||
592 | #define JN_I2C_CTXABT(_n1) I2C_CTXABT | ||
593 | #define JI_I2C_CTXABT(_n1) (_n1) | ||
594 | |||
595 | #define REG_I2C_CRXDN(_n1) jz_reg(I2C_CRXDN(_n1)) | ||
596 | #define JA_I2C_CRXDN(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x58) | ||
597 | #define JT_I2C_CRXDN(_n1) JIO_32_RW | ||
598 | #define JN_I2C_CRXDN(_n1) I2C_CRXDN | ||
599 | #define JI_I2C_CRXDN(_n1) (_n1) | ||
600 | |||
601 | #define REG_I2C_CACT(_n1) jz_reg(I2C_CACT(_n1)) | ||
602 | #define JA_I2C_CACT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x5c) | ||
603 | #define JT_I2C_CACT(_n1) JIO_32_RW | ||
604 | #define JN_I2C_CACT(_n1) I2C_CACT | ||
605 | #define JI_I2C_CACT(_n1) (_n1) | ||
606 | |||
607 | #define REG_I2C_CSTP(_n1) jz_reg(I2C_CSTP(_n1)) | ||
608 | #define JA_I2C_CSTP(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x60) | ||
609 | #define JT_I2C_CSTP(_n1) JIO_32_RW | ||
610 | #define JN_I2C_CSTP(_n1) I2C_CSTP | ||
611 | #define JI_I2C_CSTP(_n1) (_n1) | ||
612 | |||
613 | #define REG_I2C_CSTT(_n1) jz_reg(I2C_CSTT(_n1)) | ||
614 | #define JA_I2C_CSTT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x64) | ||
615 | #define JT_I2C_CSTT(_n1) JIO_32_RW | ||
616 | #define JN_I2C_CSTT(_n1) I2C_CSTT | ||
617 | #define JI_I2C_CSTT(_n1) (_n1) | ||
618 | |||
619 | #define REG_I2C_CGC(_n1) jz_reg(I2C_CGC(_n1)) | ||
620 | #define JA_I2C_CGC(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x68) | ||
621 | #define JT_I2C_CGC(_n1) JIO_32_RW | ||
622 | #define JN_I2C_CGC(_n1) I2C_CGC | ||
623 | #define JI_I2C_CGC(_n1) (_n1) | ||
624 | |||
625 | #endif /* __HEADERGEN_I2C_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/intc.h b/firmware/target/mips/ingenic_x1000/x1000/intc.h new file mode 100644 index 0000000000..37fbf33fb6 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/intc.h | |||
@@ -0,0 +1,57 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_INTC_H__ | ||
25 | #define __HEADERGEN_INTC_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_INTC_SRC(_n1) jz_reg(INTC_SRC(_n1)) | ||
30 | #define JA_INTC_SRC(_n1) (0xb0001000 + 0x0 + (_n1) * 0x20) | ||
31 | #define JT_INTC_SRC(_n1) JIO_32_RW | ||
32 | #define JN_INTC_SRC(_n1) INTC_SRC | ||
33 | #define JI_INTC_SRC(_n1) (_n1) | ||
34 | |||
35 | #define REG_INTC_MSK(_n1) jz_reg(INTC_MSK(_n1)) | ||
36 | #define JA_INTC_MSK(_n1) (0xb0001000 + 0x4 + (_n1) * 0x20) | ||
37 | #define JT_INTC_MSK(_n1) JIO_32_RW | ||
38 | #define JN_INTC_MSK(_n1) INTC_MSK | ||
39 | #define JI_INTC_MSK(_n1) (_n1) | ||
40 | #define REG_INTC_MSK_SET(_n1) jz_reg(INTC_MSK_SET(_n1)) | ||
41 | #define JA_INTC_MSK_SET(_n1) (JA_INTC_MSK(_n1) + 0x4) | ||
42 | #define JT_INTC_MSK_SET(_n1) JIO_32_WO | ||
43 | #define JN_INTC_MSK_SET(_n1) INTC_MSK | ||
44 | #define JI_INTC_MSK_SET(_n1) (_n1) | ||
45 | #define REG_INTC_MSK_CLR(_n1) jz_reg(INTC_MSK_CLR(_n1)) | ||
46 | #define JA_INTC_MSK_CLR(_n1) (JA_INTC_MSK(_n1) + 0x8) | ||
47 | #define JT_INTC_MSK_CLR(_n1) JIO_32_WO | ||
48 | #define JN_INTC_MSK_CLR(_n1) INTC_MSK | ||
49 | #define JI_INTC_MSK_CLR(_n1) (_n1) | ||
50 | |||
51 | #define REG_INTC_PND(_n1) jz_reg(INTC_PND(_n1)) | ||
52 | #define JA_INTC_PND(_n1) (0xb0001000 + 0x10 + (_n1) * 0x20) | ||
53 | #define JT_INTC_PND(_n1) JIO_32_RW | ||
54 | #define JN_INTC_PND(_n1) INTC_PND | ||
55 | #define JI_INTC_PND(_n1) (_n1) | ||
56 | |||
57 | #endif /* __HEADERGEN_INTC_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/lcd.h b/firmware/target/mips/ingenic_x1000/x1000/lcd.h new file mode 100644 index 0000000000..d4c1fe1878 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/lcd.h | |||
@@ -0,0 +1,446 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_LCD_H__ | ||
25 | #define __HEADERGEN_LCD_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_LCD_CFG jz_reg(LCD_CFG) | ||
30 | #define JA_LCD_CFG (0xb3050000 + 0x0) | ||
31 | #define JT_LCD_CFG JIO_32_RW | ||
32 | #define JN_LCD_CFG LCD_CFG | ||
33 | #define JI_LCD_CFG | ||
34 | #define BP_LCD_CFG_INVDAT 17 | ||
35 | #define BM_LCD_CFG_INVDAT 0x20000 | ||
36 | #define BF_LCD_CFG_INVDAT(v) (((v) & 0x1) << 17) | ||
37 | #define BFM_LCD_CFG_INVDAT(v) BM_LCD_CFG_INVDAT | ||
38 | #define BF_LCD_CFG_INVDAT_V(e) BF_LCD_CFG_INVDAT(BV_LCD_CFG_INVDAT__##e) | ||
39 | #define BFM_LCD_CFG_INVDAT_V(v) BM_LCD_CFG_INVDAT | ||
40 | |||
41 | #define REG_LCD_CTRL jz_reg(LCD_CTRL) | ||
42 | #define JA_LCD_CTRL (0xb3050000 + 0x30) | ||
43 | #define JT_LCD_CTRL JIO_32_RW | ||
44 | #define JN_LCD_CTRL LCD_CTRL | ||
45 | #define JI_LCD_CTRL | ||
46 | #define BP_LCD_CTRL_BURST 28 | ||
47 | #define BM_LCD_CTRL_BURST 0x70000000 | ||
48 | #define BV_LCD_CTRL_BURST__4WORD 0x0 | ||
49 | #define BV_LCD_CTRL_BURST__8WORD 0x1 | ||
50 | #define BV_LCD_CTRL_BURST__16WORD 0x2 | ||
51 | #define BV_LCD_CTRL_BURST__32WORD 0x3 | ||
52 | #define BV_LCD_CTRL_BURST__64WORD 0x4 | ||
53 | #define BF_LCD_CTRL_BURST(v) (((v) & 0x7) << 28) | ||
54 | #define BFM_LCD_CTRL_BURST(v) BM_LCD_CTRL_BURST | ||
55 | #define BF_LCD_CTRL_BURST_V(e) BF_LCD_CTRL_BURST(BV_LCD_CTRL_BURST__##e) | ||
56 | #define BFM_LCD_CTRL_BURST_V(v) BM_LCD_CTRL_BURST | ||
57 | #define BP_LCD_CTRL_BPP 0 | ||
58 | #define BM_LCD_CTRL_BPP 0x7 | ||
59 | #define BV_LCD_CTRL_BPP__15BIT_OR_16BIT 0x4 | ||
60 | #define BV_LCD_CTRL_BPP__18BIT_OR_24BIT 0x5 | ||
61 | #define BV_LCD_CTRL_BPP__24BIT_COMPRESSED 0x6 | ||
62 | #define BV_LCD_CTRL_BPP__30BIT 0x7 | ||
63 | #define BF_LCD_CTRL_BPP(v) (((v) & 0x7) << 0) | ||
64 | #define BFM_LCD_CTRL_BPP(v) BM_LCD_CTRL_BPP | ||
65 | #define BF_LCD_CTRL_BPP_V(e) BF_LCD_CTRL_BPP(BV_LCD_CTRL_BPP__##e) | ||
66 | #define BFM_LCD_CTRL_BPP_V(v) BM_LCD_CTRL_BPP | ||
67 | #define BP_LCD_CTRL_EOFM 13 | ||
68 | #define BM_LCD_CTRL_EOFM 0x2000 | ||
69 | #define BF_LCD_CTRL_EOFM(v) (((v) & 0x1) << 13) | ||
70 | #define BFM_LCD_CTRL_EOFM(v) BM_LCD_CTRL_EOFM | ||
71 | #define BF_LCD_CTRL_EOFM_V(e) BF_LCD_CTRL_EOFM(BV_LCD_CTRL_EOFM__##e) | ||
72 | #define BFM_LCD_CTRL_EOFM_V(v) BM_LCD_CTRL_EOFM | ||
73 | #define BP_LCD_CTRL_SOFM 12 | ||
74 | #define BM_LCD_CTRL_SOFM 0x1000 | ||
75 | #define BF_LCD_CTRL_SOFM(v) (((v) & 0x1) << 12) | ||
76 | #define BFM_LCD_CTRL_SOFM(v) BM_LCD_CTRL_SOFM | ||
77 | #define BF_LCD_CTRL_SOFM_V(e) BF_LCD_CTRL_SOFM(BV_LCD_CTRL_SOFM__##e) | ||
78 | #define BFM_LCD_CTRL_SOFM_V(v) BM_LCD_CTRL_SOFM | ||
79 | #define BP_LCD_CTRL_IFUM 10 | ||
80 | #define BM_LCD_CTRL_IFUM 0x400 | ||
81 | #define BF_LCD_CTRL_IFUM(v) (((v) & 0x1) << 10) | ||
82 | #define BFM_LCD_CTRL_IFUM(v) BM_LCD_CTRL_IFUM | ||
83 | #define BF_LCD_CTRL_IFUM_V(e) BF_LCD_CTRL_IFUM(BV_LCD_CTRL_IFUM__##e) | ||
84 | #define BFM_LCD_CTRL_IFUM_V(v) BM_LCD_CTRL_IFUM | ||
85 | #define BP_LCD_CTRL_QDM 7 | ||
86 | #define BM_LCD_CTRL_QDM 0x80 | ||
87 | #define BF_LCD_CTRL_QDM(v) (((v) & 0x1) << 7) | ||
88 | #define BFM_LCD_CTRL_QDM(v) BM_LCD_CTRL_QDM | ||
89 | #define BF_LCD_CTRL_QDM_V(e) BF_LCD_CTRL_QDM(BV_LCD_CTRL_QDM__##e) | ||
90 | #define BFM_LCD_CTRL_QDM_V(v) BM_LCD_CTRL_QDM | ||
91 | #define BP_LCD_CTRL_BEDN 6 | ||
92 | #define BM_LCD_CTRL_BEDN 0x40 | ||
93 | #define BF_LCD_CTRL_BEDN(v) (((v) & 0x1) << 6) | ||
94 | #define BFM_LCD_CTRL_BEDN(v) BM_LCD_CTRL_BEDN | ||
95 | #define BF_LCD_CTRL_BEDN_V(e) BF_LCD_CTRL_BEDN(BV_LCD_CTRL_BEDN__##e) | ||
96 | #define BFM_LCD_CTRL_BEDN_V(v) BM_LCD_CTRL_BEDN | ||
97 | #define BP_LCD_CTRL_PEDN 5 | ||
98 | #define BM_LCD_CTRL_PEDN 0x20 | ||
99 | #define BF_LCD_CTRL_PEDN(v) (((v) & 0x1) << 5) | ||
100 | #define BFM_LCD_CTRL_PEDN(v) BM_LCD_CTRL_PEDN | ||
101 | #define BF_LCD_CTRL_PEDN_V(e) BF_LCD_CTRL_PEDN(BV_LCD_CTRL_PEDN__##e) | ||
102 | #define BFM_LCD_CTRL_PEDN_V(v) BM_LCD_CTRL_PEDN | ||
103 | #define BP_LCD_CTRL_ENABLE 3 | ||
104 | #define BM_LCD_CTRL_ENABLE 0x8 | ||
105 | #define BF_LCD_CTRL_ENABLE(v) (((v) & 0x1) << 3) | ||
106 | #define BFM_LCD_CTRL_ENABLE(v) BM_LCD_CTRL_ENABLE | ||
107 | #define BF_LCD_CTRL_ENABLE_V(e) BF_LCD_CTRL_ENABLE(BV_LCD_CTRL_ENABLE__##e) | ||
108 | #define BFM_LCD_CTRL_ENABLE_V(v) BM_LCD_CTRL_ENABLE | ||
109 | |||
110 | #define REG_LCD_STATE jz_reg(LCD_STATE) | ||
111 | #define JA_LCD_STATE (0xb3050000 + 0x34) | ||
112 | #define JT_LCD_STATE JIO_32_RW | ||
113 | #define JN_LCD_STATE LCD_STATE | ||
114 | #define JI_LCD_STATE | ||
115 | #define BP_LCD_STATE_QD 7 | ||
116 | #define BM_LCD_STATE_QD 0x80 | ||
117 | #define BF_LCD_STATE_QD(v) (((v) & 0x1) << 7) | ||
118 | #define BFM_LCD_STATE_QD(v) BM_LCD_STATE_QD | ||
119 | #define BF_LCD_STATE_QD_V(e) BF_LCD_STATE_QD(BV_LCD_STATE_QD__##e) | ||
120 | #define BFM_LCD_STATE_QD_V(v) BM_LCD_STATE_QD | ||
121 | #define BP_LCD_STATE_EOF 5 | ||
122 | #define BM_LCD_STATE_EOF 0x20 | ||
123 | #define BF_LCD_STATE_EOF(v) (((v) & 0x1) << 5) | ||
124 | #define BFM_LCD_STATE_EOF(v) BM_LCD_STATE_EOF | ||
125 | #define BF_LCD_STATE_EOF_V(e) BF_LCD_STATE_EOF(BV_LCD_STATE_EOF__##e) | ||
126 | #define BFM_LCD_STATE_EOF_V(v) BM_LCD_STATE_EOF | ||
127 | #define BP_LCD_STATE_SOF 4 | ||
128 | #define BM_LCD_STATE_SOF 0x10 | ||
129 | #define BF_LCD_STATE_SOF(v) (((v) & 0x1) << 4) | ||
130 | #define BFM_LCD_STATE_SOF(v) BM_LCD_STATE_SOF | ||
131 | #define BF_LCD_STATE_SOF_V(e) BF_LCD_STATE_SOF(BV_LCD_STATE_SOF__##e) | ||
132 | #define BFM_LCD_STATE_SOF_V(v) BM_LCD_STATE_SOF | ||
133 | #define BP_LCD_STATE_IFU 2 | ||
134 | #define BM_LCD_STATE_IFU 0x4 | ||
135 | #define BF_LCD_STATE_IFU(v) (((v) & 0x1) << 2) | ||
136 | #define BFM_LCD_STATE_IFU(v) BM_LCD_STATE_IFU | ||
137 | #define BF_LCD_STATE_IFU_V(e) BF_LCD_STATE_IFU(BV_LCD_STATE_IFU__##e) | ||
138 | #define BFM_LCD_STATE_IFU_V(v) BM_LCD_STATE_IFU | ||
139 | |||
140 | #define REG_LCD_OSDCTRL jz_reg(LCD_OSDCTRL) | ||
141 | #define JA_LCD_OSDCTRL (0xb3050000 + 0x104) | ||
142 | #define JT_LCD_OSDCTRL JIO_32_RW | ||
143 | #define JN_LCD_OSDCTRL LCD_OSDCTRL | ||
144 | #define JI_LCD_OSDCTRL | ||
145 | |||
146 | #define REG_LCD_BGC jz_reg(LCD_BGC) | ||
147 | #define JA_LCD_BGC (0xb3050000 + 0x10c) | ||
148 | #define JT_LCD_BGC JIO_32_RW | ||
149 | #define JN_LCD_BGC LCD_BGC | ||
150 | #define JI_LCD_BGC | ||
151 | |||
152 | #define REG_LCD_DAH jz_reg(LCD_DAH) | ||
153 | #define JA_LCD_DAH (0xb3050000 + 0x10) | ||
154 | #define JT_LCD_DAH JIO_32_RW | ||
155 | #define JN_LCD_DAH LCD_DAH | ||
156 | #define JI_LCD_DAH | ||
157 | |||
158 | #define REG_LCD_DAV jz_reg(LCD_DAV) | ||
159 | #define JA_LCD_DAV (0xb3050000 + 0x14) | ||
160 | #define JT_LCD_DAV JIO_32_RW | ||
161 | #define JN_LCD_DAV LCD_DAV | ||
162 | #define JI_LCD_DAV | ||
163 | |||
164 | #define REG_LCD_VAT jz_reg(LCD_VAT) | ||
165 | #define JA_LCD_VAT (0xb3050000 + 0xc) | ||
166 | #define JT_LCD_VAT JIO_32_RW | ||
167 | #define JN_LCD_VAT LCD_VAT | ||
168 | #define JI_LCD_VAT | ||
169 | |||
170 | #define REG_LCD_VSYNC jz_reg(LCD_VSYNC) | ||
171 | #define JA_LCD_VSYNC (0xb3050000 + 0x4) | ||
172 | #define JT_LCD_VSYNC JIO_32_RW | ||
173 | #define JN_LCD_VSYNC LCD_VSYNC | ||
174 | #define JI_LCD_VSYNC | ||
175 | |||
176 | #define REG_LCD_HSYNC jz_reg(LCD_HSYNC) | ||
177 | #define JA_LCD_HSYNC (0xb3050000 + 0x8) | ||
178 | #define JT_LCD_HSYNC JIO_32_RW | ||
179 | #define JN_LCD_HSYNC LCD_HSYNC | ||
180 | #define JI_LCD_HSYNC | ||
181 | |||
182 | #define REG_LCD_IID jz_reg(LCD_IID) | ||
183 | #define JA_LCD_IID (0xb3050000 + 0x38) | ||
184 | #define JT_LCD_IID JIO_32_RW | ||
185 | #define JN_LCD_IID LCD_IID | ||
186 | #define JI_LCD_IID | ||
187 | |||
188 | #define REG_LCD_DA jz_reg(LCD_DA) | ||
189 | #define JA_LCD_DA (0xb3050000 + 0x40) | ||
190 | #define JT_LCD_DA JIO_32_RW | ||
191 | #define JN_LCD_DA LCD_DA | ||
192 | #define JI_LCD_DA | ||
193 | |||
194 | #define REG_LCD_MCFG jz_reg(LCD_MCFG) | ||
195 | #define JA_LCD_MCFG (0xb3050000 + 0xa0) | ||
196 | #define JT_LCD_MCFG JIO_32_RW | ||
197 | #define JN_LCD_MCFG LCD_MCFG | ||
198 | #define JI_LCD_MCFG | ||
199 | #define BP_LCD_MCFG_CWIDTH 8 | ||
200 | #define BM_LCD_MCFG_CWIDTH 0x300 | ||
201 | #define BV_LCD_MCFG_CWIDTH__16BIT_OR_9BIT 0x0 | ||
202 | #define BV_LCD_MCFG_CWIDTH__8BIT 0x1 | ||
203 | #define BV_LCD_MCFG_CWIDTH__18BIT 0x2 | ||
204 | #define BV_LCD_MCFG_CWIDTH__24BIT 0x3 | ||
205 | #define BF_LCD_MCFG_CWIDTH(v) (((v) & 0x3) << 8) | ||
206 | #define BFM_LCD_MCFG_CWIDTH(v) BM_LCD_MCFG_CWIDTH | ||
207 | #define BF_LCD_MCFG_CWIDTH_V(e) BF_LCD_MCFG_CWIDTH(BV_LCD_MCFG_CWIDTH__##e) | ||
208 | #define BFM_LCD_MCFG_CWIDTH_V(v) BM_LCD_MCFG_CWIDTH | ||
209 | |||
210 | #define REG_LCD_MCFG_NEW jz_reg(LCD_MCFG_NEW) | ||
211 | #define JA_LCD_MCFG_NEW (0xb3050000 + 0xb8) | ||
212 | #define JT_LCD_MCFG_NEW JIO_32_RW | ||
213 | #define JN_LCD_MCFG_NEW LCD_MCFG_NEW | ||
214 | #define JI_LCD_MCFG_NEW | ||
215 | #define BP_LCD_MCFG_NEW_DWIDTH 13 | ||
216 | #define BM_LCD_MCFG_NEW_DWIDTH 0xe000 | ||
217 | #define BV_LCD_MCFG_NEW_DWIDTH__8BIT 0x0 | ||
218 | #define BV_LCD_MCFG_NEW_DWIDTH__9BIT 0x1 | ||
219 | #define BV_LCD_MCFG_NEW_DWIDTH__16BIT 0x2 | ||
220 | #define BV_LCD_MCFG_NEW_DWIDTH__18BIT 0x3 | ||
221 | #define BV_LCD_MCFG_NEW_DWIDTH__24BIT 0x4 | ||
222 | #define BF_LCD_MCFG_NEW_DWIDTH(v) (((v) & 0x7) << 13) | ||
223 | #define BFM_LCD_MCFG_NEW_DWIDTH(v) BM_LCD_MCFG_NEW_DWIDTH | ||
224 | #define BF_LCD_MCFG_NEW_DWIDTH_V(e) BF_LCD_MCFG_NEW_DWIDTH(BV_LCD_MCFG_NEW_DWIDTH__##e) | ||
225 | #define BFM_LCD_MCFG_NEW_DWIDTH_V(v) BM_LCD_MCFG_NEW_DWIDTH | ||
226 | #define BP_LCD_MCFG_NEW_DTIMES 8 | ||
227 | #define BM_LCD_MCFG_NEW_DTIMES 0x300 | ||
228 | #define BV_LCD_MCFG_NEW_DTIMES__1TIME 0x0 | ||
229 | #define BV_LCD_MCFG_NEW_DTIMES__2TIME 0x1 | ||
230 | #define BV_LCD_MCFG_NEW_DTIMES__3TIME 0x2 | ||
231 | #define BF_LCD_MCFG_NEW_DTIMES(v) (((v) & 0x3) << 8) | ||
232 | #define BFM_LCD_MCFG_NEW_DTIMES(v) BM_LCD_MCFG_NEW_DTIMES | ||
233 | #define BF_LCD_MCFG_NEW_DTIMES_V(e) BF_LCD_MCFG_NEW_DTIMES(BV_LCD_MCFG_NEW_DTIMES__##e) | ||
234 | #define BFM_LCD_MCFG_NEW_DTIMES_V(v) BM_LCD_MCFG_NEW_DTIMES | ||
235 | #define BP_LCD_MCFG_NEW_6800_MODE 11 | ||
236 | #define BM_LCD_MCFG_NEW_6800_MODE 0x800 | ||
237 | #define BF_LCD_MCFG_NEW_6800_MODE(v) (((v) & 0x1) << 11) | ||
238 | #define BFM_LCD_MCFG_NEW_6800_MODE(v) BM_LCD_MCFG_NEW_6800_MODE | ||
239 | #define BF_LCD_MCFG_NEW_6800_MODE_V(e) BF_LCD_MCFG_NEW_6800_MODE(BV_LCD_MCFG_NEW_6800_MODE__##e) | ||
240 | #define BFM_LCD_MCFG_NEW_6800_MODE_V(v) BM_LCD_MCFG_NEW_6800_MODE | ||
241 | #define BP_LCD_MCFG_NEW_CMD_9BIT 10 | ||
242 | #define BM_LCD_MCFG_NEW_CMD_9BIT 0x400 | ||
243 | #define BF_LCD_MCFG_NEW_CMD_9BIT(v) (((v) & 0x1) << 10) | ||
244 | #define BFM_LCD_MCFG_NEW_CMD_9BIT(v) BM_LCD_MCFG_NEW_CMD_9BIT | ||
245 | #define BF_LCD_MCFG_NEW_CMD_9BIT_V(e) BF_LCD_MCFG_NEW_CMD_9BIT(BV_LCD_MCFG_NEW_CMD_9BIT__##e) | ||
246 | #define BFM_LCD_MCFG_NEW_CMD_9BIT_V(v) BM_LCD_MCFG_NEW_CMD_9BIT | ||
247 | #define BP_LCD_MCFG_NEW_CSPLY 5 | ||
248 | #define BM_LCD_MCFG_NEW_CSPLY 0x20 | ||
249 | #define BF_LCD_MCFG_NEW_CSPLY(v) (((v) & 0x1) << 5) | ||
250 | #define BFM_LCD_MCFG_NEW_CSPLY(v) BM_LCD_MCFG_NEW_CSPLY | ||
251 | #define BF_LCD_MCFG_NEW_CSPLY_V(e) BF_LCD_MCFG_NEW_CSPLY(BV_LCD_MCFG_NEW_CSPLY__##e) | ||
252 | #define BFM_LCD_MCFG_NEW_CSPLY_V(v) BM_LCD_MCFG_NEW_CSPLY | ||
253 | #define BP_LCD_MCFG_NEW_RSPLY 4 | ||
254 | #define BM_LCD_MCFG_NEW_RSPLY 0x10 | ||
255 | #define BF_LCD_MCFG_NEW_RSPLY(v) (((v) & 0x1) << 4) | ||
256 | #define BFM_LCD_MCFG_NEW_RSPLY(v) BM_LCD_MCFG_NEW_RSPLY | ||
257 | #define BF_LCD_MCFG_NEW_RSPLY_V(e) BF_LCD_MCFG_NEW_RSPLY(BV_LCD_MCFG_NEW_RSPLY__##e) | ||
258 | #define BFM_LCD_MCFG_NEW_RSPLY_V(v) BM_LCD_MCFG_NEW_RSPLY | ||
259 | #define BP_LCD_MCFG_NEW_CLKPLY 3 | ||
260 | #define BM_LCD_MCFG_NEW_CLKPLY 0x8 | ||
261 | #define BF_LCD_MCFG_NEW_CLKPLY(v) (((v) & 0x1) << 3) | ||
262 | #define BFM_LCD_MCFG_NEW_CLKPLY(v) BM_LCD_MCFG_NEW_CLKPLY | ||
263 | #define BF_LCD_MCFG_NEW_CLKPLY_V(e) BF_LCD_MCFG_NEW_CLKPLY(BV_LCD_MCFG_NEW_CLKPLY__##e) | ||
264 | #define BFM_LCD_MCFG_NEW_CLKPLY_V(v) BM_LCD_MCFG_NEW_CLKPLY | ||
265 | #define BP_LCD_MCFG_NEW_DTYPE 2 | ||
266 | #define BM_LCD_MCFG_NEW_DTYPE 0x4 | ||
267 | #define BV_LCD_MCFG_NEW_DTYPE__SERIAL 0x1 | ||
268 | #define BV_LCD_MCFG_NEW_DTYPE__PARALLEL 0x0 | ||
269 | #define BF_LCD_MCFG_NEW_DTYPE(v) (((v) & 0x1) << 2) | ||
270 | #define BFM_LCD_MCFG_NEW_DTYPE(v) BM_LCD_MCFG_NEW_DTYPE | ||
271 | #define BF_LCD_MCFG_NEW_DTYPE_V(e) BF_LCD_MCFG_NEW_DTYPE(BV_LCD_MCFG_NEW_DTYPE__##e) | ||
272 | #define BFM_LCD_MCFG_NEW_DTYPE_V(v) BM_LCD_MCFG_NEW_DTYPE | ||
273 | #define BP_LCD_MCFG_NEW_CTYPE 1 | ||
274 | #define BM_LCD_MCFG_NEW_CTYPE 0x2 | ||
275 | #define BV_LCD_MCFG_NEW_CTYPE__SERIAL 0x1 | ||
276 | #define BV_LCD_MCFG_NEW_CTYPE__PARALLEL 0x0 | ||
277 | #define BF_LCD_MCFG_NEW_CTYPE(v) (((v) & 0x1) << 1) | ||
278 | #define BFM_LCD_MCFG_NEW_CTYPE(v) BM_LCD_MCFG_NEW_CTYPE | ||
279 | #define BF_LCD_MCFG_NEW_CTYPE_V(e) BF_LCD_MCFG_NEW_CTYPE(BV_LCD_MCFG_NEW_CTYPE__##e) | ||
280 | #define BFM_LCD_MCFG_NEW_CTYPE_V(v) BM_LCD_MCFG_NEW_CTYPE | ||
281 | #define BP_LCD_MCFG_NEW_FMT_CONV 0 | ||
282 | #define BM_LCD_MCFG_NEW_FMT_CONV 0x1 | ||
283 | #define BF_LCD_MCFG_NEW_FMT_CONV(v) (((v) & 0x1) << 0) | ||
284 | #define BFM_LCD_MCFG_NEW_FMT_CONV(v) BM_LCD_MCFG_NEW_FMT_CONV | ||
285 | #define BF_LCD_MCFG_NEW_FMT_CONV_V(e) BF_LCD_MCFG_NEW_FMT_CONV(BV_LCD_MCFG_NEW_FMT_CONV__##e) | ||
286 | #define BFM_LCD_MCFG_NEW_FMT_CONV_V(v) BM_LCD_MCFG_NEW_FMT_CONV | ||
287 | |||
288 | #define REG_LCD_MCTRL jz_reg(LCD_MCTRL) | ||
289 | #define JA_LCD_MCTRL (0xb3050000 + 0xa4) | ||
290 | #define JT_LCD_MCTRL JIO_32_RW | ||
291 | #define JN_LCD_MCTRL LCD_MCTRL | ||
292 | #define JI_LCD_MCTRL | ||
293 | #define BP_LCD_MCTRL_NARROW_TE 10 | ||
294 | #define BM_LCD_MCTRL_NARROW_TE 0x400 | ||
295 | #define BF_LCD_MCTRL_NARROW_TE(v) (((v) & 0x1) << 10) | ||
296 | #define BFM_LCD_MCTRL_NARROW_TE(v) BM_LCD_MCTRL_NARROW_TE | ||
297 | #define BF_LCD_MCTRL_NARROW_TE_V(e) BF_LCD_MCTRL_NARROW_TE(BV_LCD_MCTRL_NARROW_TE__##e) | ||
298 | #define BFM_LCD_MCTRL_NARROW_TE_V(v) BM_LCD_MCTRL_NARROW_TE | ||
299 | #define BP_LCD_MCTRL_TE_INV 9 | ||
300 | #define BM_LCD_MCTRL_TE_INV 0x200 | ||
301 | #define BF_LCD_MCTRL_TE_INV(v) (((v) & 0x1) << 9) | ||
302 | #define BFM_LCD_MCTRL_TE_INV(v) BM_LCD_MCTRL_TE_INV | ||
303 | #define BF_LCD_MCTRL_TE_INV_V(e) BF_LCD_MCTRL_TE_INV(BV_LCD_MCTRL_TE_INV__##e) | ||
304 | #define BFM_LCD_MCTRL_TE_INV_V(v) BM_LCD_MCTRL_TE_INV | ||
305 | #define BP_LCD_MCTRL_NOT_USE_TE 8 | ||
306 | #define BM_LCD_MCTRL_NOT_USE_TE 0x100 | ||
307 | #define BF_LCD_MCTRL_NOT_USE_TE(v) (((v) & 0x1) << 8) | ||
308 | #define BFM_LCD_MCTRL_NOT_USE_TE(v) BM_LCD_MCTRL_NOT_USE_TE | ||
309 | #define BF_LCD_MCTRL_NOT_USE_TE_V(e) BF_LCD_MCTRL_NOT_USE_TE(BV_LCD_MCTRL_NOT_USE_TE__##e) | ||
310 | #define BFM_LCD_MCTRL_NOT_USE_TE_V(v) BM_LCD_MCTRL_NOT_USE_TE | ||
311 | #define BP_LCD_MCTRL_DCSI_SEL 7 | ||
312 | #define BM_LCD_MCTRL_DCSI_SEL 0x80 | ||
313 | #define BF_LCD_MCTRL_DCSI_SEL(v) (((v) & 0x1) << 7) | ||
314 | #define BFM_LCD_MCTRL_DCSI_SEL(v) BM_LCD_MCTRL_DCSI_SEL | ||
315 | #define BF_LCD_MCTRL_DCSI_SEL_V(e) BF_LCD_MCTRL_DCSI_SEL(BV_LCD_MCTRL_DCSI_SEL__##e) | ||
316 | #define BFM_LCD_MCTRL_DCSI_SEL_V(v) BM_LCD_MCTRL_DCSI_SEL | ||
317 | #define BP_LCD_MCTRL_MIPI_SLCD 6 | ||
318 | #define BM_LCD_MCTRL_MIPI_SLCD 0x40 | ||
319 | #define BF_LCD_MCTRL_MIPI_SLCD(v) (((v) & 0x1) << 6) | ||
320 | #define BFM_LCD_MCTRL_MIPI_SLCD(v) BM_LCD_MCTRL_MIPI_SLCD | ||
321 | #define BF_LCD_MCTRL_MIPI_SLCD_V(e) BF_LCD_MCTRL_MIPI_SLCD(BV_LCD_MCTRL_MIPI_SLCD__##e) | ||
322 | #define BFM_LCD_MCTRL_MIPI_SLCD_V(v) BM_LCD_MCTRL_MIPI_SLCD | ||
323 | #define BP_LCD_MCTRL_FAST_MODE 4 | ||
324 | #define BM_LCD_MCTRL_FAST_MODE 0x10 | ||
325 | #define BF_LCD_MCTRL_FAST_MODE(v) (((v) & 0x1) << 4) | ||
326 | #define BFM_LCD_MCTRL_FAST_MODE(v) BM_LCD_MCTRL_FAST_MODE | ||
327 | #define BF_LCD_MCTRL_FAST_MODE_V(e) BF_LCD_MCTRL_FAST_MODE(BV_LCD_MCTRL_FAST_MODE__##e) | ||
328 | #define BFM_LCD_MCTRL_FAST_MODE_V(v) BM_LCD_MCTRL_FAST_MODE | ||
329 | #define BP_LCD_MCTRL_GATE_MASK 3 | ||
330 | #define BM_LCD_MCTRL_GATE_MASK 0x8 | ||
331 | #define BF_LCD_MCTRL_GATE_MASK(v) (((v) & 0x1) << 3) | ||
332 | #define BFM_LCD_MCTRL_GATE_MASK(v) BM_LCD_MCTRL_GATE_MASK | ||
333 | #define BF_LCD_MCTRL_GATE_MASK_V(e) BF_LCD_MCTRL_GATE_MASK(BV_LCD_MCTRL_GATE_MASK__##e) | ||
334 | #define BFM_LCD_MCTRL_GATE_MASK_V(v) BM_LCD_MCTRL_GATE_MASK | ||
335 | #define BP_LCD_MCTRL_DMA_MODE 2 | ||
336 | #define BM_LCD_MCTRL_DMA_MODE 0x4 | ||
337 | #define BF_LCD_MCTRL_DMA_MODE(v) (((v) & 0x1) << 2) | ||
338 | #define BFM_LCD_MCTRL_DMA_MODE(v) BM_LCD_MCTRL_DMA_MODE | ||
339 | #define BF_LCD_MCTRL_DMA_MODE_V(e) BF_LCD_MCTRL_DMA_MODE(BV_LCD_MCTRL_DMA_MODE__##e) | ||
340 | #define BFM_LCD_MCTRL_DMA_MODE_V(v) BM_LCD_MCTRL_DMA_MODE | ||
341 | #define BP_LCD_MCTRL_DMA_START 1 | ||
342 | #define BM_LCD_MCTRL_DMA_START 0x2 | ||
343 | #define BF_LCD_MCTRL_DMA_START(v) (((v) & 0x1) << 1) | ||
344 | #define BFM_LCD_MCTRL_DMA_START(v) BM_LCD_MCTRL_DMA_START | ||
345 | #define BF_LCD_MCTRL_DMA_START_V(e) BF_LCD_MCTRL_DMA_START(BV_LCD_MCTRL_DMA_START__##e) | ||
346 | #define BFM_LCD_MCTRL_DMA_START_V(v) BM_LCD_MCTRL_DMA_START | ||
347 | #define BP_LCD_MCTRL_DMA_TX_EN 0 | ||
348 | #define BM_LCD_MCTRL_DMA_TX_EN 0x1 | ||
349 | #define BF_LCD_MCTRL_DMA_TX_EN(v) (((v) & 0x1) << 0) | ||
350 | #define BFM_LCD_MCTRL_DMA_TX_EN(v) BM_LCD_MCTRL_DMA_TX_EN | ||
351 | #define BF_LCD_MCTRL_DMA_TX_EN_V(e) BF_LCD_MCTRL_DMA_TX_EN(BV_LCD_MCTRL_DMA_TX_EN__##e) | ||
352 | #define BFM_LCD_MCTRL_DMA_TX_EN_V(v) BM_LCD_MCTRL_DMA_TX_EN | ||
353 | |||
354 | #define REG_LCD_MSTATE jz_reg(LCD_MSTATE) | ||
355 | #define JA_LCD_MSTATE (0xb3050000 + 0xa8) | ||
356 | #define JT_LCD_MSTATE JIO_32_RW | ||
357 | #define JN_LCD_MSTATE LCD_MSTATE | ||
358 | #define JI_LCD_MSTATE | ||
359 | #define BP_LCD_MSTATE_LCD_ID 16 | ||
360 | #define BM_LCD_MSTATE_LCD_ID 0xffff0000 | ||
361 | #define BF_LCD_MSTATE_LCD_ID(v) (((v) & 0xffff) << 16) | ||
362 | #define BFM_LCD_MSTATE_LCD_ID(v) BM_LCD_MSTATE_LCD_ID | ||
363 | #define BF_LCD_MSTATE_LCD_ID_V(e) BF_LCD_MSTATE_LCD_ID(BV_LCD_MSTATE_LCD_ID__##e) | ||
364 | #define BFM_LCD_MSTATE_LCD_ID_V(v) BM_LCD_MSTATE_LCD_ID | ||
365 | #define BP_LCD_MSTATE_BUSY 0 | ||
366 | #define BM_LCD_MSTATE_BUSY 0x1 | ||
367 | #define BF_LCD_MSTATE_BUSY(v) (((v) & 0x1) << 0) | ||
368 | #define BFM_LCD_MSTATE_BUSY(v) BM_LCD_MSTATE_BUSY | ||
369 | #define BF_LCD_MSTATE_BUSY_V(e) BF_LCD_MSTATE_BUSY(BV_LCD_MSTATE_BUSY__##e) | ||
370 | #define BFM_LCD_MSTATE_BUSY_V(v) BM_LCD_MSTATE_BUSY | ||
371 | |||
372 | #define REG_LCD_MDATA jz_reg(LCD_MDATA) | ||
373 | #define JA_LCD_MDATA (0xb3050000 + 0xac) | ||
374 | #define JT_LCD_MDATA JIO_32_RW | ||
375 | #define JN_LCD_MDATA LCD_MDATA | ||
376 | #define JI_LCD_MDATA | ||
377 | #define BP_LCD_MDATA_TYPE 30 | ||
378 | #define BM_LCD_MDATA_TYPE 0xc0000000 | ||
379 | #define BV_LCD_MDATA_TYPE__CMD 0x1 | ||
380 | #define BV_LCD_MDATA_TYPE__DAT 0x0 | ||
381 | #define BF_LCD_MDATA_TYPE(v) (((v) & 0x3) << 30) | ||
382 | #define BFM_LCD_MDATA_TYPE(v) BM_LCD_MDATA_TYPE | ||
383 | #define BF_LCD_MDATA_TYPE_V(e) BF_LCD_MDATA_TYPE(BV_LCD_MDATA_TYPE__##e) | ||
384 | #define BFM_LCD_MDATA_TYPE_V(v) BM_LCD_MDATA_TYPE | ||
385 | #define BP_LCD_MDATA_DATA 0 | ||
386 | #define BM_LCD_MDATA_DATA 0xffffff | ||
387 | #define BF_LCD_MDATA_DATA(v) (((v) & 0xffffff) << 0) | ||
388 | #define BFM_LCD_MDATA_DATA(v) BM_LCD_MDATA_DATA | ||
389 | #define BF_LCD_MDATA_DATA_V(e) BF_LCD_MDATA_DATA(BV_LCD_MDATA_DATA__##e) | ||
390 | #define BFM_LCD_MDATA_DATA_V(v) BM_LCD_MDATA_DATA | ||
391 | |||
392 | #define REG_LCD_WTIME jz_reg(LCD_WTIME) | ||
393 | #define JA_LCD_WTIME (0xb3050000 + 0xb0) | ||
394 | #define JT_LCD_WTIME JIO_32_RW | ||
395 | #define JN_LCD_WTIME LCD_WTIME | ||
396 | #define JI_LCD_WTIME | ||
397 | #define BP_LCD_WTIME_DHTIME 24 | ||
398 | #define BM_LCD_WTIME_DHTIME 0xff000000 | ||
399 | #define BF_LCD_WTIME_DHTIME(v) (((v) & 0xff) << 24) | ||
400 | #define BFM_LCD_WTIME_DHTIME(v) BM_LCD_WTIME_DHTIME | ||
401 | #define BF_LCD_WTIME_DHTIME_V(e) BF_LCD_WTIME_DHTIME(BV_LCD_WTIME_DHTIME__##e) | ||
402 | #define BFM_LCD_WTIME_DHTIME_V(v) BM_LCD_WTIME_DHTIME | ||
403 | #define BP_LCD_WTIME_DLTIME 16 | ||
404 | #define BM_LCD_WTIME_DLTIME 0xff0000 | ||
405 | #define BF_LCD_WTIME_DLTIME(v) (((v) & 0xff) << 16) | ||
406 | #define BFM_LCD_WTIME_DLTIME(v) BM_LCD_WTIME_DLTIME | ||
407 | #define BF_LCD_WTIME_DLTIME_V(e) BF_LCD_WTIME_DLTIME(BV_LCD_WTIME_DLTIME__##e) | ||
408 | #define BFM_LCD_WTIME_DLTIME_V(v) BM_LCD_WTIME_DLTIME | ||
409 | #define BP_LCD_WTIME_CHTIME 8 | ||
410 | #define BM_LCD_WTIME_CHTIME 0xff00 | ||
411 | #define BF_LCD_WTIME_CHTIME(v) (((v) & 0xff) << 8) | ||
412 | #define BFM_LCD_WTIME_CHTIME(v) BM_LCD_WTIME_CHTIME | ||
413 | #define BF_LCD_WTIME_CHTIME_V(e) BF_LCD_WTIME_CHTIME(BV_LCD_WTIME_CHTIME__##e) | ||
414 | #define BFM_LCD_WTIME_CHTIME_V(v) BM_LCD_WTIME_CHTIME | ||
415 | #define BP_LCD_WTIME_CLTIME 0 | ||
416 | #define BM_LCD_WTIME_CLTIME 0xff | ||
417 | #define BF_LCD_WTIME_CLTIME(v) (((v) & 0xff) << 0) | ||
418 | #define BFM_LCD_WTIME_CLTIME(v) BM_LCD_WTIME_CLTIME | ||
419 | #define BF_LCD_WTIME_CLTIME_V(e) BF_LCD_WTIME_CLTIME(BV_LCD_WTIME_CLTIME__##e) | ||
420 | #define BFM_LCD_WTIME_CLTIME_V(v) BM_LCD_WTIME_CLTIME | ||
421 | |||
422 | #define REG_LCD_TASH jz_reg(LCD_TASH) | ||
423 | #define JA_LCD_TASH (0xb3050000 + 0xb4) | ||
424 | #define JT_LCD_TASH JIO_32_RW | ||
425 | #define JN_LCD_TASH LCD_TASH | ||
426 | #define JI_LCD_TASH | ||
427 | #define BP_LCD_TASH_TAH 8 | ||
428 | #define BM_LCD_TASH_TAH 0xff00 | ||
429 | #define BF_LCD_TASH_TAH(v) (((v) & 0xff) << 8) | ||
430 | #define BFM_LCD_TASH_TAH(v) BM_LCD_TASH_TAH | ||
431 | #define BF_LCD_TASH_TAH_V(e) BF_LCD_TASH_TAH(BV_LCD_TASH_TAH__##e) | ||
432 | #define BFM_LCD_TASH_TAH_V(v) BM_LCD_TASH_TAH | ||
433 | #define BP_LCD_TASH_TAS 0 | ||
434 | #define BM_LCD_TASH_TAS 0xff | ||
435 | #define BF_LCD_TASH_TAS(v) (((v) & 0xff) << 0) | ||
436 | #define BFM_LCD_TASH_TAS(v) BM_LCD_TASH_TAS | ||
437 | #define BF_LCD_TASH_TAS_V(e) BF_LCD_TASH_TAS(BV_LCD_TASH_TAS__##e) | ||
438 | #define BFM_LCD_TASH_TAS_V(v) BM_LCD_TASH_TAS | ||
439 | |||
440 | #define REG_LCD_SMWT jz_reg(LCD_SMWT) | ||
441 | #define JA_LCD_SMWT (0xb3050000 + 0xbc) | ||
442 | #define JT_LCD_SMWT JIO_32_RW | ||
443 | #define JN_LCD_SMWT LCD_SMWT | ||
444 | #define JI_LCD_SMWT | ||
445 | |||
446 | #endif /* __HEADERGEN_LCD_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/macro.h b/firmware/target/mips/ingenic_x1000/x1000/macro.h new file mode 100644 index 0000000000..bfe8708a91 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/macro.h | |||
@@ -0,0 +1,356 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * | ||
11 | * Copyright (C) 2015 by the authors | ||
12 | * | ||
13 | * This program is free software; you can redistribute it and/or | ||
14 | * modify it under the terms of the GNU General Public License | ||
15 | * as published by the Free Software Foundation; either version 2 | ||
16 | * of the License, or (at your option) any later version. | ||
17 | * | ||
18 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
19 | * KIND, either express or implied. | ||
20 | * | ||
21 | ****************************************************************************/ | ||
22 | #ifndef __HEADERGEN_MACRO_H__ | ||
23 | #define __HEADERGEN_MACRO_H__ | ||
24 | |||
25 | #include <stdint.h> | ||
26 | |||
27 | #define __VAR_OR1(prefix, suffix) \ | ||
28 | (prefix##suffix) | ||
29 | #define __VAR_OR2(pre, s1, s2) \ | ||
30 | (__VAR_OR1(pre, s1) | __VAR_OR1(pre, s2)) | ||
31 | #define __VAR_OR3(pre, s1, s2, s3) \ | ||
32 | (__VAR_OR1(pre, s1) | __VAR_OR2(pre, s2, s3)) | ||
33 | #define __VAR_OR4(pre, s1, s2, s3, s4) \ | ||
34 | (__VAR_OR2(pre, s1, s2) | __VAR_OR2(pre, s3, s4)) | ||
35 | #define __VAR_OR5(pre, s1, s2, s3, s4, s5) \ | ||
36 | (__VAR_OR2(pre, s1, s2) | __VAR_OR3(pre, s3, s4, s5)) | ||
37 | #define __VAR_OR6(pre, s1, s2, s3, s4, s5, s6) \ | ||
38 | (__VAR_OR3(pre, s1, s2, s3) | __VAR_OR3(pre, s4, s5, s6)) | ||
39 | #define __VAR_OR7(pre, s1, s2, s3, s4, s5, s6, s7) \ | ||
40 | (__VAR_OR3(pre, s1, s2, s3) | __VAR_OR4(pre, s4, s5, s6, s7)) | ||
41 | #define __VAR_OR8(pre, s1, s2, s3, s4, s5, s6, s7, s8) \ | ||
42 | (__VAR_OR4(pre, s1, s2, s3, s4) | __VAR_OR4(pre, s5, s6, s7, s8)) | ||
43 | #define __VAR_OR9(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9) \ | ||
44 | (__VAR_OR4(pre, s1, s2, s3, s4) | __VAR_OR5(pre, s5, s6, s7, s8, s9)) | ||
45 | #define __VAR_OR10(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10) \ | ||
46 | (__VAR_OR5(pre, s1, s2, s3, s4, s5) | __VAR_OR5(pre, s6, s7, s8, s9, s10)) | ||
47 | #define __VAR_OR11(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11) \ | ||
48 | (__VAR_OR5(pre, s1, s2, s3, s4, s5) | __VAR_OR6(pre, s6, s7, s8, s9, s10, s11)) | ||
49 | #define __VAR_OR12(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12) \ | ||
50 | (__VAR_OR6(pre, s1, s2, s3, s4, s5, s6) | __VAR_OR6(pre, s7, s8, s9, s10, s11, s12)) | ||
51 | #define __VAR_OR13(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13) \ | ||
52 | (__VAR_OR6(pre, s1, s2, s3, s4, s5, s6) | __VAR_OR7(pre, s7, s8, s9, s10, s11, s12, s13)) | ||
53 | |||
54 | #define __VAR_NARGS(...) __VAR_NARGS_(__VA_ARGS__, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1) | ||
55 | #define __VAR_NARGS_(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, N, ...) N | ||
56 | |||
57 | #define __VAR_EXPAND(macro, prefix, ...) __VAR_EXPAND_(macro, __VAR_NARGS(__VA_ARGS__), prefix, __VA_ARGS__) | ||
58 | #define __VAR_EXPAND_(macro, cnt, prefix, ...) __VAR_EXPAND__(macro, cnt, prefix, __VA_ARGS__) | ||
59 | #define __VAR_EXPAND__(macro, cnt, prefix, ...) __VAR_EXPAND___(macro##cnt, prefix, __VA_ARGS__) | ||
60 | #define __VAR_EXPAND___(macro, prefix, ...) macro(prefix, __VA_ARGS__) | ||
61 | |||
62 | #define JIO_8_RO(op, name, ...) JIO_8_RO_##op(name, __VA_ARGS__) | ||
63 | #define JIO_8_RO_RD(name, ...) (*(const volatile uint8_t *)(JA_##name)) | ||
64 | #define JIO_8_RO_WR(name, val) _Static_assert(0, #name " is read-only") | ||
65 | #define JIO_8_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only") | ||
66 | #define JIO_8_RO_VAR(name, ...) (*(const volatile uint8_t *)(JA_##name)) | ||
67 | |||
68 | #define JIO_16_RO(op, name, ...) JIO_16_RO_##op(name, __VA_ARGS__) | ||
69 | #define JIO_16_RO_RD(name, ...) (*(const volatile uint16_t *)(JA_##name)) | ||
70 | #define JIO_16_RO_WR(name, val) _Static_assert(0, #name " is read-only") | ||
71 | #define JIO_16_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only") | ||
72 | #define JIO_16_RO_VAR(name, ...) (*(const volatile uint16_t *)(JA_##name)) | ||
73 | |||
74 | #define JIO_32_RO(op, name, ...) JIO_32_RO_##op(name, __VA_ARGS__) | ||
75 | #define JIO_32_RO_RD(name, ...) (*(const volatile uint32_t *)(JA_##name)) | ||
76 | #define JIO_32_RO_WR(name, val) _Static_assert(0, #name " is read-only") | ||
77 | #define JIO_32_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only") | ||
78 | #define JIO_32_RO_VAR(name, ...) (*(const volatile uint32_t *)(JA_##name)) | ||
79 | |||
80 | #define JIO_8_RW(op, name, ...) JIO_8_RW_##op(name, __VA_ARGS__) | ||
81 | #define JIO_8_RW_RD(name, ...) (*(volatile uint8_t *)(JA_##name)) | ||
82 | #define JIO_8_RW_WR(name, val) (*(volatile uint8_t *)(JA_##name)) = (val) | ||
83 | #define JIO_8_RW_RMW(name, vand, vor) JIO_8_RW_WR(name, (JIO_8_RW_RD(name) & (vand)) | (vor)) | ||
84 | #define JIO_8_RW_VAR(name, ...) (*(volatile uint8_t *)(JA_##name)) | ||
85 | |||
86 | #define JIO_16_RW(op, name, ...) JIO_16_RW_##op(name, __VA_ARGS__) | ||
87 | #define JIO_16_RW_RD(name, ...) (*(volatile uint16_t *)(JA_##name)) | ||
88 | #define JIO_16_RW_WR(name, val) (*(volatile uint16_t *)(JA_##name)) = (val) | ||
89 | #define JIO_16_RW_RMW(name, vand, vor) JIO_16_RW_WR(name, (JIO_16_RW_RD(name) & (vand)) | (vor)) | ||
90 | #define JIO_16_RW_VAR(name, ...) (*(volatile uint16_t *)(JA_##name)) | ||
91 | |||
92 | #define JIO_32_RW(op, name, ...) JIO_32_RW_##op(name, __VA_ARGS__) | ||
93 | #define JIO_32_RW_RD(name, ...) (*(volatile uint32_t *)(JA_##name)) | ||
94 | #define JIO_32_RW_WR(name, val) (*(volatile uint32_t *)(JA_##name)) = (val) | ||
95 | #define JIO_32_RW_RMW(name, vand, vor) JIO_32_RW_WR(name, (JIO_32_RW_RD(name) & (vand)) | (vor)) | ||
96 | #define JIO_32_RW_VAR(name, ...) (*(volatile uint32_t *)(JA_##name)) | ||
97 | |||
98 | #define JIO_8_WO(op, name, ...) JIO_8_WO_##op(name, __VA_ARGS__) | ||
99 | #define JIO_8_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;}) | ||
100 | #define JIO_8_WO_WR(name, val) (*(volatile uint8_t *)(JA_##name)) = (val) | ||
101 | #define JIO_8_WO_RMW(name, vand, vor) JIO_8_WO_WR(name, vor) | ||
102 | #define JIO_8_WO_VAR(name, ...) (*(volatile uint8_t *)(JA_##name)) | ||
103 | |||
104 | #define JIO_16_WO(op, name, ...) JIO_16_WO_##op(name, __VA_ARGS__) | ||
105 | #define JIO_16_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;}) | ||
106 | #define JIO_16_WO_WR(name, val) (*(volatile uint16_t *)(JA_##name)) = (val) | ||
107 | #define JIO_16_WO_RMW(name, vand, vor) JIO_16_WO_WR(name, vor) | ||
108 | #define JIO_16_WO_VAR(name, ...) (*(volatile uint16_t *)(JA_##name)) | ||
109 | |||
110 | #define JIO_32_WO(op, name, ...) JIO_32_WO_##op(name, __VA_ARGS__) | ||
111 | #define JIO_32_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;}) | ||
112 | #define JIO_32_WO_WR(name, val) (*(volatile uint32_t *)(JA_##name)) = (val) | ||
113 | #define JIO_32_WO_RMW(name, vand, vor) JIO_32_WO_WR(name, vor) | ||
114 | #define JIO_32_WO_VAR(name, ...) (*(volatile uint32_t *)(JA_##name)) | ||
115 | |||
116 | |||
117 | /** __jz_variant | ||
118 | * | ||
119 | * usage: __jz_variant(register, variant_prefix, variant_postfix) | ||
120 | * | ||
121 | * effect: expands to register variant given as argument | ||
122 | * note: internal usage | ||
123 | * note: register must be fully qualified if indexed | ||
124 | * | ||
125 | * example: __jz_variant(ICOLL_CTRL, , _SET) | ||
126 | * example: __jz_variant(ICOLL_ENABLE(3), , _CLR) | ||
127 | */ | ||
128 | #define __jz_variant(name, varp, vars) __jz_variant_(JN_##name, JI_##name, varp, vars) | ||
129 | #define __jz_variant_(...) __jz_variant__(__VA_ARGS__) | ||
130 | #define __jz_variant__(name, index, varp, vars) varp##name##vars index | ||
131 | |||
132 | /** jz_orf | ||
133 | * | ||
134 | * usage: jz_orf(register, f1(v1), f2(v2), ...) | ||
135 | * | ||
136 | * effect: expands to the register value where each field fi has value vi. | ||
137 | * Informally: reg_f1(v1) | reg_f2(v2) | ... | ||
138 | * note: enumerated values for fields can be obtained by using the syntax: | ||
139 | * f1_V(name) | ||
140 | * | ||
141 | * example: jz_orf(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED)) | ||
142 | */ | ||
143 | #define jz_orf(reg, ...) __VAR_EXPAND(__VAR_OR, BF_##reg##_, __VA_ARGS__) | ||
144 | |||
145 | /** __jz_orfm | ||
146 | * | ||
147 | * usage: __jz_orfm(register, f1(v1), f2(v2), ...) | ||
148 | * | ||
149 | * effect: expands to the register value where each field fi has maximum value (vi is ignored). | ||
150 | * note: internal usage | ||
151 | * | ||
152 | * example: __jz_orfm(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED)) | ||
153 | */ | ||
154 | #define __jz_orfm(reg, ...) __VAR_EXPAND(__VAR_OR, BFM_##reg##_, __VA_ARGS__) | ||
155 | |||
156 | /** jz_orm | ||
157 | * | ||
158 | * usage: jz_orm(register, f1, f2, ...) | ||
159 | * | ||
160 | * effect: expands to the register value where each field fi is set to its maximum value. | ||
161 | * Informally: reg_f1_mask | reg_f2_mask | ... | ||
162 | * | ||
163 | * example: jz_orm(ICOLL_CTRL, SFTRST, CLKGATE) | ||
164 | */ | ||
165 | #define jz_orm(reg, ...) __VAR_EXPAND(__VAR_OR, BM_##reg##_, __VA_ARGS__) | ||
166 | |||
167 | |||
168 | /** jz_read | ||
169 | * | ||
170 | * usage: jz_read(register) | ||
171 | * | ||
172 | * effect: read a register and return its value | ||
173 | * note: register must be fully qualified if indexed | ||
174 | * | ||
175 | * example: jz_read(ICOLL_STATUS) | ||
176 | * jz_read(ICOLL_ENABLE(42)) | ||
177 | */ | ||
178 | #define jz_read(name) JT_##name(RD, name) | ||
179 | |||
180 | /** jz_vreadf | ||
181 | * | ||
182 | * usage: jz_vreadf(value, register, field) | ||
183 | * | ||
184 | * effect: given a register value, return the value of a particular field | ||
185 | * note: this macro does NOT read any register | ||
186 | * | ||
187 | * example: jz_vreadf(0xc0000000, ICOLL_CTRL, SFTRST) | ||
188 | * jz_vreadf(0x46ff, ICOLL_ENABLE, CPU0_PRIO) | ||
189 | */ | ||
190 | #define jz_vreadf(val, name, field) (((val) & BM_##name##_##field) >> BP_##name##_##field) | ||
191 | |||
192 | /** jz_readf | ||
193 | * | ||
194 | * usage: jz_readf(register, field) | ||
195 | * | ||
196 | * effect: read a register and return the value of a particular field | ||
197 | * note: register must be fully qualified if indexed | ||
198 | * | ||
199 | * example: jz_readf(ICOLL_CTRL, SFTRST) | ||
200 | * jz_readf(ICOLL_ENABLE(3), CPU0_PRIO) | ||
201 | */ | ||
202 | #define jz_readf(name, field) jz_readf_(jz_read(name), JN_##name, field) | ||
203 | #define jz_readf_(...) jz_vreadf(__VA_ARGS__) | ||
204 | |||
205 | /** jz_write | ||
206 | * | ||
207 | * usage: jz_write(register, value) | ||
208 | * | ||
209 | * effect: write a register | ||
210 | * note: register must be fully qualified if indexed | ||
211 | * | ||
212 | * example: jz_write(ICOLL_CTRL, 0x42) | ||
213 | * jz_write(ICOLL_ENABLE_SET(3), 0x37) | ||
214 | */ | ||
215 | #define jz_write(name, val) JT_##name(WR, name, val) | ||
216 | |||
217 | /** jz_writef | ||
218 | * | ||
219 | * usage: jz_writef(register, f1(v1), f2(v2), ...) | ||
220 | * | ||
221 | * effect: change the register value so that field fi has value vi | ||
222 | * note: register must be fully qualified if indexed | ||
223 | * note: this macro may perform a read-modify-write | ||
224 | * | ||
225 | * example: jz_writef(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED)) | ||
226 | * jz_writef(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ)) | ||
227 | */ | ||
228 | #define jz_writef(name, ...) jz_writef_(name, JN_##name, __VA_ARGS__) | ||
229 | #define jz_writef_(name, name2, ...) JT_##name(RMW, name, ~__jz_orfm(name2, __VA_ARGS__), jz_orf(name2, __VA_ARGS__)) | ||
230 | |||
231 | /** jz_overwritef | ||
232 | * | ||
233 | * usage: jz_overwritef(register, f1(v1), f2(v2), ...) | ||
234 | * | ||
235 | * effect: change the register value so that field fi has value vi and other fields have value zero | ||
236 | * thus this macro is equivalent to: | ||
237 | * jz_write(register, jz_orf(register, f1(v1), ...)) | ||
238 | * note: register must be fully qualified if indexed | ||
239 | * note: this macro will overwrite the register (it is NOT a read-modify-write) | ||
240 | * | ||
241 | * example: jz_overwritef(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED)) | ||
242 | * jz_overwritef(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ)) | ||
243 | */ | ||
244 | #define jz_overwritef(name, ...) jz_overwritef_(name, JN_##name, __VA_ARGS__) | ||
245 | #define jz_overwritef_(name, name2, ...) JT_##name(WR, name, jz_orf(name2, __VA_ARGS__)) | ||
246 | |||
247 | /** jz_vwritef | ||
248 | * | ||
249 | * usage: jz_vwritef(var, register, f1(v1), f2(v2), ...) | ||
250 | * | ||
251 | * effect: change the variable value so that field fi has value vi | ||
252 | * note: this macro will perform a read-modify-write | ||
253 | * | ||
254 | * example: jz_vwritef(var, ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED)) | ||
255 | * jz_vwritef(var, ICOLL_ENABLE, CPU0_PRIO(1), CPU0_TYPE_V(FIQ)) | ||
256 | */ | ||
257 | #define jz_vwritef(var, name, ...) (var) = jz_orf(name, __VA_ARGS__) | (~__jz_orfm(name, __VA_ARGS__) & (var)) | ||
258 | |||
259 | /** jz_setf | ||
260 | * | ||
261 | * usage: jz_setf(register, f1, f2, ...) | ||
262 | * | ||
263 | * effect: change the register value so that field fi has maximum value | ||
264 | * IMPORTANT: this macro performs a write to the set variant of the register | ||
265 | * note: register must be fully qualified if indexed | ||
266 | * | ||
267 | * example: jz_setf(ICOLL_CTRL, SFTRST, CLKGATE) | ||
268 | * jz_setf(ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE) | ||
269 | */ | ||
270 | #define jz_setf(name, ...) jz_setf_(__jz_variant(name, , _SET), JN_##name, __VA_ARGS__) | ||
271 | #define jz_setf_(name, name2, ...) jz_write(name, jz_orm(name2, __VA_ARGS__)) | ||
272 | |||
273 | /** jz_clrf | ||
274 | * | ||
275 | * usage: jz_clrf(register, f1, f2, ...) | ||
276 | * | ||
277 | * effect: change the register value so that field fi has value zero | ||
278 | * IMPORTANT: this macro performs a write to the clr variant of the register | ||
279 | * note: register must be fully qualified if indexed | ||
280 | * | ||
281 | * example: jz_clrf(ICOLL_CTRL, SFTRST, CLKGATE) | ||
282 | * jz_clrf(ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE) | ||
283 | */ | ||
284 | #define jz_clrf(name, ...) jz_clrf_(__jz_variant(name, , _CLR), JN_##name, __VA_ARGS__) | ||
285 | #define jz_clrf_(name, name2, ...) jz_write(name, jz_orm(name2, __VA_ARGS__)) | ||
286 | |||
287 | /** jz_set | ||
288 | * | ||
289 | * usage: jz_set(register, set_value) | ||
290 | * | ||
291 | * effect: set some bits using set variant | ||
292 | * note: register must be fully qualified if indexed | ||
293 | * | ||
294 | * example: jz_set(ICOLL_CTRL, 0x42) | ||
295 | * jz_set(ICOLL_ENABLE(3), 0x37) | ||
296 | */ | ||
297 | #define jz_set(name, sval) jz_set_(__jz_variant(name, , _SET), sval) | ||
298 | #define jz_set_(sname, sval) jz_write(sname, sval) | ||
299 | |||
300 | /** jz_clr | ||
301 | * | ||
302 | * usage: jz_clr(register, clr_value) | ||
303 | * | ||
304 | * effect: clear some bits using clr variant | ||
305 | * note: register must be fully qualified if indexed | ||
306 | * | ||
307 | * example: jz_clr(ICOLL_CTRL, 0x42) | ||
308 | * jz_clr(ICOLL_ENABLE(3), 0x37) | ||
309 | */ | ||
310 | #define jz_clr(name, cval) jz_clr_(__jz_variant(name, , _CLR), cval) | ||
311 | #define jz_clr_(cname, cval) jz_write(cname, cval) | ||
312 | |||
313 | /** jz_cs | ||
314 | * | ||
315 | * usage: jz_cs(register, clear_value, set_value) | ||
316 | * | ||
317 | * effect: clear some bits using clr variant and then set some using set variant | ||
318 | * note: register must be fully qualified if indexed | ||
319 | * | ||
320 | * example: jz_cs(ICOLL_CTRL, 0xff, 0x42) | ||
321 | * jz_cs(ICOLL_ENABLE(3), 0xff, 0x37) | ||
322 | */ | ||
323 | #define jz_cs(name, cval, sval) jz_cs_(__jz_variant(name, , _CLR), __jz_variant(name, , _SET), cval, sval) | ||
324 | #define jz_cs_(cname, sname, cval, sval) do { jz_write(cname, cval); jz_write(sname, sval); } while(0) | ||
325 | |||
326 | /** jz_csf | ||
327 | * | ||
328 | * usage: jz_csf(register, f1(v1), f2(v2), ...) | ||
329 | * | ||
330 | * effect: change the register value so that field fi has value vi using clr and set variants | ||
331 | * note: register must be fully qualified if indexed | ||
332 | * note: this macro will NOT perform a read-modify-write and is thus safer | ||
333 | * IMPORTANT: this macro will set some fields to 0 temporarily, make sure this is acceptable | ||
334 | * | ||
335 | * example: jz_csf(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED)) | ||
336 | * jz_csf(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ)) | ||
337 | */ | ||
338 | #define jz_csf(name, ...) jz_csf_(name, JN_##name, __VA_ARGS__) | ||
339 | #define jz_csf_(name, name2, ...) jz_cs(name, __jz_orfm(name2, __VA_ARGS__), jz_orf(name2, __VA_ARGS__)) | ||
340 | |||
341 | /** jz_reg | ||
342 | * | ||
343 | * usage: jz_reg(register) | ||
344 | * | ||
345 | * effect: return a variable-like expression that can be read/written | ||
346 | * note: register must be fully qualified if indexed | ||
347 | * note: read-only registers will yield a constant expression | ||
348 | * | ||
349 | * example: unsigned x = jz_reg(ICOLL_STATUS) | ||
350 | * unsigned x = jz_reg(ICOLL_ENABLE(42)) | ||
351 | * jz_reg(ICOLL_ENABLE(42)) = 64 | ||
352 | */ | ||
353 | #define jz_reg(name) JT_##name(VAR, name) | ||
354 | |||
355 | |||
356 | #endif /* __HEADERGEN_MACRO_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/msc.h b/firmware/target/mips/ingenic_x1000/x1000/msc.h new file mode 100644 index 0000000000..762b4b1461 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/msc.h | |||
@@ -0,0 +1,824 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_MSC_H__ | ||
25 | #define __HEADERGEN_MSC_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_MSC_CTRL(_n1) jz_reg(MSC_CTRL(_n1)) | ||
30 | #define JA_MSC_CTRL(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x0) | ||
31 | #define JT_MSC_CTRL(_n1) JIO_32_RW | ||
32 | #define JN_MSC_CTRL(_n1) MSC_CTRL | ||
33 | #define JI_MSC_CTRL(_n1) (_n1) | ||
34 | #define BP_MSC_CTRL_CLOCK 0 | ||
35 | #define BM_MSC_CTRL_CLOCK 0x3 | ||
36 | #define BV_MSC_CTRL_CLOCK__DO_NOTHING 0x0 | ||
37 | #define BV_MSC_CTRL_CLOCK__STOP 0x1 | ||
38 | #define BV_MSC_CTRL_CLOCK__START 0x2 | ||
39 | #define BF_MSC_CTRL_CLOCK(v) (((v) & 0x3) << 0) | ||
40 | #define BFM_MSC_CTRL_CLOCK(v) BM_MSC_CTRL_CLOCK | ||
41 | #define BF_MSC_CTRL_CLOCK_V(e) BF_MSC_CTRL_CLOCK(BV_MSC_CTRL_CLOCK__##e) | ||
42 | #define BFM_MSC_CTRL_CLOCK_V(v) BM_MSC_CTRL_CLOCK | ||
43 | #define BP_MSC_CTRL_SEND_CCSD 15 | ||
44 | #define BM_MSC_CTRL_SEND_CCSD 0x8000 | ||
45 | #define BF_MSC_CTRL_SEND_CCSD(v) (((v) & 0x1) << 15) | ||
46 | #define BFM_MSC_CTRL_SEND_CCSD(v) BM_MSC_CTRL_SEND_CCSD | ||
47 | #define BF_MSC_CTRL_SEND_CCSD_V(e) BF_MSC_CTRL_SEND_CCSD(BV_MSC_CTRL_SEND_CCSD__##e) | ||
48 | #define BFM_MSC_CTRL_SEND_CCSD_V(v) BM_MSC_CTRL_SEND_CCSD | ||
49 | #define BP_MSC_CTRL_SEND_AS_CCSD 14 | ||
50 | #define BM_MSC_CTRL_SEND_AS_CCSD 0x4000 | ||
51 | #define BF_MSC_CTRL_SEND_AS_CCSD(v) (((v) & 0x1) << 14) | ||
52 | #define BFM_MSC_CTRL_SEND_AS_CCSD(v) BM_MSC_CTRL_SEND_AS_CCSD | ||
53 | #define BF_MSC_CTRL_SEND_AS_CCSD_V(e) BF_MSC_CTRL_SEND_AS_CCSD(BV_MSC_CTRL_SEND_AS_CCSD__##e) | ||
54 | #define BFM_MSC_CTRL_SEND_AS_CCSD_V(v) BM_MSC_CTRL_SEND_AS_CCSD | ||
55 | #define BP_MSC_CTRL_EXIT_MULTIPLE 7 | ||
56 | #define BM_MSC_CTRL_EXIT_MULTIPLE 0x80 | ||
57 | #define BF_MSC_CTRL_EXIT_MULTIPLE(v) (((v) & 0x1) << 7) | ||
58 | #define BFM_MSC_CTRL_EXIT_MULTIPLE(v) BM_MSC_CTRL_EXIT_MULTIPLE | ||
59 | #define BF_MSC_CTRL_EXIT_MULTIPLE_V(e) BF_MSC_CTRL_EXIT_MULTIPLE(BV_MSC_CTRL_EXIT_MULTIPLE__##e) | ||
60 | #define BFM_MSC_CTRL_EXIT_MULTIPLE_V(v) BM_MSC_CTRL_EXIT_MULTIPLE | ||
61 | #define BP_MSC_CTRL_EXIT_TRANSFER 6 | ||
62 | #define BM_MSC_CTRL_EXIT_TRANSFER 0x40 | ||
63 | #define BF_MSC_CTRL_EXIT_TRANSFER(v) (((v) & 0x1) << 6) | ||
64 | #define BFM_MSC_CTRL_EXIT_TRANSFER(v) BM_MSC_CTRL_EXIT_TRANSFER | ||
65 | #define BF_MSC_CTRL_EXIT_TRANSFER_V(e) BF_MSC_CTRL_EXIT_TRANSFER(BV_MSC_CTRL_EXIT_TRANSFER__##e) | ||
66 | #define BFM_MSC_CTRL_EXIT_TRANSFER_V(v) BM_MSC_CTRL_EXIT_TRANSFER | ||
67 | #define BP_MSC_CTRL_START_READ_WAIT 5 | ||
68 | #define BM_MSC_CTRL_START_READ_WAIT 0x20 | ||
69 | #define BF_MSC_CTRL_START_READ_WAIT(v) (((v) & 0x1) << 5) | ||
70 | #define BFM_MSC_CTRL_START_READ_WAIT(v) BM_MSC_CTRL_START_READ_WAIT | ||
71 | #define BF_MSC_CTRL_START_READ_WAIT_V(e) BF_MSC_CTRL_START_READ_WAIT(BV_MSC_CTRL_START_READ_WAIT__##e) | ||
72 | #define BFM_MSC_CTRL_START_READ_WAIT_V(v) BM_MSC_CTRL_START_READ_WAIT | ||
73 | #define BP_MSC_CTRL_STOP_READ_WAIT 4 | ||
74 | #define BM_MSC_CTRL_STOP_READ_WAIT 0x10 | ||
75 | #define BF_MSC_CTRL_STOP_READ_WAIT(v) (((v) & 0x1) << 4) | ||
76 | #define BFM_MSC_CTRL_STOP_READ_WAIT(v) BM_MSC_CTRL_STOP_READ_WAIT | ||
77 | #define BF_MSC_CTRL_STOP_READ_WAIT_V(e) BF_MSC_CTRL_STOP_READ_WAIT(BV_MSC_CTRL_STOP_READ_WAIT__##e) | ||
78 | #define BFM_MSC_CTRL_STOP_READ_WAIT_V(v) BM_MSC_CTRL_STOP_READ_WAIT | ||
79 | #define BP_MSC_CTRL_RESET 3 | ||
80 | #define BM_MSC_CTRL_RESET 0x8 | ||
81 | #define BF_MSC_CTRL_RESET(v) (((v) & 0x1) << 3) | ||
82 | #define BFM_MSC_CTRL_RESET(v) BM_MSC_CTRL_RESET | ||
83 | #define BF_MSC_CTRL_RESET_V(e) BF_MSC_CTRL_RESET(BV_MSC_CTRL_RESET__##e) | ||
84 | #define BFM_MSC_CTRL_RESET_V(v) BM_MSC_CTRL_RESET | ||
85 | #define BP_MSC_CTRL_START_OP 2 | ||
86 | #define BM_MSC_CTRL_START_OP 0x4 | ||
87 | #define BF_MSC_CTRL_START_OP(v) (((v) & 0x1) << 2) | ||
88 | #define BFM_MSC_CTRL_START_OP(v) BM_MSC_CTRL_START_OP | ||
89 | #define BF_MSC_CTRL_START_OP_V(e) BF_MSC_CTRL_START_OP(BV_MSC_CTRL_START_OP__##e) | ||
90 | #define BFM_MSC_CTRL_START_OP_V(v) BM_MSC_CTRL_START_OP | ||
91 | |||
92 | #define REG_MSC_STAT(_n1) jz_reg(MSC_STAT(_n1)) | ||
93 | #define JA_MSC_STAT(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x4) | ||
94 | #define JT_MSC_STAT(_n1) JIO_32_RW | ||
95 | #define JN_MSC_STAT(_n1) MSC_STAT | ||
96 | #define JI_MSC_STAT(_n1) (_n1) | ||
97 | #define BP_MSC_STAT_PINS 24 | ||
98 | #define BM_MSC_STAT_PINS 0x1f000000 | ||
99 | #define BF_MSC_STAT_PINS(v) (((v) & 0x1f) << 24) | ||
100 | #define BFM_MSC_STAT_PINS(v) BM_MSC_STAT_PINS | ||
101 | #define BF_MSC_STAT_PINS_V(e) BF_MSC_STAT_PINS(BV_MSC_STAT_PINS__##e) | ||
102 | #define BFM_MSC_STAT_PINS_V(v) BM_MSC_STAT_PINS | ||
103 | #define BP_MSC_STAT_CRC_WRITE_ERROR 2 | ||
104 | #define BM_MSC_STAT_CRC_WRITE_ERROR 0xc | ||
105 | #define BV_MSC_STAT_CRC_WRITE_ERROR__NONE 0x0 | ||
106 | #define BV_MSC_STAT_CRC_WRITE_ERROR__BADDATA 0x1 | ||
107 | #define BV_MSC_STAT_CRC_WRITE_ERROR__NOCRC 0x2 | ||
108 | #define BF_MSC_STAT_CRC_WRITE_ERROR(v) (((v) & 0x3) << 2) | ||
109 | #define BFM_MSC_STAT_CRC_WRITE_ERROR(v) BM_MSC_STAT_CRC_WRITE_ERROR | ||
110 | #define BF_MSC_STAT_CRC_WRITE_ERROR_V(e) BF_MSC_STAT_CRC_WRITE_ERROR(BV_MSC_STAT_CRC_WRITE_ERROR__##e) | ||
111 | #define BFM_MSC_STAT_CRC_WRITE_ERROR_V(v) BM_MSC_STAT_CRC_WRITE_ERROR | ||
112 | #define BP_MSC_STAT_AUTO_CMD12_DONE 31 | ||
113 | #define BM_MSC_STAT_AUTO_CMD12_DONE 0x80000000 | ||
114 | #define BF_MSC_STAT_AUTO_CMD12_DONE(v) (((v) & 0x1) << 31) | ||
115 | #define BFM_MSC_STAT_AUTO_CMD12_DONE(v) BM_MSC_STAT_AUTO_CMD12_DONE | ||
116 | #define BF_MSC_STAT_AUTO_CMD12_DONE_V(e) BF_MSC_STAT_AUTO_CMD12_DONE(BV_MSC_STAT_AUTO_CMD12_DONE__##e) | ||
117 | #define BFM_MSC_STAT_AUTO_CMD12_DONE_V(v) BM_MSC_STAT_AUTO_CMD12_DONE | ||
118 | #define BP_MSC_STAT_BCE 20 | ||
119 | #define BM_MSC_STAT_BCE 0x100000 | ||
120 | #define BF_MSC_STAT_BCE(v) (((v) & 0x1) << 20) | ||
121 | #define BFM_MSC_STAT_BCE(v) BM_MSC_STAT_BCE | ||
122 | #define BF_MSC_STAT_BCE_V(e) BF_MSC_STAT_BCE(BV_MSC_STAT_BCE__##e) | ||
123 | #define BFM_MSC_STAT_BCE_V(v) BM_MSC_STAT_BCE | ||
124 | #define BP_MSC_STAT_BDE 19 | ||
125 | #define BM_MSC_STAT_BDE 0x80000 | ||
126 | #define BF_MSC_STAT_BDE(v) (((v) & 0x1) << 19) | ||
127 | #define BFM_MSC_STAT_BDE(v) BM_MSC_STAT_BDE | ||
128 | #define BF_MSC_STAT_BDE_V(e) BF_MSC_STAT_BDE(BV_MSC_STAT_BDE__##e) | ||
129 | #define BFM_MSC_STAT_BDE_V(v) BM_MSC_STAT_BDE | ||
130 | #define BP_MSC_STAT_BAE 18 | ||
131 | #define BM_MSC_STAT_BAE 0x40000 | ||
132 | #define BF_MSC_STAT_BAE(v) (((v) & 0x1) << 18) | ||
133 | #define BFM_MSC_STAT_BAE(v) BM_MSC_STAT_BAE | ||
134 | #define BF_MSC_STAT_BAE_V(e) BF_MSC_STAT_BAE(BV_MSC_STAT_BAE__##e) | ||
135 | #define BFM_MSC_STAT_BAE_V(v) BM_MSC_STAT_BAE | ||
136 | #define BP_MSC_STAT_BAR 17 | ||
137 | #define BM_MSC_STAT_BAR 0x20000 | ||
138 | #define BF_MSC_STAT_BAR(v) (((v) & 0x1) << 17) | ||
139 | #define BFM_MSC_STAT_BAR(v) BM_MSC_STAT_BAR | ||
140 | #define BF_MSC_STAT_BAR_V(e) BF_MSC_STAT_BAR(BV_MSC_STAT_BAR__##e) | ||
141 | #define BFM_MSC_STAT_BAR_V(v) BM_MSC_STAT_BAR | ||
142 | #define BP_MSC_STAT_DMAEND 16 | ||
143 | #define BM_MSC_STAT_DMAEND 0x10000 | ||
144 | #define BF_MSC_STAT_DMAEND(v) (((v) & 0x1) << 16) | ||
145 | #define BFM_MSC_STAT_DMAEND(v) BM_MSC_STAT_DMAEND | ||
146 | #define BF_MSC_STAT_DMAEND_V(e) BF_MSC_STAT_DMAEND(BV_MSC_STAT_DMAEND__##e) | ||
147 | #define BFM_MSC_STAT_DMAEND_V(v) BM_MSC_STAT_DMAEND | ||
148 | #define BP_MSC_STAT_IS_RESETTING 15 | ||
149 | #define BM_MSC_STAT_IS_RESETTING 0x8000 | ||
150 | #define BF_MSC_STAT_IS_RESETTING(v) (((v) & 0x1) << 15) | ||
151 | #define BFM_MSC_STAT_IS_RESETTING(v) BM_MSC_STAT_IS_RESETTING | ||
152 | #define BF_MSC_STAT_IS_RESETTING_V(e) BF_MSC_STAT_IS_RESETTING(BV_MSC_STAT_IS_RESETTING__##e) | ||
153 | #define BFM_MSC_STAT_IS_RESETTING_V(v) BM_MSC_STAT_IS_RESETTING | ||
154 | #define BP_MSC_STAT_SDIO_INT_ACTIVE 14 | ||
155 | #define BM_MSC_STAT_SDIO_INT_ACTIVE 0x4000 | ||
156 | #define BF_MSC_STAT_SDIO_INT_ACTIVE(v) (((v) & 0x1) << 14) | ||
157 | #define BFM_MSC_STAT_SDIO_INT_ACTIVE(v) BM_MSC_STAT_SDIO_INT_ACTIVE | ||
158 | #define BF_MSC_STAT_SDIO_INT_ACTIVE_V(e) BF_MSC_STAT_SDIO_INT_ACTIVE(BV_MSC_STAT_SDIO_INT_ACTIVE__##e) | ||
159 | #define BFM_MSC_STAT_SDIO_INT_ACTIVE_V(v) BM_MSC_STAT_SDIO_INT_ACTIVE | ||
160 | #define BP_MSC_STAT_PROG_DONE 13 | ||
161 | #define BM_MSC_STAT_PROG_DONE 0x2000 | ||
162 | #define BF_MSC_STAT_PROG_DONE(v) (((v) & 0x1) << 13) | ||
163 | #define BFM_MSC_STAT_PROG_DONE(v) BM_MSC_STAT_PROG_DONE | ||
164 | #define BF_MSC_STAT_PROG_DONE_V(e) BF_MSC_STAT_PROG_DONE(BV_MSC_STAT_PROG_DONE__##e) | ||
165 | #define BFM_MSC_STAT_PROG_DONE_V(v) BM_MSC_STAT_PROG_DONE | ||
166 | #define BP_MSC_STAT_DATA_TRAN_DONE 12 | ||
167 | #define BM_MSC_STAT_DATA_TRAN_DONE 0x1000 | ||
168 | #define BF_MSC_STAT_DATA_TRAN_DONE(v) (((v) & 0x1) << 12) | ||
169 | #define BFM_MSC_STAT_DATA_TRAN_DONE(v) BM_MSC_STAT_DATA_TRAN_DONE | ||
170 | #define BF_MSC_STAT_DATA_TRAN_DONE_V(e) BF_MSC_STAT_DATA_TRAN_DONE(BV_MSC_STAT_DATA_TRAN_DONE__##e) | ||
171 | #define BFM_MSC_STAT_DATA_TRAN_DONE_V(v) BM_MSC_STAT_DATA_TRAN_DONE | ||
172 | #define BP_MSC_STAT_END_CMD_RES 11 | ||
173 | #define BM_MSC_STAT_END_CMD_RES 0x800 | ||
174 | #define BF_MSC_STAT_END_CMD_RES(v) (((v) & 0x1) << 11) | ||
175 | #define BFM_MSC_STAT_END_CMD_RES(v) BM_MSC_STAT_END_CMD_RES | ||
176 | #define BF_MSC_STAT_END_CMD_RES_V(e) BF_MSC_STAT_END_CMD_RES(BV_MSC_STAT_END_CMD_RES__##e) | ||
177 | #define BFM_MSC_STAT_END_CMD_RES_V(v) BM_MSC_STAT_END_CMD_RES | ||
178 | #define BP_MSC_STAT_DATA_FIFO_AFULL 10 | ||
179 | #define BM_MSC_STAT_DATA_FIFO_AFULL 0x400 | ||
180 | #define BF_MSC_STAT_DATA_FIFO_AFULL(v) (((v) & 0x1) << 10) | ||
181 | #define BFM_MSC_STAT_DATA_FIFO_AFULL(v) BM_MSC_STAT_DATA_FIFO_AFULL | ||
182 | #define BF_MSC_STAT_DATA_FIFO_AFULL_V(e) BF_MSC_STAT_DATA_FIFO_AFULL(BV_MSC_STAT_DATA_FIFO_AFULL__##e) | ||
183 | #define BFM_MSC_STAT_DATA_FIFO_AFULL_V(v) BM_MSC_STAT_DATA_FIFO_AFULL | ||
184 | #define BP_MSC_STAT_IS_READ_WAIT 9 | ||
185 | #define BM_MSC_STAT_IS_READ_WAIT 0x200 | ||
186 | #define BF_MSC_STAT_IS_READ_WAIT(v) (((v) & 0x1) << 9) | ||
187 | #define BFM_MSC_STAT_IS_READ_WAIT(v) BM_MSC_STAT_IS_READ_WAIT | ||
188 | #define BF_MSC_STAT_IS_READ_WAIT_V(e) BF_MSC_STAT_IS_READ_WAIT(BV_MSC_STAT_IS_READ_WAIT__##e) | ||
189 | #define BFM_MSC_STAT_IS_READ_WAIT_V(v) BM_MSC_STAT_IS_READ_WAIT | ||
190 | #define BP_MSC_STAT_CLOCK_EN 8 | ||
191 | #define BM_MSC_STAT_CLOCK_EN 0x100 | ||
192 | #define BF_MSC_STAT_CLOCK_EN(v) (((v) & 0x1) << 8) | ||
193 | #define BFM_MSC_STAT_CLOCK_EN(v) BM_MSC_STAT_CLOCK_EN | ||
194 | #define BF_MSC_STAT_CLOCK_EN_V(e) BF_MSC_STAT_CLOCK_EN(BV_MSC_STAT_CLOCK_EN__##e) | ||
195 | #define BFM_MSC_STAT_CLOCK_EN_V(v) BM_MSC_STAT_CLOCK_EN | ||
196 | #define BP_MSC_STAT_DATA_FIFO_FULL 7 | ||
197 | #define BM_MSC_STAT_DATA_FIFO_FULL 0x80 | ||
198 | #define BF_MSC_STAT_DATA_FIFO_FULL(v) (((v) & 0x1) << 7) | ||
199 | #define BFM_MSC_STAT_DATA_FIFO_FULL(v) BM_MSC_STAT_DATA_FIFO_FULL | ||
200 | #define BF_MSC_STAT_DATA_FIFO_FULL_V(e) BF_MSC_STAT_DATA_FIFO_FULL(BV_MSC_STAT_DATA_FIFO_FULL__##e) | ||
201 | #define BFM_MSC_STAT_DATA_FIFO_FULL_V(v) BM_MSC_STAT_DATA_FIFO_FULL | ||
202 | #define BP_MSC_STAT_DATA_FIFO_EMPTY 6 | ||
203 | #define BM_MSC_STAT_DATA_FIFO_EMPTY 0x40 | ||
204 | #define BF_MSC_STAT_DATA_FIFO_EMPTY(v) (((v) & 0x1) << 6) | ||
205 | #define BFM_MSC_STAT_DATA_FIFO_EMPTY(v) BM_MSC_STAT_DATA_FIFO_EMPTY | ||
206 | #define BF_MSC_STAT_DATA_FIFO_EMPTY_V(e) BF_MSC_STAT_DATA_FIFO_EMPTY(BV_MSC_STAT_DATA_FIFO_EMPTY__##e) | ||
207 | #define BFM_MSC_STAT_DATA_FIFO_EMPTY_V(v) BM_MSC_STAT_DATA_FIFO_EMPTY | ||
208 | #define BP_MSC_STAT_CRC_RES_ERROR 5 | ||
209 | #define BM_MSC_STAT_CRC_RES_ERROR 0x20 | ||
210 | #define BF_MSC_STAT_CRC_RES_ERROR(v) (((v) & 0x1) << 5) | ||
211 | #define BFM_MSC_STAT_CRC_RES_ERROR(v) BM_MSC_STAT_CRC_RES_ERROR | ||
212 | #define BF_MSC_STAT_CRC_RES_ERROR_V(e) BF_MSC_STAT_CRC_RES_ERROR(BV_MSC_STAT_CRC_RES_ERROR__##e) | ||
213 | #define BFM_MSC_STAT_CRC_RES_ERROR_V(v) BM_MSC_STAT_CRC_RES_ERROR | ||
214 | #define BP_MSC_STAT_CRC_READ_ERROR 4 | ||
215 | #define BM_MSC_STAT_CRC_READ_ERROR 0x10 | ||
216 | #define BF_MSC_STAT_CRC_READ_ERROR(v) (((v) & 0x1) << 4) | ||
217 | #define BFM_MSC_STAT_CRC_READ_ERROR(v) BM_MSC_STAT_CRC_READ_ERROR | ||
218 | #define BF_MSC_STAT_CRC_READ_ERROR_V(e) BF_MSC_STAT_CRC_READ_ERROR(BV_MSC_STAT_CRC_READ_ERROR__##e) | ||
219 | #define BFM_MSC_STAT_CRC_READ_ERROR_V(v) BM_MSC_STAT_CRC_READ_ERROR | ||
220 | #define BP_MSC_STAT_TIME_OUT_RES 1 | ||
221 | #define BM_MSC_STAT_TIME_OUT_RES 0x2 | ||
222 | #define BF_MSC_STAT_TIME_OUT_RES(v) (((v) & 0x1) << 1) | ||
223 | #define BFM_MSC_STAT_TIME_OUT_RES(v) BM_MSC_STAT_TIME_OUT_RES | ||
224 | #define BF_MSC_STAT_TIME_OUT_RES_V(e) BF_MSC_STAT_TIME_OUT_RES(BV_MSC_STAT_TIME_OUT_RES__##e) | ||
225 | #define BFM_MSC_STAT_TIME_OUT_RES_V(v) BM_MSC_STAT_TIME_OUT_RES | ||
226 | #define BP_MSC_STAT_TIME_OUT_READ 0 | ||
227 | #define BM_MSC_STAT_TIME_OUT_READ 0x1 | ||
228 | #define BF_MSC_STAT_TIME_OUT_READ(v) (((v) & 0x1) << 0) | ||
229 | #define BFM_MSC_STAT_TIME_OUT_READ(v) BM_MSC_STAT_TIME_OUT_READ | ||
230 | #define BF_MSC_STAT_TIME_OUT_READ_V(e) BF_MSC_STAT_TIME_OUT_READ(BV_MSC_STAT_TIME_OUT_READ__##e) | ||
231 | #define BFM_MSC_STAT_TIME_OUT_READ_V(v) BM_MSC_STAT_TIME_OUT_READ | ||
232 | |||
233 | #define REG_MSC_CMDAT(_n1) jz_reg(MSC_CMDAT(_n1)) | ||
234 | #define JA_MSC_CMDAT(_n1) (0xb3450000 + (_n1) * 0x10000 + 0xc) | ||
235 | #define JT_MSC_CMDAT(_n1) JIO_32_RW | ||
236 | #define JN_MSC_CMDAT(_n1) MSC_CMDAT | ||
237 | #define JI_MSC_CMDAT(_n1) (_n1) | ||
238 | #define BP_MSC_CMDAT_RTRG 14 | ||
239 | #define BM_MSC_CMDAT_RTRG 0xc000 | ||
240 | #define BV_MSC_CMDAT_RTRG__GE16 0x0 | ||
241 | #define BV_MSC_CMDAT_RTRG__GE32 0x1 | ||
242 | #define BV_MSC_CMDAT_RTRG__GE64 0x2 | ||
243 | #define BV_MSC_CMDAT_RTRG__GE96 0x3 | ||
244 | #define BF_MSC_CMDAT_RTRG(v) (((v) & 0x3) << 14) | ||
245 | #define BFM_MSC_CMDAT_RTRG(v) BM_MSC_CMDAT_RTRG | ||
246 | #define BF_MSC_CMDAT_RTRG_V(e) BF_MSC_CMDAT_RTRG(BV_MSC_CMDAT_RTRG__##e) | ||
247 | #define BFM_MSC_CMDAT_RTRG_V(v) BM_MSC_CMDAT_RTRG | ||
248 | #define BP_MSC_CMDAT_TTRG 12 | ||
249 | #define BM_MSC_CMDAT_TTRG 0x3000 | ||
250 | #define BV_MSC_CMDAT_TTRG__LE16 0x0 | ||
251 | #define BV_MSC_CMDAT_TTRG__LE32 0x1 | ||
252 | #define BV_MSC_CMDAT_TTRG__LE64 0x2 | ||
253 | #define BV_MSC_CMDAT_TTRG__LE96 0x3 | ||
254 | #define BF_MSC_CMDAT_TTRG(v) (((v) & 0x3) << 12) | ||
255 | #define BFM_MSC_CMDAT_TTRG(v) BM_MSC_CMDAT_TTRG | ||
256 | #define BF_MSC_CMDAT_TTRG_V(e) BF_MSC_CMDAT_TTRG(BV_MSC_CMDAT_TTRG__##e) | ||
257 | #define BFM_MSC_CMDAT_TTRG_V(v) BM_MSC_CMDAT_TTRG | ||
258 | #define BP_MSC_CMDAT_BUS_WIDTH 9 | ||
259 | #define BM_MSC_CMDAT_BUS_WIDTH 0x600 | ||
260 | #define BV_MSC_CMDAT_BUS_WIDTH__1BIT 0x0 | ||
261 | #define BV_MSC_CMDAT_BUS_WIDTH__4BIT 0x2 | ||
262 | #define BV_MSC_CMDAT_BUS_WIDTH__8BIT 0x3 | ||
263 | #define BF_MSC_CMDAT_BUS_WIDTH(v) (((v) & 0x3) << 9) | ||
264 | #define BFM_MSC_CMDAT_BUS_WIDTH(v) BM_MSC_CMDAT_BUS_WIDTH | ||
265 | #define BF_MSC_CMDAT_BUS_WIDTH_V(e) BF_MSC_CMDAT_BUS_WIDTH(BV_MSC_CMDAT_BUS_WIDTH__##e) | ||
266 | #define BFM_MSC_CMDAT_BUS_WIDTH_V(v) BM_MSC_CMDAT_BUS_WIDTH | ||
267 | #define BP_MSC_CMDAT_RESP_FMT 0 | ||
268 | #define BM_MSC_CMDAT_RESP_FMT 0x7 | ||
269 | #define BF_MSC_CMDAT_RESP_FMT(v) (((v) & 0x7) << 0) | ||
270 | #define BFM_MSC_CMDAT_RESP_FMT(v) BM_MSC_CMDAT_RESP_FMT | ||
271 | #define BF_MSC_CMDAT_RESP_FMT_V(e) BF_MSC_CMDAT_RESP_FMT(BV_MSC_CMDAT_RESP_FMT__##e) | ||
272 | #define BFM_MSC_CMDAT_RESP_FMT_V(v) BM_MSC_CMDAT_RESP_FMT | ||
273 | #define BP_MSC_CMDAT_CCS_EXPECTED 31 | ||
274 | #define BM_MSC_CMDAT_CCS_EXPECTED 0x80000000 | ||
275 | #define BF_MSC_CMDAT_CCS_EXPECTED(v) (((v) & 0x1) << 31) | ||
276 | #define BFM_MSC_CMDAT_CCS_EXPECTED(v) BM_MSC_CMDAT_CCS_EXPECTED | ||
277 | #define BF_MSC_CMDAT_CCS_EXPECTED_V(e) BF_MSC_CMDAT_CCS_EXPECTED(BV_MSC_CMDAT_CCS_EXPECTED__##e) | ||
278 | #define BFM_MSC_CMDAT_CCS_EXPECTED_V(v) BM_MSC_CMDAT_CCS_EXPECTED | ||
279 | #define BP_MSC_CMDAT_READ_CEATA 30 | ||
280 | #define BM_MSC_CMDAT_READ_CEATA 0x40000000 | ||
281 | #define BF_MSC_CMDAT_READ_CEATA(v) (((v) & 0x1) << 30) | ||
282 | #define BFM_MSC_CMDAT_READ_CEATA(v) BM_MSC_CMDAT_READ_CEATA | ||
283 | #define BF_MSC_CMDAT_READ_CEATA_V(e) BF_MSC_CMDAT_READ_CEATA(BV_MSC_CMDAT_READ_CEATA__##e) | ||
284 | #define BFM_MSC_CMDAT_READ_CEATA_V(v) BM_MSC_CMDAT_READ_CEATA | ||
285 | #define BP_MSC_CMDAT_DIS_BOOT 27 | ||
286 | #define BM_MSC_CMDAT_DIS_BOOT 0x8000000 | ||
287 | #define BF_MSC_CMDAT_DIS_BOOT(v) (((v) & 0x1) << 27) | ||
288 | #define BFM_MSC_CMDAT_DIS_BOOT(v) BM_MSC_CMDAT_DIS_BOOT | ||
289 | #define BF_MSC_CMDAT_DIS_BOOT_V(e) BF_MSC_CMDAT_DIS_BOOT(BV_MSC_CMDAT_DIS_BOOT__##e) | ||
290 | #define BFM_MSC_CMDAT_DIS_BOOT_V(v) BM_MSC_CMDAT_DIS_BOOT | ||
291 | #define BP_MSC_CMDAT_EXP_BOOT_ACK 25 | ||
292 | #define BM_MSC_CMDAT_EXP_BOOT_ACK 0x2000000 | ||
293 | #define BF_MSC_CMDAT_EXP_BOOT_ACK(v) (((v) & 0x1) << 25) | ||
294 | #define BFM_MSC_CMDAT_EXP_BOOT_ACK(v) BM_MSC_CMDAT_EXP_BOOT_ACK | ||
295 | #define BF_MSC_CMDAT_EXP_BOOT_ACK_V(e) BF_MSC_CMDAT_EXP_BOOT_ACK(BV_MSC_CMDAT_EXP_BOOT_ACK__##e) | ||
296 | #define BFM_MSC_CMDAT_EXP_BOOT_ACK_V(v) BM_MSC_CMDAT_EXP_BOOT_ACK | ||
297 | #define BP_MSC_CMDAT_BOOT_MODE 24 | ||
298 | #define BM_MSC_CMDAT_BOOT_MODE 0x1000000 | ||
299 | #define BF_MSC_CMDAT_BOOT_MODE(v) (((v) & 0x1) << 24) | ||
300 | #define BFM_MSC_CMDAT_BOOT_MODE(v) BM_MSC_CMDAT_BOOT_MODE | ||
301 | #define BF_MSC_CMDAT_BOOT_MODE_V(e) BF_MSC_CMDAT_BOOT_MODE(BV_MSC_CMDAT_BOOT_MODE__##e) | ||
302 | #define BFM_MSC_CMDAT_BOOT_MODE_V(v) BM_MSC_CMDAT_BOOT_MODE | ||
303 | #define BP_MSC_CMDAT_SDIO_PRDT 17 | ||
304 | #define BM_MSC_CMDAT_SDIO_PRDT 0x20000 | ||
305 | #define BF_MSC_CMDAT_SDIO_PRDT(v) (((v) & 0x1) << 17) | ||
306 | #define BFM_MSC_CMDAT_SDIO_PRDT(v) BM_MSC_CMDAT_SDIO_PRDT | ||
307 | #define BF_MSC_CMDAT_SDIO_PRDT_V(e) BF_MSC_CMDAT_SDIO_PRDT(BV_MSC_CMDAT_SDIO_PRDT__##e) | ||
308 | #define BFM_MSC_CMDAT_SDIO_PRDT_V(v) BM_MSC_CMDAT_SDIO_PRDT | ||
309 | #define BP_MSC_CMDAT_AUTO_CMD12 16 | ||
310 | #define BM_MSC_CMDAT_AUTO_CMD12 0x10000 | ||
311 | #define BF_MSC_CMDAT_AUTO_CMD12(v) (((v) & 0x1) << 16) | ||
312 | #define BFM_MSC_CMDAT_AUTO_CMD12(v) BM_MSC_CMDAT_AUTO_CMD12 | ||
313 | #define BF_MSC_CMDAT_AUTO_CMD12_V(e) BF_MSC_CMDAT_AUTO_CMD12(BV_MSC_CMDAT_AUTO_CMD12__##e) | ||
314 | #define BFM_MSC_CMDAT_AUTO_CMD12_V(v) BM_MSC_CMDAT_AUTO_CMD12 | ||
315 | #define BP_MSC_CMDAT_IO_ABORT 11 | ||
316 | #define BM_MSC_CMDAT_IO_ABORT 0x800 | ||
317 | #define BF_MSC_CMDAT_IO_ABORT(v) (((v) & 0x1) << 11) | ||
318 | #define BFM_MSC_CMDAT_IO_ABORT(v) BM_MSC_CMDAT_IO_ABORT | ||
319 | #define BF_MSC_CMDAT_IO_ABORT_V(e) BF_MSC_CMDAT_IO_ABORT(BV_MSC_CMDAT_IO_ABORT__##e) | ||
320 | #define BFM_MSC_CMDAT_IO_ABORT_V(v) BM_MSC_CMDAT_IO_ABORT | ||
321 | #define BP_MSC_CMDAT_INIT 7 | ||
322 | #define BM_MSC_CMDAT_INIT 0x80 | ||
323 | #define BF_MSC_CMDAT_INIT(v) (((v) & 0x1) << 7) | ||
324 | #define BFM_MSC_CMDAT_INIT(v) BM_MSC_CMDAT_INIT | ||
325 | #define BF_MSC_CMDAT_INIT_V(e) BF_MSC_CMDAT_INIT(BV_MSC_CMDAT_INIT__##e) | ||
326 | #define BFM_MSC_CMDAT_INIT_V(v) BM_MSC_CMDAT_INIT | ||
327 | #define BP_MSC_CMDAT_BUSY 6 | ||
328 | #define BM_MSC_CMDAT_BUSY 0x40 | ||
329 | #define BF_MSC_CMDAT_BUSY(v) (((v) & 0x1) << 6) | ||
330 | #define BFM_MSC_CMDAT_BUSY(v) BM_MSC_CMDAT_BUSY | ||
331 | #define BF_MSC_CMDAT_BUSY_V(e) BF_MSC_CMDAT_BUSY(BV_MSC_CMDAT_BUSY__##e) | ||
332 | #define BFM_MSC_CMDAT_BUSY_V(v) BM_MSC_CMDAT_BUSY | ||
333 | #define BP_MSC_CMDAT_STREAM_BLOCK 5 | ||
334 | #define BM_MSC_CMDAT_STREAM_BLOCK 0x20 | ||
335 | #define BF_MSC_CMDAT_STREAM_BLOCK(v) (((v) & 0x1) << 5) | ||
336 | #define BFM_MSC_CMDAT_STREAM_BLOCK(v) BM_MSC_CMDAT_STREAM_BLOCK | ||
337 | #define BF_MSC_CMDAT_STREAM_BLOCK_V(e) BF_MSC_CMDAT_STREAM_BLOCK(BV_MSC_CMDAT_STREAM_BLOCK__##e) | ||
338 | #define BFM_MSC_CMDAT_STREAM_BLOCK_V(v) BM_MSC_CMDAT_STREAM_BLOCK | ||
339 | #define BP_MSC_CMDAT_WRITE_READ 4 | ||
340 | #define BM_MSC_CMDAT_WRITE_READ 0x10 | ||
341 | #define BF_MSC_CMDAT_WRITE_READ(v) (((v) & 0x1) << 4) | ||
342 | #define BFM_MSC_CMDAT_WRITE_READ(v) BM_MSC_CMDAT_WRITE_READ | ||
343 | #define BF_MSC_CMDAT_WRITE_READ_V(e) BF_MSC_CMDAT_WRITE_READ(BV_MSC_CMDAT_WRITE_READ__##e) | ||
344 | #define BFM_MSC_CMDAT_WRITE_READ_V(v) BM_MSC_CMDAT_WRITE_READ | ||
345 | #define BP_MSC_CMDAT_DATA_EN 3 | ||
346 | #define BM_MSC_CMDAT_DATA_EN 0x8 | ||
347 | #define BF_MSC_CMDAT_DATA_EN(v) (((v) & 0x1) << 3) | ||
348 | #define BFM_MSC_CMDAT_DATA_EN(v) BM_MSC_CMDAT_DATA_EN | ||
349 | #define BF_MSC_CMDAT_DATA_EN_V(e) BF_MSC_CMDAT_DATA_EN(BV_MSC_CMDAT_DATA_EN__##e) | ||
350 | #define BFM_MSC_CMDAT_DATA_EN_V(v) BM_MSC_CMDAT_DATA_EN | ||
351 | |||
352 | #define REG_MSC_IMASK(_n1) jz_reg(MSC_IMASK(_n1)) | ||
353 | #define JA_MSC_IMASK(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x24) | ||
354 | #define JT_MSC_IMASK(_n1) JIO_32_RW | ||
355 | #define JN_MSC_IMASK(_n1) MSC_IMASK | ||
356 | #define JI_MSC_IMASK(_n1) (_n1) | ||
357 | #define BP_MSC_IMASK_PINS 24 | ||
358 | #define BM_MSC_IMASK_PINS 0x1f000000 | ||
359 | #define BF_MSC_IMASK_PINS(v) (((v) & 0x1f) << 24) | ||
360 | #define BFM_MSC_IMASK_PINS(v) BM_MSC_IMASK_PINS | ||
361 | #define BF_MSC_IMASK_PINS_V(e) BF_MSC_IMASK_PINS(BV_MSC_IMASK_PINS__##e) | ||
362 | #define BFM_MSC_IMASK_PINS_V(v) BM_MSC_IMASK_PINS | ||
363 | #define BP_MSC_IMASK_DMA_DATA_DONE 31 | ||
364 | #define BM_MSC_IMASK_DMA_DATA_DONE 0x80000000 | ||
365 | #define BF_MSC_IMASK_DMA_DATA_DONE(v) (((v) & 0x1) << 31) | ||
366 | #define BFM_MSC_IMASK_DMA_DATA_DONE(v) BM_MSC_IMASK_DMA_DATA_DONE | ||
367 | #define BF_MSC_IMASK_DMA_DATA_DONE_V(e) BF_MSC_IMASK_DMA_DATA_DONE(BV_MSC_IMASK_DMA_DATA_DONE__##e) | ||
368 | #define BFM_MSC_IMASK_DMA_DATA_DONE_V(v) BM_MSC_IMASK_DMA_DATA_DONE | ||
369 | #define BP_MSC_IMASK_WR_ALL_DONE 23 | ||
370 | #define BM_MSC_IMASK_WR_ALL_DONE 0x800000 | ||
371 | #define BF_MSC_IMASK_WR_ALL_DONE(v) (((v) & 0x1) << 23) | ||
372 | #define BFM_MSC_IMASK_WR_ALL_DONE(v) BM_MSC_IMASK_WR_ALL_DONE | ||
373 | #define BF_MSC_IMASK_WR_ALL_DONE_V(e) BF_MSC_IMASK_WR_ALL_DONE(BV_MSC_IMASK_WR_ALL_DONE__##e) | ||
374 | #define BFM_MSC_IMASK_WR_ALL_DONE_V(v) BM_MSC_IMASK_WR_ALL_DONE | ||
375 | #define BP_MSC_IMASK_BCE 20 | ||
376 | #define BM_MSC_IMASK_BCE 0x100000 | ||
377 | #define BF_MSC_IMASK_BCE(v) (((v) & 0x1) << 20) | ||
378 | #define BFM_MSC_IMASK_BCE(v) BM_MSC_IMASK_BCE | ||
379 | #define BF_MSC_IMASK_BCE_V(e) BF_MSC_IMASK_BCE(BV_MSC_IMASK_BCE__##e) | ||
380 | #define BFM_MSC_IMASK_BCE_V(v) BM_MSC_IMASK_BCE | ||
381 | #define BP_MSC_IMASK_BDE 19 | ||
382 | #define BM_MSC_IMASK_BDE 0x80000 | ||
383 | #define BF_MSC_IMASK_BDE(v) (((v) & 0x1) << 19) | ||
384 | #define BFM_MSC_IMASK_BDE(v) BM_MSC_IMASK_BDE | ||
385 | #define BF_MSC_IMASK_BDE_V(e) BF_MSC_IMASK_BDE(BV_MSC_IMASK_BDE__##e) | ||
386 | #define BFM_MSC_IMASK_BDE_V(v) BM_MSC_IMASK_BDE | ||
387 | #define BP_MSC_IMASK_BAE 18 | ||
388 | #define BM_MSC_IMASK_BAE 0x40000 | ||
389 | #define BF_MSC_IMASK_BAE(v) (((v) & 0x1) << 18) | ||
390 | #define BFM_MSC_IMASK_BAE(v) BM_MSC_IMASK_BAE | ||
391 | #define BF_MSC_IMASK_BAE_V(e) BF_MSC_IMASK_BAE(BV_MSC_IMASK_BAE__##e) | ||
392 | #define BFM_MSC_IMASK_BAE_V(v) BM_MSC_IMASK_BAE | ||
393 | #define BP_MSC_IMASK_BAR 17 | ||
394 | #define BM_MSC_IMASK_BAR 0x20000 | ||
395 | #define BF_MSC_IMASK_BAR(v) (((v) & 0x1) << 17) | ||
396 | #define BFM_MSC_IMASK_BAR(v) BM_MSC_IMASK_BAR | ||
397 | #define BF_MSC_IMASK_BAR_V(e) BF_MSC_IMASK_BAR(BV_MSC_IMASK_BAR__##e) | ||
398 | #define BFM_MSC_IMASK_BAR_V(v) BM_MSC_IMASK_BAR | ||
399 | #define BP_MSC_IMASK_DMAEND 16 | ||
400 | #define BM_MSC_IMASK_DMAEND 0x10000 | ||
401 | #define BF_MSC_IMASK_DMAEND(v) (((v) & 0x1) << 16) | ||
402 | #define BFM_MSC_IMASK_DMAEND(v) BM_MSC_IMASK_DMAEND | ||
403 | #define BF_MSC_IMASK_DMAEND_V(e) BF_MSC_IMASK_DMAEND(BV_MSC_IMASK_DMAEND__##e) | ||
404 | #define BFM_MSC_IMASK_DMAEND_V(v) BM_MSC_IMASK_DMAEND | ||
405 | #define BP_MSC_IMASK_AUTO_CMD12_DONE 15 | ||
406 | #define BM_MSC_IMASK_AUTO_CMD12_DONE 0x8000 | ||
407 | #define BF_MSC_IMASK_AUTO_CMD12_DONE(v) (((v) & 0x1) << 15) | ||
408 | #define BFM_MSC_IMASK_AUTO_CMD12_DONE(v) BM_MSC_IMASK_AUTO_CMD12_DONE | ||
409 | #define BF_MSC_IMASK_AUTO_CMD12_DONE_V(e) BF_MSC_IMASK_AUTO_CMD12_DONE(BV_MSC_IMASK_AUTO_CMD12_DONE__##e) | ||
410 | #define BFM_MSC_IMASK_AUTO_CMD12_DONE_V(v) BM_MSC_IMASK_AUTO_CMD12_DONE | ||
411 | #define BP_MSC_IMASK_DATA_FIFO_FULL 14 | ||
412 | #define BM_MSC_IMASK_DATA_FIFO_FULL 0x4000 | ||
413 | #define BF_MSC_IMASK_DATA_FIFO_FULL(v) (((v) & 0x1) << 14) | ||
414 | #define BFM_MSC_IMASK_DATA_FIFO_FULL(v) BM_MSC_IMASK_DATA_FIFO_FULL | ||
415 | #define BF_MSC_IMASK_DATA_FIFO_FULL_V(e) BF_MSC_IMASK_DATA_FIFO_FULL(BV_MSC_IMASK_DATA_FIFO_FULL__##e) | ||
416 | #define BFM_MSC_IMASK_DATA_FIFO_FULL_V(v) BM_MSC_IMASK_DATA_FIFO_FULL | ||
417 | #define BP_MSC_IMASK_DATA_FIFO_EMPTY 13 | ||
418 | #define BM_MSC_IMASK_DATA_FIFO_EMPTY 0x2000 | ||
419 | #define BF_MSC_IMASK_DATA_FIFO_EMPTY(v) (((v) & 0x1) << 13) | ||
420 | #define BFM_MSC_IMASK_DATA_FIFO_EMPTY(v) BM_MSC_IMASK_DATA_FIFO_EMPTY | ||
421 | #define BF_MSC_IMASK_DATA_FIFO_EMPTY_V(e) BF_MSC_IMASK_DATA_FIFO_EMPTY(BV_MSC_IMASK_DATA_FIFO_EMPTY__##e) | ||
422 | #define BFM_MSC_IMASK_DATA_FIFO_EMPTY_V(v) BM_MSC_IMASK_DATA_FIFO_EMPTY | ||
423 | #define BP_MSC_IMASK_CRC_RES_ERROR 12 | ||
424 | #define BM_MSC_IMASK_CRC_RES_ERROR 0x1000 | ||
425 | #define BF_MSC_IMASK_CRC_RES_ERROR(v) (((v) & 0x1) << 12) | ||
426 | #define BFM_MSC_IMASK_CRC_RES_ERROR(v) BM_MSC_IMASK_CRC_RES_ERROR | ||
427 | #define BF_MSC_IMASK_CRC_RES_ERROR_V(e) BF_MSC_IMASK_CRC_RES_ERROR(BV_MSC_IMASK_CRC_RES_ERROR__##e) | ||
428 | #define BFM_MSC_IMASK_CRC_RES_ERROR_V(v) BM_MSC_IMASK_CRC_RES_ERROR | ||
429 | #define BP_MSC_IMASK_CRC_READ_ERROR 11 | ||
430 | #define BM_MSC_IMASK_CRC_READ_ERROR 0x800 | ||
431 | #define BF_MSC_IMASK_CRC_READ_ERROR(v) (((v) & 0x1) << 11) | ||
432 | #define BFM_MSC_IMASK_CRC_READ_ERROR(v) BM_MSC_IMASK_CRC_READ_ERROR | ||
433 | #define BF_MSC_IMASK_CRC_READ_ERROR_V(e) BF_MSC_IMASK_CRC_READ_ERROR(BV_MSC_IMASK_CRC_READ_ERROR__##e) | ||
434 | #define BFM_MSC_IMASK_CRC_READ_ERROR_V(v) BM_MSC_IMASK_CRC_READ_ERROR | ||
435 | #define BP_MSC_IMASK_CRC_WRITE_ERROR 10 | ||
436 | #define BM_MSC_IMASK_CRC_WRITE_ERROR 0x400 | ||
437 | #define BF_MSC_IMASK_CRC_WRITE_ERROR(v) (((v) & 0x1) << 10) | ||
438 | #define BFM_MSC_IMASK_CRC_WRITE_ERROR(v) BM_MSC_IMASK_CRC_WRITE_ERROR | ||
439 | #define BF_MSC_IMASK_CRC_WRITE_ERROR_V(e) BF_MSC_IMASK_CRC_WRITE_ERROR(BV_MSC_IMASK_CRC_WRITE_ERROR__##e) | ||
440 | #define BFM_MSC_IMASK_CRC_WRITE_ERROR_V(v) BM_MSC_IMASK_CRC_WRITE_ERROR | ||
441 | #define BP_MSC_IMASK_TIME_OUT_RES 9 | ||
442 | #define BM_MSC_IMASK_TIME_OUT_RES 0x200 | ||
443 | #define BF_MSC_IMASK_TIME_OUT_RES(v) (((v) & 0x1) << 9) | ||
444 | #define BFM_MSC_IMASK_TIME_OUT_RES(v) BM_MSC_IMASK_TIME_OUT_RES | ||
445 | #define BF_MSC_IMASK_TIME_OUT_RES_V(e) BF_MSC_IMASK_TIME_OUT_RES(BV_MSC_IMASK_TIME_OUT_RES__##e) | ||
446 | #define BFM_MSC_IMASK_TIME_OUT_RES_V(v) BM_MSC_IMASK_TIME_OUT_RES | ||
447 | #define BP_MSC_IMASK_TIME_OUT_READ 8 | ||
448 | #define BM_MSC_IMASK_TIME_OUT_READ 0x100 | ||
449 | #define BF_MSC_IMASK_TIME_OUT_READ(v) (((v) & 0x1) << 8) | ||
450 | #define BFM_MSC_IMASK_TIME_OUT_READ(v) BM_MSC_IMASK_TIME_OUT_READ | ||
451 | #define BF_MSC_IMASK_TIME_OUT_READ_V(e) BF_MSC_IMASK_TIME_OUT_READ(BV_MSC_IMASK_TIME_OUT_READ__##e) | ||
452 | #define BFM_MSC_IMASK_TIME_OUT_READ_V(v) BM_MSC_IMASK_TIME_OUT_READ | ||
453 | #define BP_MSC_IMASK_SDIO 7 | ||
454 | #define BM_MSC_IMASK_SDIO 0x80 | ||
455 | #define BF_MSC_IMASK_SDIO(v) (((v) & 0x1) << 7) | ||
456 | #define BFM_MSC_IMASK_SDIO(v) BM_MSC_IMASK_SDIO | ||
457 | #define BF_MSC_IMASK_SDIO_V(e) BF_MSC_IMASK_SDIO(BV_MSC_IMASK_SDIO__##e) | ||
458 | #define BFM_MSC_IMASK_SDIO_V(v) BM_MSC_IMASK_SDIO | ||
459 | #define BP_MSC_IMASK_TXFIFO_WR_REQ 6 | ||
460 | #define BM_MSC_IMASK_TXFIFO_WR_REQ 0x40 | ||
461 | #define BF_MSC_IMASK_TXFIFO_WR_REQ(v) (((v) & 0x1) << 6) | ||
462 | #define BFM_MSC_IMASK_TXFIFO_WR_REQ(v) BM_MSC_IMASK_TXFIFO_WR_REQ | ||
463 | #define BF_MSC_IMASK_TXFIFO_WR_REQ_V(e) BF_MSC_IMASK_TXFIFO_WR_REQ(BV_MSC_IMASK_TXFIFO_WR_REQ__##e) | ||
464 | #define BFM_MSC_IMASK_TXFIFO_WR_REQ_V(v) BM_MSC_IMASK_TXFIFO_WR_REQ | ||
465 | #define BP_MSC_IMASK_RXFIFO_RD_REQ 5 | ||
466 | #define BM_MSC_IMASK_RXFIFO_RD_REQ 0x20 | ||
467 | #define BF_MSC_IMASK_RXFIFO_RD_REQ(v) (((v) & 0x1) << 5) | ||
468 | #define BFM_MSC_IMASK_RXFIFO_RD_REQ(v) BM_MSC_IMASK_RXFIFO_RD_REQ | ||
469 | #define BF_MSC_IMASK_RXFIFO_RD_REQ_V(e) BF_MSC_IMASK_RXFIFO_RD_REQ(BV_MSC_IMASK_RXFIFO_RD_REQ__##e) | ||
470 | #define BFM_MSC_IMASK_RXFIFO_RD_REQ_V(v) BM_MSC_IMASK_RXFIFO_RD_REQ | ||
471 | #define BP_MSC_IMASK_END_CMD_RES 2 | ||
472 | #define BM_MSC_IMASK_END_CMD_RES 0x4 | ||
473 | #define BF_MSC_IMASK_END_CMD_RES(v) (((v) & 0x1) << 2) | ||
474 | #define BFM_MSC_IMASK_END_CMD_RES(v) BM_MSC_IMASK_END_CMD_RES | ||
475 | #define BF_MSC_IMASK_END_CMD_RES_V(e) BF_MSC_IMASK_END_CMD_RES(BV_MSC_IMASK_END_CMD_RES__##e) | ||
476 | #define BFM_MSC_IMASK_END_CMD_RES_V(v) BM_MSC_IMASK_END_CMD_RES | ||
477 | #define BP_MSC_IMASK_PROG_DONE 1 | ||
478 | #define BM_MSC_IMASK_PROG_DONE 0x2 | ||
479 | #define BF_MSC_IMASK_PROG_DONE(v) (((v) & 0x1) << 1) | ||
480 | #define BFM_MSC_IMASK_PROG_DONE(v) BM_MSC_IMASK_PROG_DONE | ||
481 | #define BF_MSC_IMASK_PROG_DONE_V(e) BF_MSC_IMASK_PROG_DONE(BV_MSC_IMASK_PROG_DONE__##e) | ||
482 | #define BFM_MSC_IMASK_PROG_DONE_V(v) BM_MSC_IMASK_PROG_DONE | ||
483 | #define BP_MSC_IMASK_DATA_TRAN_DONE 0 | ||
484 | #define BM_MSC_IMASK_DATA_TRAN_DONE 0x1 | ||
485 | #define BF_MSC_IMASK_DATA_TRAN_DONE(v) (((v) & 0x1) << 0) | ||
486 | #define BFM_MSC_IMASK_DATA_TRAN_DONE(v) BM_MSC_IMASK_DATA_TRAN_DONE | ||
487 | #define BF_MSC_IMASK_DATA_TRAN_DONE_V(e) BF_MSC_IMASK_DATA_TRAN_DONE(BV_MSC_IMASK_DATA_TRAN_DONE__##e) | ||
488 | #define BFM_MSC_IMASK_DATA_TRAN_DONE_V(v) BM_MSC_IMASK_DATA_TRAN_DONE | ||
489 | |||
490 | #define REG_MSC_IFLAG(_n1) jz_reg(MSC_IFLAG(_n1)) | ||
491 | #define JA_MSC_IFLAG(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x28) | ||
492 | #define JT_MSC_IFLAG(_n1) JIO_32_RW | ||
493 | #define JN_MSC_IFLAG(_n1) MSC_IFLAG | ||
494 | #define JI_MSC_IFLAG(_n1) (_n1) | ||
495 | #define BP_MSC_IFLAG_PINS 24 | ||
496 | #define BM_MSC_IFLAG_PINS 0x1f000000 | ||
497 | #define BF_MSC_IFLAG_PINS(v) (((v) & 0x1f) << 24) | ||
498 | #define BFM_MSC_IFLAG_PINS(v) BM_MSC_IFLAG_PINS | ||
499 | #define BF_MSC_IFLAG_PINS_V(e) BF_MSC_IFLAG_PINS(BV_MSC_IFLAG_PINS__##e) | ||
500 | #define BFM_MSC_IFLAG_PINS_V(v) BM_MSC_IFLAG_PINS | ||
501 | #define BP_MSC_IFLAG_DMA_DATA_DONE 31 | ||
502 | #define BM_MSC_IFLAG_DMA_DATA_DONE 0x80000000 | ||
503 | #define BF_MSC_IFLAG_DMA_DATA_DONE(v) (((v) & 0x1) << 31) | ||
504 | #define BFM_MSC_IFLAG_DMA_DATA_DONE(v) BM_MSC_IFLAG_DMA_DATA_DONE | ||
505 | #define BF_MSC_IFLAG_DMA_DATA_DONE_V(e) BF_MSC_IFLAG_DMA_DATA_DONE(BV_MSC_IFLAG_DMA_DATA_DONE__##e) | ||
506 | #define BFM_MSC_IFLAG_DMA_DATA_DONE_V(v) BM_MSC_IFLAG_DMA_DATA_DONE | ||
507 | #define BP_MSC_IFLAG_WR_ALL_DONE 23 | ||
508 | #define BM_MSC_IFLAG_WR_ALL_DONE 0x800000 | ||
509 | #define BF_MSC_IFLAG_WR_ALL_DONE(v) (((v) & 0x1) << 23) | ||
510 | #define BFM_MSC_IFLAG_WR_ALL_DONE(v) BM_MSC_IFLAG_WR_ALL_DONE | ||
511 | #define BF_MSC_IFLAG_WR_ALL_DONE_V(e) BF_MSC_IFLAG_WR_ALL_DONE(BV_MSC_IFLAG_WR_ALL_DONE__##e) | ||
512 | #define BFM_MSC_IFLAG_WR_ALL_DONE_V(v) BM_MSC_IFLAG_WR_ALL_DONE | ||
513 | #define BP_MSC_IFLAG_BCE 20 | ||
514 | #define BM_MSC_IFLAG_BCE 0x100000 | ||
515 | #define BF_MSC_IFLAG_BCE(v) (((v) & 0x1) << 20) | ||
516 | #define BFM_MSC_IFLAG_BCE(v) BM_MSC_IFLAG_BCE | ||
517 | #define BF_MSC_IFLAG_BCE_V(e) BF_MSC_IFLAG_BCE(BV_MSC_IFLAG_BCE__##e) | ||
518 | #define BFM_MSC_IFLAG_BCE_V(v) BM_MSC_IFLAG_BCE | ||
519 | #define BP_MSC_IFLAG_BDE 19 | ||
520 | #define BM_MSC_IFLAG_BDE 0x80000 | ||
521 | #define BF_MSC_IFLAG_BDE(v) (((v) & 0x1) << 19) | ||
522 | #define BFM_MSC_IFLAG_BDE(v) BM_MSC_IFLAG_BDE | ||
523 | #define BF_MSC_IFLAG_BDE_V(e) BF_MSC_IFLAG_BDE(BV_MSC_IFLAG_BDE__##e) | ||
524 | #define BFM_MSC_IFLAG_BDE_V(v) BM_MSC_IFLAG_BDE | ||
525 | #define BP_MSC_IFLAG_BAE 18 | ||
526 | #define BM_MSC_IFLAG_BAE 0x40000 | ||
527 | #define BF_MSC_IFLAG_BAE(v) (((v) & 0x1) << 18) | ||
528 | #define BFM_MSC_IFLAG_BAE(v) BM_MSC_IFLAG_BAE | ||
529 | #define BF_MSC_IFLAG_BAE_V(e) BF_MSC_IFLAG_BAE(BV_MSC_IFLAG_BAE__##e) | ||
530 | #define BFM_MSC_IFLAG_BAE_V(v) BM_MSC_IFLAG_BAE | ||
531 | #define BP_MSC_IFLAG_BAR 17 | ||
532 | #define BM_MSC_IFLAG_BAR 0x20000 | ||
533 | #define BF_MSC_IFLAG_BAR(v) (((v) & 0x1) << 17) | ||
534 | #define BFM_MSC_IFLAG_BAR(v) BM_MSC_IFLAG_BAR | ||
535 | #define BF_MSC_IFLAG_BAR_V(e) BF_MSC_IFLAG_BAR(BV_MSC_IFLAG_BAR__##e) | ||
536 | #define BFM_MSC_IFLAG_BAR_V(v) BM_MSC_IFLAG_BAR | ||
537 | #define BP_MSC_IFLAG_DMAEND 16 | ||
538 | #define BM_MSC_IFLAG_DMAEND 0x10000 | ||
539 | #define BF_MSC_IFLAG_DMAEND(v) (((v) & 0x1) << 16) | ||
540 | #define BFM_MSC_IFLAG_DMAEND(v) BM_MSC_IFLAG_DMAEND | ||
541 | #define BF_MSC_IFLAG_DMAEND_V(e) BF_MSC_IFLAG_DMAEND(BV_MSC_IFLAG_DMAEND__##e) | ||
542 | #define BFM_MSC_IFLAG_DMAEND_V(v) BM_MSC_IFLAG_DMAEND | ||
543 | #define BP_MSC_IFLAG_AUTO_CMD12_DONE 15 | ||
544 | #define BM_MSC_IFLAG_AUTO_CMD12_DONE 0x8000 | ||
545 | #define BF_MSC_IFLAG_AUTO_CMD12_DONE(v) (((v) & 0x1) << 15) | ||
546 | #define BFM_MSC_IFLAG_AUTO_CMD12_DONE(v) BM_MSC_IFLAG_AUTO_CMD12_DONE | ||
547 | #define BF_MSC_IFLAG_AUTO_CMD12_DONE_V(e) BF_MSC_IFLAG_AUTO_CMD12_DONE(BV_MSC_IFLAG_AUTO_CMD12_DONE__##e) | ||
548 | #define BFM_MSC_IFLAG_AUTO_CMD12_DONE_V(v) BM_MSC_IFLAG_AUTO_CMD12_DONE | ||
549 | #define BP_MSC_IFLAG_DATA_FIFO_FULL 14 | ||
550 | #define BM_MSC_IFLAG_DATA_FIFO_FULL 0x4000 | ||
551 | #define BF_MSC_IFLAG_DATA_FIFO_FULL(v) (((v) & 0x1) << 14) | ||
552 | #define BFM_MSC_IFLAG_DATA_FIFO_FULL(v) BM_MSC_IFLAG_DATA_FIFO_FULL | ||
553 | #define BF_MSC_IFLAG_DATA_FIFO_FULL_V(e) BF_MSC_IFLAG_DATA_FIFO_FULL(BV_MSC_IFLAG_DATA_FIFO_FULL__##e) | ||
554 | #define BFM_MSC_IFLAG_DATA_FIFO_FULL_V(v) BM_MSC_IFLAG_DATA_FIFO_FULL | ||
555 | #define BP_MSC_IFLAG_DATA_FIFO_EMPTY 13 | ||
556 | #define BM_MSC_IFLAG_DATA_FIFO_EMPTY 0x2000 | ||
557 | #define BF_MSC_IFLAG_DATA_FIFO_EMPTY(v) (((v) & 0x1) << 13) | ||
558 | #define BFM_MSC_IFLAG_DATA_FIFO_EMPTY(v) BM_MSC_IFLAG_DATA_FIFO_EMPTY | ||
559 | #define BF_MSC_IFLAG_DATA_FIFO_EMPTY_V(e) BF_MSC_IFLAG_DATA_FIFO_EMPTY(BV_MSC_IFLAG_DATA_FIFO_EMPTY__##e) | ||
560 | #define BFM_MSC_IFLAG_DATA_FIFO_EMPTY_V(v) BM_MSC_IFLAG_DATA_FIFO_EMPTY | ||
561 | #define BP_MSC_IFLAG_CRC_RES_ERROR 12 | ||
562 | #define BM_MSC_IFLAG_CRC_RES_ERROR 0x1000 | ||
563 | #define BF_MSC_IFLAG_CRC_RES_ERROR(v) (((v) & 0x1) << 12) | ||
564 | #define BFM_MSC_IFLAG_CRC_RES_ERROR(v) BM_MSC_IFLAG_CRC_RES_ERROR | ||
565 | #define BF_MSC_IFLAG_CRC_RES_ERROR_V(e) BF_MSC_IFLAG_CRC_RES_ERROR(BV_MSC_IFLAG_CRC_RES_ERROR__##e) | ||
566 | #define BFM_MSC_IFLAG_CRC_RES_ERROR_V(v) BM_MSC_IFLAG_CRC_RES_ERROR | ||
567 | #define BP_MSC_IFLAG_CRC_READ_ERROR 11 | ||
568 | #define BM_MSC_IFLAG_CRC_READ_ERROR 0x800 | ||
569 | #define BF_MSC_IFLAG_CRC_READ_ERROR(v) (((v) & 0x1) << 11) | ||
570 | #define BFM_MSC_IFLAG_CRC_READ_ERROR(v) BM_MSC_IFLAG_CRC_READ_ERROR | ||
571 | #define BF_MSC_IFLAG_CRC_READ_ERROR_V(e) BF_MSC_IFLAG_CRC_READ_ERROR(BV_MSC_IFLAG_CRC_READ_ERROR__##e) | ||
572 | #define BFM_MSC_IFLAG_CRC_READ_ERROR_V(v) BM_MSC_IFLAG_CRC_READ_ERROR | ||
573 | #define BP_MSC_IFLAG_CRC_WRITE_ERROR 10 | ||
574 | #define BM_MSC_IFLAG_CRC_WRITE_ERROR 0x400 | ||
575 | #define BF_MSC_IFLAG_CRC_WRITE_ERROR(v) (((v) & 0x1) << 10) | ||
576 | #define BFM_MSC_IFLAG_CRC_WRITE_ERROR(v) BM_MSC_IFLAG_CRC_WRITE_ERROR | ||
577 | #define BF_MSC_IFLAG_CRC_WRITE_ERROR_V(e) BF_MSC_IFLAG_CRC_WRITE_ERROR(BV_MSC_IFLAG_CRC_WRITE_ERROR__##e) | ||
578 | #define BFM_MSC_IFLAG_CRC_WRITE_ERROR_V(v) BM_MSC_IFLAG_CRC_WRITE_ERROR | ||
579 | #define BP_MSC_IFLAG_TIME_OUT_RES 9 | ||
580 | #define BM_MSC_IFLAG_TIME_OUT_RES 0x200 | ||
581 | #define BF_MSC_IFLAG_TIME_OUT_RES(v) (((v) & 0x1) << 9) | ||
582 | #define BFM_MSC_IFLAG_TIME_OUT_RES(v) BM_MSC_IFLAG_TIME_OUT_RES | ||
583 | #define BF_MSC_IFLAG_TIME_OUT_RES_V(e) BF_MSC_IFLAG_TIME_OUT_RES(BV_MSC_IFLAG_TIME_OUT_RES__##e) | ||
584 | #define BFM_MSC_IFLAG_TIME_OUT_RES_V(v) BM_MSC_IFLAG_TIME_OUT_RES | ||
585 | #define BP_MSC_IFLAG_TIME_OUT_READ 8 | ||
586 | #define BM_MSC_IFLAG_TIME_OUT_READ 0x100 | ||
587 | #define BF_MSC_IFLAG_TIME_OUT_READ(v) (((v) & 0x1) << 8) | ||
588 | #define BFM_MSC_IFLAG_TIME_OUT_READ(v) BM_MSC_IFLAG_TIME_OUT_READ | ||
589 | #define BF_MSC_IFLAG_TIME_OUT_READ_V(e) BF_MSC_IFLAG_TIME_OUT_READ(BV_MSC_IFLAG_TIME_OUT_READ__##e) | ||
590 | #define BFM_MSC_IFLAG_TIME_OUT_READ_V(v) BM_MSC_IFLAG_TIME_OUT_READ | ||
591 | #define BP_MSC_IFLAG_SDIO 7 | ||
592 | #define BM_MSC_IFLAG_SDIO 0x80 | ||
593 | #define BF_MSC_IFLAG_SDIO(v) (((v) & 0x1) << 7) | ||
594 | #define BFM_MSC_IFLAG_SDIO(v) BM_MSC_IFLAG_SDIO | ||
595 | #define BF_MSC_IFLAG_SDIO_V(e) BF_MSC_IFLAG_SDIO(BV_MSC_IFLAG_SDIO__##e) | ||
596 | #define BFM_MSC_IFLAG_SDIO_V(v) BM_MSC_IFLAG_SDIO | ||
597 | #define BP_MSC_IFLAG_TXFIFO_WR_REQ 6 | ||
598 | #define BM_MSC_IFLAG_TXFIFO_WR_REQ 0x40 | ||
599 | #define BF_MSC_IFLAG_TXFIFO_WR_REQ(v) (((v) & 0x1) << 6) | ||
600 | #define BFM_MSC_IFLAG_TXFIFO_WR_REQ(v) BM_MSC_IFLAG_TXFIFO_WR_REQ | ||
601 | #define BF_MSC_IFLAG_TXFIFO_WR_REQ_V(e) BF_MSC_IFLAG_TXFIFO_WR_REQ(BV_MSC_IFLAG_TXFIFO_WR_REQ__##e) | ||
602 | #define BFM_MSC_IFLAG_TXFIFO_WR_REQ_V(v) BM_MSC_IFLAG_TXFIFO_WR_REQ | ||
603 | #define BP_MSC_IFLAG_RXFIFO_RD_REQ 5 | ||
604 | #define BM_MSC_IFLAG_RXFIFO_RD_REQ 0x20 | ||
605 | #define BF_MSC_IFLAG_RXFIFO_RD_REQ(v) (((v) & 0x1) << 5) | ||
606 | #define BFM_MSC_IFLAG_RXFIFO_RD_REQ(v) BM_MSC_IFLAG_RXFIFO_RD_REQ | ||
607 | #define BF_MSC_IFLAG_RXFIFO_RD_REQ_V(e) BF_MSC_IFLAG_RXFIFO_RD_REQ(BV_MSC_IFLAG_RXFIFO_RD_REQ__##e) | ||
608 | #define BFM_MSC_IFLAG_RXFIFO_RD_REQ_V(v) BM_MSC_IFLAG_RXFIFO_RD_REQ | ||
609 | #define BP_MSC_IFLAG_END_CMD_RES 2 | ||
610 | #define BM_MSC_IFLAG_END_CMD_RES 0x4 | ||
611 | #define BF_MSC_IFLAG_END_CMD_RES(v) (((v) & 0x1) << 2) | ||
612 | #define BFM_MSC_IFLAG_END_CMD_RES(v) BM_MSC_IFLAG_END_CMD_RES | ||
613 | #define BF_MSC_IFLAG_END_CMD_RES_V(e) BF_MSC_IFLAG_END_CMD_RES(BV_MSC_IFLAG_END_CMD_RES__##e) | ||
614 | #define BFM_MSC_IFLAG_END_CMD_RES_V(v) BM_MSC_IFLAG_END_CMD_RES | ||
615 | #define BP_MSC_IFLAG_PROG_DONE 1 | ||
616 | #define BM_MSC_IFLAG_PROG_DONE 0x2 | ||
617 | #define BF_MSC_IFLAG_PROG_DONE(v) (((v) & 0x1) << 1) | ||
618 | #define BFM_MSC_IFLAG_PROG_DONE(v) BM_MSC_IFLAG_PROG_DONE | ||
619 | #define BF_MSC_IFLAG_PROG_DONE_V(e) BF_MSC_IFLAG_PROG_DONE(BV_MSC_IFLAG_PROG_DONE__##e) | ||
620 | #define BFM_MSC_IFLAG_PROG_DONE_V(v) BM_MSC_IFLAG_PROG_DONE | ||
621 | #define BP_MSC_IFLAG_DATA_TRAN_DONE 0 | ||
622 | #define BM_MSC_IFLAG_DATA_TRAN_DONE 0x1 | ||
623 | #define BF_MSC_IFLAG_DATA_TRAN_DONE(v) (((v) & 0x1) << 0) | ||
624 | #define BFM_MSC_IFLAG_DATA_TRAN_DONE(v) BM_MSC_IFLAG_DATA_TRAN_DONE | ||
625 | #define BF_MSC_IFLAG_DATA_TRAN_DONE_V(e) BF_MSC_IFLAG_DATA_TRAN_DONE(BV_MSC_IFLAG_DATA_TRAN_DONE__##e) | ||
626 | #define BFM_MSC_IFLAG_DATA_TRAN_DONE_V(v) BM_MSC_IFLAG_DATA_TRAN_DONE | ||
627 | |||
628 | #define REG_MSC_LPM(_n1) jz_reg(MSC_LPM(_n1)) | ||
629 | #define JA_MSC_LPM(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x40) | ||
630 | #define JT_MSC_LPM(_n1) JIO_32_RW | ||
631 | #define JN_MSC_LPM(_n1) MSC_LPM | ||
632 | #define JI_MSC_LPM(_n1) (_n1) | ||
633 | #define BP_MSC_LPM_DRV_SEL 30 | ||
634 | #define BM_MSC_LPM_DRV_SEL 0xc0000000 | ||
635 | #define BV_MSC_LPM_DRV_SEL__FALL_EDGE 0x0 | ||
636 | #define BV_MSC_LPM_DRV_SEL__RISE_EDGE_DELAY_1NS 0x1 | ||
637 | #define BV_MSC_LPM_DRV_SEL__RISE_EDGE_DELAY_QTR_PHASE 0x2 | ||
638 | #define BF_MSC_LPM_DRV_SEL(v) (((v) & 0x3) << 30) | ||
639 | #define BFM_MSC_LPM_DRV_SEL(v) BM_MSC_LPM_DRV_SEL | ||
640 | #define BF_MSC_LPM_DRV_SEL_V(e) BF_MSC_LPM_DRV_SEL(BV_MSC_LPM_DRV_SEL__##e) | ||
641 | #define BFM_MSC_LPM_DRV_SEL_V(v) BM_MSC_LPM_DRV_SEL | ||
642 | #define BP_MSC_LPM_SMP_SEL 28 | ||
643 | #define BM_MSC_LPM_SMP_SEL 0x30000000 | ||
644 | #define BV_MSC_LPM_SMP_SEL__RISE_EDGE 0x0 | ||
645 | #define BV_MSC_LPM_SMP_SEL__RISE_EDGE_DELAYED 0x1 | ||
646 | #define BF_MSC_LPM_SMP_SEL(v) (((v) & 0x3) << 28) | ||
647 | #define BFM_MSC_LPM_SMP_SEL(v) BM_MSC_LPM_SMP_SEL | ||
648 | #define BF_MSC_LPM_SMP_SEL_V(e) BF_MSC_LPM_SMP_SEL(BV_MSC_LPM_SMP_SEL__##e) | ||
649 | #define BFM_MSC_LPM_SMP_SEL_V(v) BM_MSC_LPM_SMP_SEL | ||
650 | #define BP_MSC_LPM_ENABLE 0 | ||
651 | #define BM_MSC_LPM_ENABLE 0x1 | ||
652 | #define BF_MSC_LPM_ENABLE(v) (((v) & 0x1) << 0) | ||
653 | #define BFM_MSC_LPM_ENABLE(v) BM_MSC_LPM_ENABLE | ||
654 | #define BF_MSC_LPM_ENABLE_V(e) BF_MSC_LPM_ENABLE(BV_MSC_LPM_ENABLE__##e) | ||
655 | #define BFM_MSC_LPM_ENABLE_V(v) BM_MSC_LPM_ENABLE | ||
656 | |||
657 | #define REG_MSC_DMAC(_n1) jz_reg(MSC_DMAC(_n1)) | ||
658 | #define JA_MSC_DMAC(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x44) | ||
659 | #define JT_MSC_DMAC(_n1) JIO_32_RW | ||
660 | #define JN_MSC_DMAC(_n1) MSC_DMAC | ||
661 | #define JI_MSC_DMAC(_n1) (_n1) | ||
662 | #define BP_MSC_DMAC_ADDR_OFFSET 5 | ||
663 | #define BM_MSC_DMAC_ADDR_OFFSET 0x60 | ||
664 | #define BF_MSC_DMAC_ADDR_OFFSET(v) (((v) & 0x3) << 5) | ||
665 | #define BFM_MSC_DMAC_ADDR_OFFSET(v) BM_MSC_DMAC_ADDR_OFFSET | ||
666 | #define BF_MSC_DMAC_ADDR_OFFSET_V(e) BF_MSC_DMAC_ADDR_OFFSET(BV_MSC_DMAC_ADDR_OFFSET__##e) | ||
667 | #define BFM_MSC_DMAC_ADDR_OFFSET_V(v) BM_MSC_DMAC_ADDR_OFFSET | ||
668 | #define BP_MSC_DMAC_INCR 2 | ||
669 | #define BM_MSC_DMAC_INCR 0xc | ||
670 | #define BF_MSC_DMAC_INCR(v) (((v) & 0x3) << 2) | ||
671 | #define BFM_MSC_DMAC_INCR(v) BM_MSC_DMAC_INCR | ||
672 | #define BF_MSC_DMAC_INCR_V(e) BF_MSC_DMAC_INCR(BV_MSC_DMAC_INCR__##e) | ||
673 | #define BFM_MSC_DMAC_INCR_V(v) BM_MSC_DMAC_INCR | ||
674 | #define BP_MSC_DMAC_MODE_SEL 7 | ||
675 | #define BM_MSC_DMAC_MODE_SEL 0x80 | ||
676 | #define BF_MSC_DMAC_MODE_SEL(v) (((v) & 0x1) << 7) | ||
677 | #define BFM_MSC_DMAC_MODE_SEL(v) BM_MSC_DMAC_MODE_SEL | ||
678 | #define BF_MSC_DMAC_MODE_SEL_V(e) BF_MSC_DMAC_MODE_SEL(BV_MSC_DMAC_MODE_SEL__##e) | ||
679 | #define BFM_MSC_DMAC_MODE_SEL_V(v) BM_MSC_DMAC_MODE_SEL | ||
680 | #define BP_MSC_DMAC_ALIGN_EN 4 | ||
681 | #define BM_MSC_DMAC_ALIGN_EN 0x10 | ||
682 | #define BF_MSC_DMAC_ALIGN_EN(v) (((v) & 0x1) << 4) | ||
683 | #define BFM_MSC_DMAC_ALIGN_EN(v) BM_MSC_DMAC_ALIGN_EN | ||
684 | #define BF_MSC_DMAC_ALIGN_EN_V(e) BF_MSC_DMAC_ALIGN_EN(BV_MSC_DMAC_ALIGN_EN__##e) | ||
685 | #define BFM_MSC_DMAC_ALIGN_EN_V(v) BM_MSC_DMAC_ALIGN_EN | ||
686 | #define BP_MSC_DMAC_DMASEL 1 | ||
687 | #define BM_MSC_DMAC_DMASEL 0x2 | ||
688 | #define BF_MSC_DMAC_DMASEL(v) (((v) & 0x1) << 1) | ||
689 | #define BFM_MSC_DMAC_DMASEL(v) BM_MSC_DMAC_DMASEL | ||
690 | #define BF_MSC_DMAC_DMASEL_V(e) BF_MSC_DMAC_DMASEL(BV_MSC_DMAC_DMASEL__##e) | ||
691 | #define BFM_MSC_DMAC_DMASEL_V(v) BM_MSC_DMAC_DMASEL | ||
692 | #define BP_MSC_DMAC_ENABLE 0 | ||
693 | #define BM_MSC_DMAC_ENABLE 0x1 | ||
694 | #define BF_MSC_DMAC_ENABLE(v) (((v) & 0x1) << 0) | ||
695 | #define BFM_MSC_DMAC_ENABLE(v) BM_MSC_DMAC_ENABLE | ||
696 | #define BF_MSC_DMAC_ENABLE_V(e) BF_MSC_DMAC_ENABLE(BV_MSC_DMAC_ENABLE__##e) | ||
697 | #define BFM_MSC_DMAC_ENABLE_V(v) BM_MSC_DMAC_ENABLE | ||
698 | |||
699 | #define REG_MSC_CTRL2(_n1) jz_reg(MSC_CTRL2(_n1)) | ||
700 | #define JA_MSC_CTRL2(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x58) | ||
701 | #define JT_MSC_CTRL2(_n1) JIO_32_RW | ||
702 | #define JN_MSC_CTRL2(_n1) MSC_CTRL2 | ||
703 | #define JI_MSC_CTRL2(_n1) (_n1) | ||
704 | #define BP_MSC_CTRL2_PIN_INT_POLARITY 24 | ||
705 | #define BM_MSC_CTRL2_PIN_INT_POLARITY 0x1f000000 | ||
706 | #define BF_MSC_CTRL2_PIN_INT_POLARITY(v) (((v) & 0x1f) << 24) | ||
707 | #define BFM_MSC_CTRL2_PIN_INT_POLARITY(v) BM_MSC_CTRL2_PIN_INT_POLARITY | ||
708 | #define BF_MSC_CTRL2_PIN_INT_POLARITY_V(e) BF_MSC_CTRL2_PIN_INT_POLARITY(BV_MSC_CTRL2_PIN_INT_POLARITY__##e) | ||
709 | #define BFM_MSC_CTRL2_PIN_INT_POLARITY_V(v) BM_MSC_CTRL2_PIN_INT_POLARITY | ||
710 | #define BP_MSC_CTRL2_SPEED 0 | ||
711 | #define BM_MSC_CTRL2_SPEED 0x7 | ||
712 | #define BV_MSC_CTRL2_SPEED__DEFAULT 0x0 | ||
713 | #define BV_MSC_CTRL2_SPEED__HIGHSPEED 0x1 | ||
714 | #define BV_MSC_CTRL2_SPEED__SDR12 0x2 | ||
715 | #define BV_MSC_CTRL2_SPEED__SDR25 0x3 | ||
716 | #define BV_MSC_CTRL2_SPEED__SDR50 0x4 | ||
717 | #define BF_MSC_CTRL2_SPEED(v) (((v) & 0x7) << 0) | ||
718 | #define BFM_MSC_CTRL2_SPEED(v) BM_MSC_CTRL2_SPEED | ||
719 | #define BF_MSC_CTRL2_SPEED_V(e) BF_MSC_CTRL2_SPEED(BV_MSC_CTRL2_SPEED__##e) | ||
720 | #define BFM_MSC_CTRL2_SPEED_V(v) BM_MSC_CTRL2_SPEED | ||
721 | #define BP_MSC_CTRL2_STPRM 4 | ||
722 | #define BM_MSC_CTRL2_STPRM 0x10 | ||
723 | #define BF_MSC_CTRL2_STPRM(v) (((v) & 0x1) << 4) | ||
724 | #define BFM_MSC_CTRL2_STPRM(v) BM_MSC_CTRL2_STPRM | ||
725 | #define BF_MSC_CTRL2_STPRM_V(e) BF_MSC_CTRL2_STPRM(BV_MSC_CTRL2_STPRM__##e) | ||
726 | #define BFM_MSC_CTRL2_STPRM_V(v) BM_MSC_CTRL2_STPRM | ||
727 | |||
728 | #define REG_MSC_CLKRT(_n1) jz_reg(MSC_CLKRT(_n1)) | ||
729 | #define JA_MSC_CLKRT(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x8) | ||
730 | #define JT_MSC_CLKRT(_n1) JIO_32_RW | ||
731 | #define JN_MSC_CLKRT(_n1) MSC_CLKRT | ||
732 | #define JI_MSC_CLKRT(_n1) (_n1) | ||
733 | |||
734 | #define REG_MSC_RESTO(_n1) jz_reg(MSC_RESTO(_n1)) | ||
735 | #define JA_MSC_RESTO(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x10) | ||
736 | #define JT_MSC_RESTO(_n1) JIO_32_RW | ||
737 | #define JN_MSC_RESTO(_n1) MSC_RESTO | ||
738 | #define JI_MSC_RESTO(_n1) (_n1) | ||
739 | |||
740 | #define REG_MSC_RDTO(_n1) jz_reg(MSC_RDTO(_n1)) | ||
741 | #define JA_MSC_RDTO(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x14) | ||
742 | #define JT_MSC_RDTO(_n1) JIO_32_RW | ||
743 | #define JN_MSC_RDTO(_n1) MSC_RDTO | ||
744 | #define JI_MSC_RDTO(_n1) (_n1) | ||
745 | |||
746 | #define REG_MSC_BLKLEN(_n1) jz_reg(MSC_BLKLEN(_n1)) | ||
747 | #define JA_MSC_BLKLEN(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x18) | ||
748 | #define JT_MSC_BLKLEN(_n1) JIO_32_RW | ||
749 | #define JN_MSC_BLKLEN(_n1) MSC_BLKLEN | ||
750 | #define JI_MSC_BLKLEN(_n1) (_n1) | ||
751 | |||
752 | #define REG_MSC_NOB(_n1) jz_reg(MSC_NOB(_n1)) | ||
753 | #define JA_MSC_NOB(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x1c) | ||
754 | #define JT_MSC_NOB(_n1) JIO_32_RW | ||
755 | #define JN_MSC_NOB(_n1) MSC_NOB | ||
756 | #define JI_MSC_NOB(_n1) (_n1) | ||
757 | |||
758 | #define REG_MSC_SNOB(_n1) jz_reg(MSC_SNOB(_n1)) | ||
759 | #define JA_MSC_SNOB(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x20) | ||
760 | #define JT_MSC_SNOB(_n1) JIO_32_RW | ||
761 | #define JN_MSC_SNOB(_n1) MSC_SNOB | ||
762 | #define JI_MSC_SNOB(_n1) (_n1) | ||
763 | |||
764 | #define REG_MSC_CMD(_n1) jz_reg(MSC_CMD(_n1)) | ||
765 | #define JA_MSC_CMD(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x2c) | ||
766 | #define JT_MSC_CMD(_n1) JIO_32_RW | ||
767 | #define JN_MSC_CMD(_n1) MSC_CMD | ||
768 | #define JI_MSC_CMD(_n1) (_n1) | ||
769 | |||
770 | #define REG_MSC_ARG(_n1) jz_reg(MSC_ARG(_n1)) | ||
771 | #define JA_MSC_ARG(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x30) | ||
772 | #define JT_MSC_ARG(_n1) JIO_32_RW | ||
773 | #define JN_MSC_ARG(_n1) MSC_ARG | ||
774 | #define JI_MSC_ARG(_n1) (_n1) | ||
775 | |||
776 | #define REG_MSC_RES(_n1) jz_reg(MSC_RES(_n1)) | ||
777 | #define JA_MSC_RES(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x34) | ||
778 | #define JT_MSC_RES(_n1) JIO_32_RW | ||
779 | #define JN_MSC_RES(_n1) MSC_RES | ||
780 | #define JI_MSC_RES(_n1) (_n1) | ||
781 | |||
782 | #define REG_MSC_RXFIFO(_n1) jz_reg(MSC_RXFIFO(_n1)) | ||
783 | #define JA_MSC_RXFIFO(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x38) | ||
784 | #define JT_MSC_RXFIFO(_n1) JIO_32_RW | ||
785 | #define JN_MSC_RXFIFO(_n1) MSC_RXFIFO | ||
786 | #define JI_MSC_RXFIFO(_n1) (_n1) | ||
787 | |||
788 | #define REG_MSC_TXFIFO(_n1) jz_reg(MSC_TXFIFO(_n1)) | ||
789 | #define JA_MSC_TXFIFO(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x3c) | ||
790 | #define JT_MSC_TXFIFO(_n1) JIO_32_RW | ||
791 | #define JN_MSC_TXFIFO(_n1) MSC_TXFIFO | ||
792 | #define JI_MSC_TXFIFO(_n1) (_n1) | ||
793 | |||
794 | #define REG_MSC_DMANDA(_n1) jz_reg(MSC_DMANDA(_n1)) | ||
795 | #define JA_MSC_DMANDA(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x48) | ||
796 | #define JT_MSC_DMANDA(_n1) JIO_32_RW | ||
797 | #define JN_MSC_DMANDA(_n1) MSC_DMANDA | ||
798 | #define JI_MSC_DMANDA(_n1) (_n1) | ||
799 | |||
800 | #define REG_MSC_DMADA(_n1) jz_reg(MSC_DMADA(_n1)) | ||
801 | #define JA_MSC_DMADA(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x4c) | ||
802 | #define JT_MSC_DMADA(_n1) JIO_32_RW | ||
803 | #define JN_MSC_DMADA(_n1) MSC_DMADA | ||
804 | #define JI_MSC_DMADA(_n1) (_n1) | ||
805 | |||
806 | #define REG_MSC_DMALEN(_n1) jz_reg(MSC_DMALEN(_n1)) | ||
807 | #define JA_MSC_DMALEN(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x50) | ||
808 | #define JT_MSC_DMALEN(_n1) JIO_32_RW | ||
809 | #define JN_MSC_DMALEN(_n1) MSC_DMALEN | ||
810 | #define JI_MSC_DMALEN(_n1) (_n1) | ||
811 | |||
812 | #define REG_MSC_DMACMD(_n1) jz_reg(MSC_DMACMD(_n1)) | ||
813 | #define JA_MSC_DMACMD(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x54) | ||
814 | #define JT_MSC_DMACMD(_n1) JIO_32_RW | ||
815 | #define JN_MSC_DMACMD(_n1) MSC_DMACMD | ||
816 | #define JI_MSC_DMACMD(_n1) (_n1) | ||
817 | |||
818 | #define REG_MSC_RTCNT(_n1) jz_reg(MSC_RTCNT(_n1)) | ||
819 | #define JA_MSC_RTCNT(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x5c) | ||
820 | #define JT_MSC_RTCNT(_n1) JIO_32_RW | ||
821 | #define JN_MSC_RTCNT(_n1) MSC_RTCNT | ||
822 | #define JI_MSC_RTCNT(_n1) (_n1) | ||
823 | |||
824 | #endif /* __HEADERGEN_MSC_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/ost.h b/firmware/target/mips/ingenic_x1000/x1000/ost.h new file mode 100644 index 0000000000..8f2619e0e7 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/ost.h | |||
@@ -0,0 +1,141 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_OST_H__ | ||
25 | #define __HEADERGEN_OST_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_OST_CTRL jz_reg(OST_CTRL) | ||
30 | #define JA_OST_CTRL (0xb2000000 + 0x0) | ||
31 | #define JT_OST_CTRL JIO_32_RW | ||
32 | #define JN_OST_CTRL OST_CTRL | ||
33 | #define JI_OST_CTRL | ||
34 | #define BP_OST_CTRL_PRESCALE2 3 | ||
35 | #define BM_OST_CTRL_PRESCALE2 0x38 | ||
36 | #define BV_OST_CTRL_PRESCALE2__BY_1 0x0 | ||
37 | #define BV_OST_CTRL_PRESCALE2__BY_4 0x1 | ||
38 | #define BV_OST_CTRL_PRESCALE2__BY_16 0x2 | ||
39 | #define BF_OST_CTRL_PRESCALE2(v) (((v) & 0x7) << 3) | ||
40 | #define BFM_OST_CTRL_PRESCALE2(v) BM_OST_CTRL_PRESCALE2 | ||
41 | #define BF_OST_CTRL_PRESCALE2_V(e) BF_OST_CTRL_PRESCALE2(BV_OST_CTRL_PRESCALE2__##e) | ||
42 | #define BFM_OST_CTRL_PRESCALE2_V(v) BM_OST_CTRL_PRESCALE2 | ||
43 | #define BP_OST_CTRL_PRESCALE1 0 | ||
44 | #define BM_OST_CTRL_PRESCALE1 0x7 | ||
45 | #define BV_OST_CTRL_PRESCALE1__BY_1 0x0 | ||
46 | #define BV_OST_CTRL_PRESCALE1__BY_4 0x1 | ||
47 | #define BV_OST_CTRL_PRESCALE1__BY_16 0x2 | ||
48 | #define BF_OST_CTRL_PRESCALE1(v) (((v) & 0x7) << 0) | ||
49 | #define BFM_OST_CTRL_PRESCALE1(v) BM_OST_CTRL_PRESCALE1 | ||
50 | #define BF_OST_CTRL_PRESCALE1_V(e) BF_OST_CTRL_PRESCALE1(BV_OST_CTRL_PRESCALE1__##e) | ||
51 | #define BFM_OST_CTRL_PRESCALE1_V(v) BM_OST_CTRL_PRESCALE1 | ||
52 | |||
53 | #define REG_OST_ENABLE jz_reg(OST_ENABLE) | ||
54 | #define JA_OST_ENABLE (0xb2000000 + 0x4) | ||
55 | #define JT_OST_ENABLE JIO_32_RW | ||
56 | #define JN_OST_ENABLE OST_ENABLE | ||
57 | #define JI_OST_ENABLE | ||
58 | #define REG_OST_ENABLE_SET jz_reg(OST_ENABLE_SET) | ||
59 | #define JA_OST_ENABLE_SET (JA_OST_ENABLE + 0x30) | ||
60 | #define JT_OST_ENABLE_SET JIO_32_WO | ||
61 | #define JN_OST_ENABLE_SET OST_ENABLE | ||
62 | #define JI_OST_ENABLE_SET | ||
63 | #define REG_OST_ENABLE_CLR jz_reg(OST_ENABLE_CLR) | ||
64 | #define JA_OST_ENABLE_CLR (JA_OST_ENABLE + 0x34) | ||
65 | #define JT_OST_ENABLE_CLR JIO_32_WO | ||
66 | #define JN_OST_ENABLE_CLR OST_ENABLE | ||
67 | #define JI_OST_ENABLE_CLR | ||
68 | #define BP_OST_ENABLE_OST1 0 | ||
69 | #define BM_OST_ENABLE_OST1 0x1 | ||
70 | #define BF_OST_ENABLE_OST1(v) (((v) & 0x1) << 0) | ||
71 | #define BFM_OST_ENABLE_OST1(v) BM_OST_ENABLE_OST1 | ||
72 | #define BF_OST_ENABLE_OST1_V(e) BF_OST_ENABLE_OST1(BV_OST_ENABLE_OST1__##e) | ||
73 | #define BFM_OST_ENABLE_OST1_V(v) BM_OST_ENABLE_OST1 | ||
74 | #define BP_OST_ENABLE_OST2 1 | ||
75 | #define BM_OST_ENABLE_OST2 0x2 | ||
76 | #define BF_OST_ENABLE_OST2(v) (((v) & 0x1) << 1) | ||
77 | #define BFM_OST_ENABLE_OST2(v) BM_OST_ENABLE_OST2 | ||
78 | #define BF_OST_ENABLE_OST2_V(e) BF_OST_ENABLE_OST2(BV_OST_ENABLE_OST2__##e) | ||
79 | #define BFM_OST_ENABLE_OST2_V(v) BM_OST_ENABLE_OST2 | ||
80 | |||
81 | #define REG_OST_CLEAR jz_reg(OST_CLEAR) | ||
82 | #define JA_OST_CLEAR (0xb2000000 + 0x8) | ||
83 | #define JT_OST_CLEAR JIO_32_RW | ||
84 | #define JN_OST_CLEAR OST_CLEAR | ||
85 | #define JI_OST_CLEAR | ||
86 | #define BP_OST_CLEAR_OST1 0 | ||
87 | #define BM_OST_CLEAR_OST1 0x1 | ||
88 | #define BF_OST_CLEAR_OST1(v) (((v) & 0x1) << 0) | ||
89 | #define BFM_OST_CLEAR_OST1(v) BM_OST_CLEAR_OST1 | ||
90 | #define BF_OST_CLEAR_OST1_V(e) BF_OST_CLEAR_OST1(BV_OST_CLEAR_OST1__##e) | ||
91 | #define BFM_OST_CLEAR_OST1_V(v) BM_OST_CLEAR_OST1 | ||
92 | #define BP_OST_CLEAR_OST2 1 | ||
93 | #define BM_OST_CLEAR_OST2 0x2 | ||
94 | #define BF_OST_CLEAR_OST2(v) (((v) & 0x1) << 1) | ||
95 | #define BFM_OST_CLEAR_OST2(v) BM_OST_CLEAR_OST2 | ||
96 | #define BF_OST_CLEAR_OST2_V(e) BF_OST_CLEAR_OST2(BV_OST_CLEAR_OST2__##e) | ||
97 | #define BFM_OST_CLEAR_OST2_V(v) BM_OST_CLEAR_OST2 | ||
98 | |||
99 | #define REG_OST_1FLG jz_reg(OST_1FLG) | ||
100 | #define JA_OST_1FLG (0xb2000000 + 0xc) | ||
101 | #define JT_OST_1FLG JIO_32_RW | ||
102 | #define JN_OST_1FLG OST_1FLG | ||
103 | #define JI_OST_1FLG | ||
104 | |||
105 | #define REG_OST_1MSK jz_reg(OST_1MSK) | ||
106 | #define JA_OST_1MSK (0xb2000000 + 0x10) | ||
107 | #define JT_OST_1MSK JIO_32_RW | ||
108 | #define JN_OST_1MSK OST_1MSK | ||
109 | #define JI_OST_1MSK | ||
110 | |||
111 | #define REG_OST_1DFR jz_reg(OST_1DFR) | ||
112 | #define JA_OST_1DFR (0xb2000000 + 0x14) | ||
113 | #define JT_OST_1DFR JIO_32_RW | ||
114 | #define JN_OST_1DFR OST_1DFR | ||
115 | #define JI_OST_1DFR | ||
116 | |||
117 | #define REG_OST_1CNT jz_reg(OST_1CNT) | ||
118 | #define JA_OST_1CNT (0xb2000000 + 0x18) | ||
119 | #define JT_OST_1CNT JIO_32_RW | ||
120 | #define JN_OST_1CNT OST_1CNT | ||
121 | #define JI_OST_1CNT | ||
122 | |||
123 | #define REG_OST_2CNTH jz_reg(OST_2CNTH) | ||
124 | #define JA_OST_2CNTH (0xb2000000 + 0x1c) | ||
125 | #define JT_OST_2CNTH JIO_32_RW | ||
126 | #define JN_OST_2CNTH OST_2CNTH | ||
127 | #define JI_OST_2CNTH | ||
128 | |||
129 | #define REG_OST_2CNTL jz_reg(OST_2CNTL) | ||
130 | #define JA_OST_2CNTL (0xb2000000 + 0x20) | ||
131 | #define JT_OST_2CNTL JIO_32_RW | ||
132 | #define JN_OST_2CNTL OST_2CNTL | ||
133 | #define JI_OST_2CNTL | ||
134 | |||
135 | #define REG_OST_2CNTHB jz_reg(OST_2CNTHB) | ||
136 | #define JA_OST_2CNTHB (0xb2000000 + 0x24) | ||
137 | #define JT_OST_2CNTHB JIO_32_RW | ||
138 | #define JN_OST_2CNTHB OST_2CNTHB | ||
139 | #define JI_OST_2CNTHB | ||
140 | |||
141 | #endif /* __HEADERGEN_OST_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/rtc.h b/firmware/target/mips/ingenic_x1000/x1000/rtc.h new file mode 100644 index 0000000000..38f82e7d0d --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/rtc.h | |||
@@ -0,0 +1,221 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_RTC_H__ | ||
25 | #define __HEADERGEN_RTC_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_RTC_CR jz_reg(RTC_CR) | ||
30 | #define JA_RTC_CR (0xb0003000 + 0x0) | ||
31 | #define JT_RTC_CR JIO_32_RW | ||
32 | #define JN_RTC_CR RTC_CR | ||
33 | #define JI_RTC_CR | ||
34 | #define BP_RTC_CR_WRDY 7 | ||
35 | #define BM_RTC_CR_WRDY 0x80 | ||
36 | #define BF_RTC_CR_WRDY(v) (((v) & 0x1) << 7) | ||
37 | #define BFM_RTC_CR_WRDY(v) BM_RTC_CR_WRDY | ||
38 | #define BF_RTC_CR_WRDY_V(e) BF_RTC_CR_WRDY(BV_RTC_CR_WRDY__##e) | ||
39 | #define BFM_RTC_CR_WRDY_V(v) BM_RTC_CR_WRDY | ||
40 | #define BP_RTC_CR_1HZ 6 | ||
41 | #define BM_RTC_CR_1HZ 0x40 | ||
42 | #define BF_RTC_CR_1HZ(v) (((v) & 0x1) << 6) | ||
43 | #define BFM_RTC_CR_1HZ(v) BM_RTC_CR_1HZ | ||
44 | #define BF_RTC_CR_1HZ_V(e) BF_RTC_CR_1HZ(BV_RTC_CR_1HZ__##e) | ||
45 | #define BFM_RTC_CR_1HZ_V(v) BM_RTC_CR_1HZ | ||
46 | #define BP_RTC_CR_1HZIE 5 | ||
47 | #define BM_RTC_CR_1HZIE 0x20 | ||
48 | #define BF_RTC_CR_1HZIE(v) (((v) & 0x1) << 5) | ||
49 | #define BFM_RTC_CR_1HZIE(v) BM_RTC_CR_1HZIE | ||
50 | #define BF_RTC_CR_1HZIE_V(e) BF_RTC_CR_1HZIE(BV_RTC_CR_1HZIE__##e) | ||
51 | #define BFM_RTC_CR_1HZIE_V(v) BM_RTC_CR_1HZIE | ||
52 | #define BP_RTC_CR_AF 4 | ||
53 | #define BM_RTC_CR_AF 0x10 | ||
54 | #define BF_RTC_CR_AF(v) (((v) & 0x1) << 4) | ||
55 | #define BFM_RTC_CR_AF(v) BM_RTC_CR_AF | ||
56 | #define BF_RTC_CR_AF_V(e) BF_RTC_CR_AF(BV_RTC_CR_AF__##e) | ||
57 | #define BFM_RTC_CR_AF_V(v) BM_RTC_CR_AF | ||
58 | #define BP_RTC_CR_AIE 3 | ||
59 | #define BM_RTC_CR_AIE 0x8 | ||
60 | #define BF_RTC_CR_AIE(v) (((v) & 0x1) << 3) | ||
61 | #define BFM_RTC_CR_AIE(v) BM_RTC_CR_AIE | ||
62 | #define BF_RTC_CR_AIE_V(e) BF_RTC_CR_AIE(BV_RTC_CR_AIE__##e) | ||
63 | #define BFM_RTC_CR_AIE_V(v) BM_RTC_CR_AIE | ||
64 | #define BP_RTC_CR_AE 2 | ||
65 | #define BM_RTC_CR_AE 0x4 | ||
66 | #define BF_RTC_CR_AE(v) (((v) & 0x1) << 2) | ||
67 | #define BFM_RTC_CR_AE(v) BM_RTC_CR_AE | ||
68 | #define BF_RTC_CR_AE_V(e) BF_RTC_CR_AE(BV_RTC_CR_AE__##e) | ||
69 | #define BFM_RTC_CR_AE_V(v) BM_RTC_CR_AE | ||
70 | #define BP_RTC_CR_SELEXC 1 | ||
71 | #define BM_RTC_CR_SELEXC 0x2 | ||
72 | #define BF_RTC_CR_SELEXC(v) (((v) & 0x1) << 1) | ||
73 | #define BFM_RTC_CR_SELEXC(v) BM_RTC_CR_SELEXC | ||
74 | #define BF_RTC_CR_SELEXC_V(e) BF_RTC_CR_SELEXC(BV_RTC_CR_SELEXC__##e) | ||
75 | #define BFM_RTC_CR_SELEXC_V(v) BM_RTC_CR_SELEXC | ||
76 | #define BP_RTC_CR_ENABLE 0 | ||
77 | #define BM_RTC_CR_ENABLE 0x1 | ||
78 | #define BF_RTC_CR_ENABLE(v) (((v) & 0x1) << 0) | ||
79 | #define BFM_RTC_CR_ENABLE(v) BM_RTC_CR_ENABLE | ||
80 | #define BF_RTC_CR_ENABLE_V(e) BF_RTC_CR_ENABLE(BV_RTC_CR_ENABLE__##e) | ||
81 | #define BFM_RTC_CR_ENABLE_V(v) BM_RTC_CR_ENABLE | ||
82 | |||
83 | #define REG_RTC_SR jz_reg(RTC_SR) | ||
84 | #define JA_RTC_SR (0xb0003000 + 0x4) | ||
85 | #define JT_RTC_SR JIO_32_RW | ||
86 | #define JN_RTC_SR RTC_SR | ||
87 | #define JI_RTC_SR | ||
88 | |||
89 | #define REG_RTC_SAR jz_reg(RTC_SAR) | ||
90 | #define JA_RTC_SAR (0xb0003000 + 0x8) | ||
91 | #define JT_RTC_SAR JIO_32_RW | ||
92 | #define JN_RTC_SAR RTC_SAR | ||
93 | #define JI_RTC_SAR | ||
94 | |||
95 | #define REG_RTC_GR jz_reg(RTC_GR) | ||
96 | #define JA_RTC_GR (0xb0003000 + 0xc) | ||
97 | #define JT_RTC_GR JIO_32_RW | ||
98 | #define JN_RTC_GR RTC_GR | ||
99 | #define JI_RTC_GR | ||
100 | #define BP_RTC_GR_ADJC 16 | ||
101 | #define BM_RTC_GR_ADJC 0x3ff0000 | ||
102 | #define BF_RTC_GR_ADJC(v) (((v) & 0x3ff) << 16) | ||
103 | #define BFM_RTC_GR_ADJC(v) BM_RTC_GR_ADJC | ||
104 | #define BF_RTC_GR_ADJC_V(e) BF_RTC_GR_ADJC(BV_RTC_GR_ADJC__##e) | ||
105 | #define BFM_RTC_GR_ADJC_V(v) BM_RTC_GR_ADJC | ||
106 | #define BP_RTC_GR_NC1HZ 0 | ||
107 | #define BM_RTC_GR_NC1HZ 0xffff | ||
108 | #define BF_RTC_GR_NC1HZ(v) (((v) & 0xffff) << 0) | ||
109 | #define BFM_RTC_GR_NC1HZ(v) BM_RTC_GR_NC1HZ | ||
110 | #define BF_RTC_GR_NC1HZ_V(e) BF_RTC_GR_NC1HZ(BV_RTC_GR_NC1HZ__##e) | ||
111 | #define BFM_RTC_GR_NC1HZ_V(v) BM_RTC_GR_NC1HZ | ||
112 | #define BP_RTC_GR_LOCK 31 | ||
113 | #define BM_RTC_GR_LOCK 0x80000000 | ||
114 | #define BF_RTC_GR_LOCK(v) (((v) & 0x1) << 31) | ||
115 | #define BFM_RTC_GR_LOCK(v) BM_RTC_GR_LOCK | ||
116 | #define BF_RTC_GR_LOCK_V(e) BF_RTC_GR_LOCK(BV_RTC_GR_LOCK__##e) | ||
117 | #define BFM_RTC_GR_LOCK_V(v) BM_RTC_GR_LOCK | ||
118 | |||
119 | #define REG_RTC_HCR jz_reg(RTC_HCR) | ||
120 | #define JA_RTC_HCR (0xb0003000 + 0x20) | ||
121 | #define JT_RTC_HCR JIO_32_RW | ||
122 | #define JN_RTC_HCR RTC_HCR | ||
123 | #define JI_RTC_HCR | ||
124 | |||
125 | #define REG_RTC_HWFCR jz_reg(RTC_HWFCR) | ||
126 | #define JA_RTC_HWFCR (0xb0003000 + 0x24) | ||
127 | #define JT_RTC_HWFCR JIO_32_RW | ||
128 | #define JN_RTC_HWFCR RTC_HWFCR | ||
129 | #define JI_RTC_HWFCR | ||
130 | |||
131 | #define REG_RTC_HRCR jz_reg(RTC_HRCR) | ||
132 | #define JA_RTC_HRCR (0xb0003000 + 0x28) | ||
133 | #define JT_RTC_HRCR JIO_32_RW | ||
134 | #define JN_RTC_HRCR RTC_HRCR | ||
135 | #define JI_RTC_HRCR | ||
136 | |||
137 | #define REG_RTC_HWCR jz_reg(RTC_HWCR) | ||
138 | #define JA_RTC_HWCR (0xb0003000 + 0x2c) | ||
139 | #define JT_RTC_HWCR JIO_32_RW | ||
140 | #define JN_RTC_HWCR RTC_HWCR | ||
141 | #define JI_RTC_HWCR | ||
142 | #define BP_RTC_HWCR_EPDET 3 | ||
143 | #define BM_RTC_HWCR_EPDET 0xfffffff8 | ||
144 | #define BF_RTC_HWCR_EPDET(v) (((v) & 0x1fffffff) << 3) | ||
145 | #define BFM_RTC_HWCR_EPDET(v) BM_RTC_HWCR_EPDET | ||
146 | #define BF_RTC_HWCR_EPDET_V(e) BF_RTC_HWCR_EPDET(BV_RTC_HWCR_EPDET__##e) | ||
147 | #define BFM_RTC_HWCR_EPDET_V(v) BM_RTC_HWCR_EPDET | ||
148 | #define BP_RTC_HWCR_EALM 1 | ||
149 | #define BM_RTC_HWCR_EALM 0x2 | ||
150 | #define BF_RTC_HWCR_EALM(v) (((v) & 0x1) << 1) | ||
151 | #define BFM_RTC_HWCR_EALM(v) BM_RTC_HWCR_EALM | ||
152 | #define BF_RTC_HWCR_EALM_V(e) BF_RTC_HWCR_EALM(BV_RTC_HWCR_EALM__##e) | ||
153 | #define BFM_RTC_HWCR_EALM_V(v) BM_RTC_HWCR_EALM | ||
154 | |||
155 | #define REG_RTC_HWRSR jz_reg(RTC_HWRSR) | ||
156 | #define JA_RTC_HWRSR (0xb0003000 + 0x30) | ||
157 | #define JT_RTC_HWRSR JIO_32_RW | ||
158 | #define JN_RTC_HWRSR RTC_HWRSR | ||
159 | #define JI_RTC_HWRSR | ||
160 | #define BP_RTC_HWRSR_APD 8 | ||
161 | #define BM_RTC_HWRSR_APD 0x100 | ||
162 | #define BF_RTC_HWRSR_APD(v) (((v) & 0x1) << 8) | ||
163 | #define BFM_RTC_HWRSR_APD(v) BM_RTC_HWRSR_APD | ||
164 | #define BF_RTC_HWRSR_APD_V(e) BF_RTC_HWRSR_APD(BV_RTC_HWRSR_APD__##e) | ||
165 | #define BFM_RTC_HWRSR_APD_V(v) BM_RTC_HWRSR_APD | ||
166 | #define BP_RTC_HWRSR_HR 5 | ||
167 | #define BM_RTC_HWRSR_HR 0x20 | ||
168 | #define BF_RTC_HWRSR_HR(v) (((v) & 0x1) << 5) | ||
169 | #define BFM_RTC_HWRSR_HR(v) BM_RTC_HWRSR_HR | ||
170 | #define BF_RTC_HWRSR_HR_V(e) BF_RTC_HWRSR_HR(BV_RTC_HWRSR_HR__##e) | ||
171 | #define BFM_RTC_HWRSR_HR_V(v) BM_RTC_HWRSR_HR | ||
172 | #define BP_RTC_HWRSR_PPR 4 | ||
173 | #define BM_RTC_HWRSR_PPR 0x10 | ||
174 | #define BF_RTC_HWRSR_PPR(v) (((v) & 0x1) << 4) | ||
175 | #define BFM_RTC_HWRSR_PPR(v) BM_RTC_HWRSR_PPR | ||
176 | #define BF_RTC_HWRSR_PPR_V(e) BF_RTC_HWRSR_PPR(BV_RTC_HWRSR_PPR__##e) | ||
177 | #define BFM_RTC_HWRSR_PPR_V(v) BM_RTC_HWRSR_PPR | ||
178 | #define BP_RTC_HWRSR_PIN 1 | ||
179 | #define BM_RTC_HWRSR_PIN 0x2 | ||
180 | #define BF_RTC_HWRSR_PIN(v) (((v) & 0x1) << 1) | ||
181 | #define BFM_RTC_HWRSR_PIN(v) BM_RTC_HWRSR_PIN | ||
182 | #define BF_RTC_HWRSR_PIN_V(e) BF_RTC_HWRSR_PIN(BV_RTC_HWRSR_PIN__##e) | ||
183 | #define BFM_RTC_HWRSR_PIN_V(v) BM_RTC_HWRSR_PIN | ||
184 | #define BP_RTC_HWRSR_ALM 0 | ||
185 | #define BM_RTC_HWRSR_ALM 0x1 | ||
186 | #define BF_RTC_HWRSR_ALM(v) (((v) & 0x1) << 0) | ||
187 | #define BFM_RTC_HWRSR_ALM(v) BM_RTC_HWRSR_ALM | ||
188 | #define BF_RTC_HWRSR_ALM_V(e) BF_RTC_HWRSR_ALM(BV_RTC_HWRSR_ALM__##e) | ||
189 | #define BFM_RTC_HWRSR_ALM_V(v) BM_RTC_HWRSR_ALM | ||
190 | |||
191 | #define REG_RTC_HSPR jz_reg(RTC_HSPR) | ||
192 | #define JA_RTC_HSPR (0xb0003000 + 0x34) | ||
193 | #define JT_RTC_HSPR JIO_32_RW | ||
194 | #define JN_RTC_HSPR RTC_HSPR | ||
195 | #define JI_RTC_HSPR | ||
196 | |||
197 | #define REG_RTC_WENR jz_reg(RTC_WENR) | ||
198 | #define JA_RTC_WENR (0xb0003000 + 0x3c) | ||
199 | #define JT_RTC_WENR JIO_32_RW | ||
200 | #define JN_RTC_WENR RTC_WENR | ||
201 | #define JI_RTC_WENR | ||
202 | #define BP_RTC_WENR_WEN 31 | ||
203 | #define BM_RTC_WENR_WEN 0x80000000 | ||
204 | #define BF_RTC_WENR_WEN(v) (((v) & 0x1) << 31) | ||
205 | #define BFM_RTC_WENR_WEN(v) BM_RTC_WENR_WEN | ||
206 | #define BF_RTC_WENR_WEN_V(e) BF_RTC_WENR_WEN(BV_RTC_WENR_WEN__##e) | ||
207 | #define BFM_RTC_WENR_WEN_V(v) BM_RTC_WENR_WEN | ||
208 | #define BP_RTC_WENR_WENPAT 0 | ||
209 | #define BM_RTC_WENR_WENPAT 0xffff | ||
210 | #define BF_RTC_WENR_WENPAT(v) (((v) & 0xffff) << 0) | ||
211 | #define BFM_RTC_WENR_WENPAT(v) BM_RTC_WENR_WENPAT | ||
212 | #define BF_RTC_WENR_WENPAT_V(e) BF_RTC_WENR_WENPAT(BV_RTC_WENR_WENPAT__##e) | ||
213 | #define BFM_RTC_WENR_WENPAT_V(v) BM_RTC_WENR_WENPAT | ||
214 | |||
215 | #define REG_RTC_WKUPPINCR jz_reg(RTC_WKUPPINCR) | ||
216 | #define JA_RTC_WKUPPINCR (0xb0003000 + 0x48) | ||
217 | #define JT_RTC_WKUPPINCR JIO_32_RW | ||
218 | #define JN_RTC_WKUPPINCR RTC_WKUPPINCR | ||
219 | #define JI_RTC_WKUPPINCR | ||
220 | |||
221 | #endif /* __HEADERGEN_RTC_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/sfc.h b/firmware/target/mips/ingenic_x1000/x1000/sfc.h new file mode 100644 index 0000000000..1a3c102c64 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/sfc.h | |||
@@ -0,0 +1,481 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_SFC_H__ | ||
25 | #define __HEADERGEN_SFC_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_SFC_GLB jz_reg(SFC_GLB) | ||
30 | #define JA_SFC_GLB (0xb3440000 + 0x0) | ||
31 | #define JT_SFC_GLB JIO_32_RW | ||
32 | #define JN_SFC_GLB SFC_GLB | ||
33 | #define JI_SFC_GLB | ||
34 | #define BP_SFC_GLB_THRESHOLD 7 | ||
35 | #define BM_SFC_GLB_THRESHOLD 0x1f80 | ||
36 | #define BF_SFC_GLB_THRESHOLD(v) (((v) & 0x3f) << 7) | ||
37 | #define BFM_SFC_GLB_THRESHOLD(v) BM_SFC_GLB_THRESHOLD | ||
38 | #define BF_SFC_GLB_THRESHOLD_V(e) BF_SFC_GLB_THRESHOLD(BV_SFC_GLB_THRESHOLD__##e) | ||
39 | #define BFM_SFC_GLB_THRESHOLD_V(v) BM_SFC_GLB_THRESHOLD | ||
40 | #define BP_SFC_GLB_PHASE_NUM 3 | ||
41 | #define BM_SFC_GLB_PHASE_NUM 0x38 | ||
42 | #define BF_SFC_GLB_PHASE_NUM(v) (((v) & 0x7) << 3) | ||
43 | #define BFM_SFC_GLB_PHASE_NUM(v) BM_SFC_GLB_PHASE_NUM | ||
44 | #define BF_SFC_GLB_PHASE_NUM_V(e) BF_SFC_GLB_PHASE_NUM(BV_SFC_GLB_PHASE_NUM__##e) | ||
45 | #define BFM_SFC_GLB_PHASE_NUM_V(v) BM_SFC_GLB_PHASE_NUM | ||
46 | #define BP_SFC_GLB_TRAN_DIR 13 | ||
47 | #define BM_SFC_GLB_TRAN_DIR 0x2000 | ||
48 | #define BV_SFC_GLB_TRAN_DIR__READ 0x0 | ||
49 | #define BV_SFC_GLB_TRAN_DIR__WRITE 0x1 | ||
50 | #define BF_SFC_GLB_TRAN_DIR(v) (((v) & 0x1) << 13) | ||
51 | #define BFM_SFC_GLB_TRAN_DIR(v) BM_SFC_GLB_TRAN_DIR | ||
52 | #define BF_SFC_GLB_TRAN_DIR_V(e) BF_SFC_GLB_TRAN_DIR(BV_SFC_GLB_TRAN_DIR__##e) | ||
53 | #define BFM_SFC_GLB_TRAN_DIR_V(v) BM_SFC_GLB_TRAN_DIR | ||
54 | #define BP_SFC_GLB_OP_MODE 6 | ||
55 | #define BM_SFC_GLB_OP_MODE 0x40 | ||
56 | #define BV_SFC_GLB_OP_MODE__SLAVE 0x0 | ||
57 | #define BV_SFC_GLB_OP_MODE__DMA 0x1 | ||
58 | #define BF_SFC_GLB_OP_MODE(v) (((v) & 0x1) << 6) | ||
59 | #define BFM_SFC_GLB_OP_MODE(v) BM_SFC_GLB_OP_MODE | ||
60 | #define BF_SFC_GLB_OP_MODE_V(e) BF_SFC_GLB_OP_MODE(BV_SFC_GLB_OP_MODE__##e) | ||
61 | #define BFM_SFC_GLB_OP_MODE_V(v) BM_SFC_GLB_OP_MODE | ||
62 | #define BP_SFC_GLB_WP_EN 2 | ||
63 | #define BM_SFC_GLB_WP_EN 0x4 | ||
64 | #define BF_SFC_GLB_WP_EN(v) (((v) & 0x1) << 2) | ||
65 | #define BFM_SFC_GLB_WP_EN(v) BM_SFC_GLB_WP_EN | ||
66 | #define BF_SFC_GLB_WP_EN_V(e) BF_SFC_GLB_WP_EN(BV_SFC_GLB_WP_EN__##e) | ||
67 | #define BFM_SFC_GLB_WP_EN_V(v) BM_SFC_GLB_WP_EN | ||
68 | #define BP_SFC_GLB_BURST_MD 0 | ||
69 | #define BM_SFC_GLB_BURST_MD 0x3 | ||
70 | #define BV_SFC_GLB_BURST_MD__INCR4 0x0 | ||
71 | #define BV_SFC_GLB_BURST_MD__INCR8 0x1 | ||
72 | #define BV_SFC_GLB_BURST_MD__INCR16 0x2 | ||
73 | #define BV_SFC_GLB_BURST_MD__INCR32 0x3 | ||
74 | #define BF_SFC_GLB_BURST_MD(v) (((v) & 0x3) << 0) | ||
75 | #define BFM_SFC_GLB_BURST_MD(v) BM_SFC_GLB_BURST_MD | ||
76 | #define BF_SFC_GLB_BURST_MD_V(e) BF_SFC_GLB_BURST_MD(BV_SFC_GLB_BURST_MD__##e) | ||
77 | #define BFM_SFC_GLB_BURST_MD_V(v) BM_SFC_GLB_BURST_MD | ||
78 | |||
79 | #define REG_SFC_DEV_CONF jz_reg(SFC_DEV_CONF) | ||
80 | #define JA_SFC_DEV_CONF (0xb3440000 + 0x4) | ||
81 | #define JT_SFC_DEV_CONF JIO_32_RW | ||
82 | #define JN_SFC_DEV_CONF SFC_DEV_CONF | ||
83 | #define JI_SFC_DEV_CONF | ||
84 | #define BP_SFC_DEV_CONF_SMP_DELAY 16 | ||
85 | #define BM_SFC_DEV_CONF_SMP_DELAY 0x30000 | ||
86 | #define BF_SFC_DEV_CONF_SMP_DELAY(v) (((v) & 0x3) << 16) | ||
87 | #define BFM_SFC_DEV_CONF_SMP_DELAY(v) BM_SFC_DEV_CONF_SMP_DELAY | ||
88 | #define BF_SFC_DEV_CONF_SMP_DELAY_V(e) BF_SFC_DEV_CONF_SMP_DELAY(BV_SFC_DEV_CONF_SMP_DELAY__##e) | ||
89 | #define BFM_SFC_DEV_CONF_SMP_DELAY_V(v) BM_SFC_DEV_CONF_SMP_DELAY | ||
90 | #define BP_SFC_DEV_CONF_STA_TYPE 13 | ||
91 | #define BM_SFC_DEV_CONF_STA_TYPE 0x6000 | ||
92 | #define BV_SFC_DEV_CONF_STA_TYPE__1BYTE 0x0 | ||
93 | #define BV_SFC_DEV_CONF_STA_TYPE__2BYTE 0x1 | ||
94 | #define BV_SFC_DEV_CONF_STA_TYPE__3BYTE 0x2 | ||
95 | #define BV_SFC_DEV_CONF_STA_TYPE__4BYTE 0x3 | ||
96 | #define BF_SFC_DEV_CONF_STA_TYPE(v) (((v) & 0x3) << 13) | ||
97 | #define BFM_SFC_DEV_CONF_STA_TYPE(v) BM_SFC_DEV_CONF_STA_TYPE | ||
98 | #define BF_SFC_DEV_CONF_STA_TYPE_V(e) BF_SFC_DEV_CONF_STA_TYPE(BV_SFC_DEV_CONF_STA_TYPE__##e) | ||
99 | #define BFM_SFC_DEV_CONF_STA_TYPE_V(v) BM_SFC_DEV_CONF_STA_TYPE | ||
100 | #define BP_SFC_DEV_CONF_THOLD 11 | ||
101 | #define BM_SFC_DEV_CONF_THOLD 0x1800 | ||
102 | #define BF_SFC_DEV_CONF_THOLD(v) (((v) & 0x3) << 11) | ||
103 | #define BFM_SFC_DEV_CONF_THOLD(v) BM_SFC_DEV_CONF_THOLD | ||
104 | #define BF_SFC_DEV_CONF_THOLD_V(e) BF_SFC_DEV_CONF_THOLD(BV_SFC_DEV_CONF_THOLD__##e) | ||
105 | #define BFM_SFC_DEV_CONF_THOLD_V(v) BM_SFC_DEV_CONF_THOLD | ||
106 | #define BP_SFC_DEV_CONF_TSETUP 9 | ||
107 | #define BM_SFC_DEV_CONF_TSETUP 0x600 | ||
108 | #define BF_SFC_DEV_CONF_TSETUP(v) (((v) & 0x3) << 9) | ||
109 | #define BFM_SFC_DEV_CONF_TSETUP(v) BM_SFC_DEV_CONF_TSETUP | ||
110 | #define BF_SFC_DEV_CONF_TSETUP_V(e) BF_SFC_DEV_CONF_TSETUP(BV_SFC_DEV_CONF_TSETUP__##e) | ||
111 | #define BFM_SFC_DEV_CONF_TSETUP_V(v) BM_SFC_DEV_CONF_TSETUP | ||
112 | #define BP_SFC_DEV_CONF_TSH 5 | ||
113 | #define BM_SFC_DEV_CONF_TSH 0x1e0 | ||
114 | #define BF_SFC_DEV_CONF_TSH(v) (((v) & 0xf) << 5) | ||
115 | #define BFM_SFC_DEV_CONF_TSH(v) BM_SFC_DEV_CONF_TSH | ||
116 | #define BF_SFC_DEV_CONF_TSH_V(e) BF_SFC_DEV_CONF_TSH(BV_SFC_DEV_CONF_TSH__##e) | ||
117 | #define BFM_SFC_DEV_CONF_TSH_V(v) BM_SFC_DEV_CONF_TSH | ||
118 | #define BP_SFC_DEV_CONF_CMD_TYPE 15 | ||
119 | #define BM_SFC_DEV_CONF_CMD_TYPE 0x8000 | ||
120 | #define BV_SFC_DEV_CONF_CMD_TYPE__8BITS 0x0 | ||
121 | #define BV_SFC_DEV_CONF_CMD_TYPE__16BITS 0x1 | ||
122 | #define BF_SFC_DEV_CONF_CMD_TYPE(v) (((v) & 0x1) << 15) | ||
123 | #define BFM_SFC_DEV_CONF_CMD_TYPE(v) BM_SFC_DEV_CONF_CMD_TYPE | ||
124 | #define BF_SFC_DEV_CONF_CMD_TYPE_V(e) BF_SFC_DEV_CONF_CMD_TYPE(BV_SFC_DEV_CONF_CMD_TYPE__##e) | ||
125 | #define BFM_SFC_DEV_CONF_CMD_TYPE_V(v) BM_SFC_DEV_CONF_CMD_TYPE | ||
126 | #define BP_SFC_DEV_CONF_CPHA 4 | ||
127 | #define BM_SFC_DEV_CONF_CPHA 0x10 | ||
128 | #define BF_SFC_DEV_CONF_CPHA(v) (((v) & 0x1) << 4) | ||
129 | #define BFM_SFC_DEV_CONF_CPHA(v) BM_SFC_DEV_CONF_CPHA | ||
130 | #define BF_SFC_DEV_CONF_CPHA_V(e) BF_SFC_DEV_CONF_CPHA(BV_SFC_DEV_CONF_CPHA__##e) | ||
131 | #define BFM_SFC_DEV_CONF_CPHA_V(v) BM_SFC_DEV_CONF_CPHA | ||
132 | #define BP_SFC_DEV_CONF_CPOL 3 | ||
133 | #define BM_SFC_DEV_CONF_CPOL 0x8 | ||
134 | #define BF_SFC_DEV_CONF_CPOL(v) (((v) & 0x1) << 3) | ||
135 | #define BFM_SFC_DEV_CONF_CPOL(v) BM_SFC_DEV_CONF_CPOL | ||
136 | #define BF_SFC_DEV_CONF_CPOL_V(e) BF_SFC_DEV_CONF_CPOL(BV_SFC_DEV_CONF_CPOL__##e) | ||
137 | #define BFM_SFC_DEV_CONF_CPOL_V(v) BM_SFC_DEV_CONF_CPOL | ||
138 | #define BP_SFC_DEV_CONF_CE_DL 2 | ||
139 | #define BM_SFC_DEV_CONF_CE_DL 0x4 | ||
140 | #define BF_SFC_DEV_CONF_CE_DL(v) (((v) & 0x1) << 2) | ||
141 | #define BFM_SFC_DEV_CONF_CE_DL(v) BM_SFC_DEV_CONF_CE_DL | ||
142 | #define BF_SFC_DEV_CONF_CE_DL_V(e) BF_SFC_DEV_CONF_CE_DL(BV_SFC_DEV_CONF_CE_DL__##e) | ||
143 | #define BFM_SFC_DEV_CONF_CE_DL_V(v) BM_SFC_DEV_CONF_CE_DL | ||
144 | #define BP_SFC_DEV_CONF_HOLD_DL 1 | ||
145 | #define BM_SFC_DEV_CONF_HOLD_DL 0x2 | ||
146 | #define BF_SFC_DEV_CONF_HOLD_DL(v) (((v) & 0x1) << 1) | ||
147 | #define BFM_SFC_DEV_CONF_HOLD_DL(v) BM_SFC_DEV_CONF_HOLD_DL | ||
148 | #define BF_SFC_DEV_CONF_HOLD_DL_V(e) BF_SFC_DEV_CONF_HOLD_DL(BV_SFC_DEV_CONF_HOLD_DL__##e) | ||
149 | #define BFM_SFC_DEV_CONF_HOLD_DL_V(v) BM_SFC_DEV_CONF_HOLD_DL | ||
150 | #define BP_SFC_DEV_CONF_WP_DL 0 | ||
151 | #define BM_SFC_DEV_CONF_WP_DL 0x1 | ||
152 | #define BF_SFC_DEV_CONF_WP_DL(v) (((v) & 0x1) << 0) | ||
153 | #define BFM_SFC_DEV_CONF_WP_DL(v) BM_SFC_DEV_CONF_WP_DL | ||
154 | #define BF_SFC_DEV_CONF_WP_DL_V(e) BF_SFC_DEV_CONF_WP_DL(BV_SFC_DEV_CONF_WP_DL__##e) | ||
155 | #define BFM_SFC_DEV_CONF_WP_DL_V(v) BM_SFC_DEV_CONF_WP_DL | ||
156 | |||
157 | #define REG_SFC_DEV_STA_EXP jz_reg(SFC_DEV_STA_EXP) | ||
158 | #define JA_SFC_DEV_STA_EXP (0xb3440000 + 0x8) | ||
159 | #define JT_SFC_DEV_STA_EXP JIO_32_RW | ||
160 | #define JN_SFC_DEV_STA_EXP SFC_DEV_STA_EXP | ||
161 | #define JI_SFC_DEV_STA_EXP | ||
162 | |||
163 | #define REG_SFC_DEV_STA_RT jz_reg(SFC_DEV_STA_RT) | ||
164 | #define JA_SFC_DEV_STA_RT (0xb3440000 + 0xc) | ||
165 | #define JT_SFC_DEV_STA_RT JIO_32_RW | ||
166 | #define JN_SFC_DEV_STA_RT SFC_DEV_STA_RT | ||
167 | #define JI_SFC_DEV_STA_RT | ||
168 | |||
169 | #define REG_SFC_DEV_STA_MSK jz_reg(SFC_DEV_STA_MSK) | ||
170 | #define JA_SFC_DEV_STA_MSK (0xb3440000 + 0x10) | ||
171 | #define JT_SFC_DEV_STA_MSK JIO_32_RW | ||
172 | #define JN_SFC_DEV_STA_MSK SFC_DEV_STA_MSK | ||
173 | #define JI_SFC_DEV_STA_MSK | ||
174 | |||
175 | #define REG_SFC_TRAN_CONF(_n1) jz_reg(SFC_TRAN_CONF(_n1)) | ||
176 | #define JA_SFC_TRAN_CONF(_n1) (0xb3440000 + 0x14 + (_n1) * 0x4) | ||
177 | #define JT_SFC_TRAN_CONF(_n1) JIO_32_RW | ||
178 | #define JN_SFC_TRAN_CONF(_n1) SFC_TRAN_CONF | ||
179 | #define JI_SFC_TRAN_CONF(_n1) (_n1) | ||
180 | #define BP_SFC_TRAN_CONF_MODE 29 | ||
181 | #define BM_SFC_TRAN_CONF_MODE 0xe0000000 | ||
182 | #define BF_SFC_TRAN_CONF_MODE(v) (((v) & 0x7) << 29) | ||
183 | #define BFM_SFC_TRAN_CONF_MODE(v) BM_SFC_TRAN_CONF_MODE | ||
184 | #define BF_SFC_TRAN_CONF_MODE_V(e) BF_SFC_TRAN_CONF_MODE(BV_SFC_TRAN_CONF_MODE__##e) | ||
185 | #define BFM_SFC_TRAN_CONF_MODE_V(v) BM_SFC_TRAN_CONF_MODE | ||
186 | #define BP_SFC_TRAN_CONF_ADDR_WIDTH 26 | ||
187 | #define BM_SFC_TRAN_CONF_ADDR_WIDTH 0x1c000000 | ||
188 | #define BF_SFC_TRAN_CONF_ADDR_WIDTH(v) (((v) & 0x7) << 26) | ||
189 | #define BFM_SFC_TRAN_CONF_ADDR_WIDTH(v) BM_SFC_TRAN_CONF_ADDR_WIDTH | ||
190 | #define BF_SFC_TRAN_CONF_ADDR_WIDTH_V(e) BF_SFC_TRAN_CONF_ADDR_WIDTH(BV_SFC_TRAN_CONF_ADDR_WIDTH__##e) | ||
191 | #define BFM_SFC_TRAN_CONF_ADDR_WIDTH_V(v) BM_SFC_TRAN_CONF_ADDR_WIDTH | ||
192 | #define BP_SFC_TRAN_CONF_DUMMY_BITS 17 | ||
193 | #define BM_SFC_TRAN_CONF_DUMMY_BITS 0x7e0000 | ||
194 | #define BF_SFC_TRAN_CONF_DUMMY_BITS(v) (((v) & 0x3f) << 17) | ||
195 | #define BFM_SFC_TRAN_CONF_DUMMY_BITS(v) BM_SFC_TRAN_CONF_DUMMY_BITS | ||
196 | #define BF_SFC_TRAN_CONF_DUMMY_BITS_V(e) BF_SFC_TRAN_CONF_DUMMY_BITS(BV_SFC_TRAN_CONF_DUMMY_BITS__##e) | ||
197 | #define BFM_SFC_TRAN_CONF_DUMMY_BITS_V(v) BM_SFC_TRAN_CONF_DUMMY_BITS | ||
198 | #define BP_SFC_TRAN_CONF_COMMAND 0 | ||
199 | #define BM_SFC_TRAN_CONF_COMMAND 0xffff | ||
200 | #define BF_SFC_TRAN_CONF_COMMAND(v) (((v) & 0xffff) << 0) | ||
201 | #define BFM_SFC_TRAN_CONF_COMMAND(v) BM_SFC_TRAN_CONF_COMMAND | ||
202 | #define BF_SFC_TRAN_CONF_COMMAND_V(e) BF_SFC_TRAN_CONF_COMMAND(BV_SFC_TRAN_CONF_COMMAND__##e) | ||
203 | #define BFM_SFC_TRAN_CONF_COMMAND_V(v) BM_SFC_TRAN_CONF_COMMAND | ||
204 | #define BP_SFC_TRAN_CONF_POLL_EN 25 | ||
205 | #define BM_SFC_TRAN_CONF_POLL_EN 0x2000000 | ||
206 | #define BF_SFC_TRAN_CONF_POLL_EN(v) (((v) & 0x1) << 25) | ||
207 | #define BFM_SFC_TRAN_CONF_POLL_EN(v) BM_SFC_TRAN_CONF_POLL_EN | ||
208 | #define BF_SFC_TRAN_CONF_POLL_EN_V(e) BF_SFC_TRAN_CONF_POLL_EN(BV_SFC_TRAN_CONF_POLL_EN__##e) | ||
209 | #define BFM_SFC_TRAN_CONF_POLL_EN_V(v) BM_SFC_TRAN_CONF_POLL_EN | ||
210 | #define BP_SFC_TRAN_CONF_CMD_EN 24 | ||
211 | #define BM_SFC_TRAN_CONF_CMD_EN 0x1000000 | ||
212 | #define BF_SFC_TRAN_CONF_CMD_EN(v) (((v) & 0x1) << 24) | ||
213 | #define BFM_SFC_TRAN_CONF_CMD_EN(v) BM_SFC_TRAN_CONF_CMD_EN | ||
214 | #define BF_SFC_TRAN_CONF_CMD_EN_V(e) BF_SFC_TRAN_CONF_CMD_EN(BV_SFC_TRAN_CONF_CMD_EN__##e) | ||
215 | #define BFM_SFC_TRAN_CONF_CMD_EN_V(v) BM_SFC_TRAN_CONF_CMD_EN | ||
216 | #define BP_SFC_TRAN_CONF_PHASE_FMT 23 | ||
217 | #define BM_SFC_TRAN_CONF_PHASE_FMT 0x800000 | ||
218 | #define BF_SFC_TRAN_CONF_PHASE_FMT(v) (((v) & 0x1) << 23) | ||
219 | #define BFM_SFC_TRAN_CONF_PHASE_FMT(v) BM_SFC_TRAN_CONF_PHASE_FMT | ||
220 | #define BF_SFC_TRAN_CONF_PHASE_FMT_V(e) BF_SFC_TRAN_CONF_PHASE_FMT(BV_SFC_TRAN_CONF_PHASE_FMT__##e) | ||
221 | #define BFM_SFC_TRAN_CONF_PHASE_FMT_V(v) BM_SFC_TRAN_CONF_PHASE_FMT | ||
222 | #define BP_SFC_TRAN_CONF_DATA_EN 16 | ||
223 | #define BM_SFC_TRAN_CONF_DATA_EN 0x10000 | ||
224 | #define BF_SFC_TRAN_CONF_DATA_EN(v) (((v) & 0x1) << 16) | ||
225 | #define BFM_SFC_TRAN_CONF_DATA_EN(v) BM_SFC_TRAN_CONF_DATA_EN | ||
226 | #define BF_SFC_TRAN_CONF_DATA_EN_V(e) BF_SFC_TRAN_CONF_DATA_EN(BV_SFC_TRAN_CONF_DATA_EN__##e) | ||
227 | #define BFM_SFC_TRAN_CONF_DATA_EN_V(v) BM_SFC_TRAN_CONF_DATA_EN | ||
228 | |||
229 | #define REG_SFC_TRAN_LENGTH jz_reg(SFC_TRAN_LENGTH) | ||
230 | #define JA_SFC_TRAN_LENGTH (0xb3440000 + 0x2c) | ||
231 | #define JT_SFC_TRAN_LENGTH JIO_32_RW | ||
232 | #define JN_SFC_TRAN_LENGTH SFC_TRAN_LENGTH | ||
233 | #define JI_SFC_TRAN_LENGTH | ||
234 | |||
235 | #define REG_SFC_DEV_ADDR(_n1) jz_reg(SFC_DEV_ADDR(_n1)) | ||
236 | #define JA_SFC_DEV_ADDR(_n1) (0xb3440000 + 0x30 + (_n1) * 0x4) | ||
237 | #define JT_SFC_DEV_ADDR(_n1) JIO_32_RW | ||
238 | #define JN_SFC_DEV_ADDR(_n1) SFC_DEV_ADDR | ||
239 | #define JI_SFC_DEV_ADDR(_n1) (_n1) | ||
240 | |||
241 | #define REG_SFC_DEV_PLUS(_n1) jz_reg(SFC_DEV_PLUS(_n1)) | ||
242 | #define JA_SFC_DEV_PLUS(_n1) (0xb3440000 + 0x48 + (_n1) * 0x40) | ||
243 | #define JT_SFC_DEV_PLUS(_n1) JIO_32_RW | ||
244 | #define JN_SFC_DEV_PLUS(_n1) SFC_DEV_PLUS | ||
245 | #define JI_SFC_DEV_PLUS(_n1) (_n1) | ||
246 | |||
247 | #define REG_SFC_MEM_ADDR jz_reg(SFC_MEM_ADDR) | ||
248 | #define JA_SFC_MEM_ADDR (0xb3440000 + 0x60) | ||
249 | #define JT_SFC_MEM_ADDR JIO_32_RW | ||
250 | #define JN_SFC_MEM_ADDR SFC_MEM_ADDR | ||
251 | #define JI_SFC_MEM_ADDR | ||
252 | |||
253 | #define REG_SFC_TRIG jz_reg(SFC_TRIG) | ||
254 | #define JA_SFC_TRIG (0xb3440000 + 0x64) | ||
255 | #define JT_SFC_TRIG JIO_32_RW | ||
256 | #define JN_SFC_TRIG SFC_TRIG | ||
257 | #define JI_SFC_TRIG | ||
258 | #define BP_SFC_TRIG_FLUSH 2 | ||
259 | #define BM_SFC_TRIG_FLUSH 0x4 | ||
260 | #define BF_SFC_TRIG_FLUSH(v) (((v) & 0x1) << 2) | ||
261 | #define BFM_SFC_TRIG_FLUSH(v) BM_SFC_TRIG_FLUSH | ||
262 | #define BF_SFC_TRIG_FLUSH_V(e) BF_SFC_TRIG_FLUSH(BV_SFC_TRIG_FLUSH__##e) | ||
263 | #define BFM_SFC_TRIG_FLUSH_V(v) BM_SFC_TRIG_FLUSH | ||
264 | #define BP_SFC_TRIG_STOP 1 | ||
265 | #define BM_SFC_TRIG_STOP 0x2 | ||
266 | #define BF_SFC_TRIG_STOP(v) (((v) & 0x1) << 1) | ||
267 | #define BFM_SFC_TRIG_STOP(v) BM_SFC_TRIG_STOP | ||
268 | #define BF_SFC_TRIG_STOP_V(e) BF_SFC_TRIG_STOP(BV_SFC_TRIG_STOP__##e) | ||
269 | #define BFM_SFC_TRIG_STOP_V(v) BM_SFC_TRIG_STOP | ||
270 | #define BP_SFC_TRIG_START 0 | ||
271 | #define BM_SFC_TRIG_START 0x1 | ||
272 | #define BF_SFC_TRIG_START(v) (((v) & 0x1) << 0) | ||
273 | #define BFM_SFC_TRIG_START(v) BM_SFC_TRIG_START | ||
274 | #define BF_SFC_TRIG_START_V(e) BF_SFC_TRIG_START(BV_SFC_TRIG_START__##e) | ||
275 | #define BFM_SFC_TRIG_START_V(v) BM_SFC_TRIG_START | ||
276 | |||
277 | #define REG_SFC_SR jz_reg(SFC_SR) | ||
278 | #define JA_SFC_SR (0xb3440000 + 0x68) | ||
279 | #define JT_SFC_SR JIO_32_RW | ||
280 | #define JN_SFC_SR SFC_SR | ||
281 | #define JI_SFC_SR | ||
282 | #define BP_SFC_SR_FIFO_NUM 16 | ||
283 | #define BM_SFC_SR_FIFO_NUM 0x7f0000 | ||
284 | #define BF_SFC_SR_FIFO_NUM(v) (((v) & 0x7f) << 16) | ||
285 | #define BFM_SFC_SR_FIFO_NUM(v) BM_SFC_SR_FIFO_NUM | ||
286 | #define BF_SFC_SR_FIFO_NUM_V(e) BF_SFC_SR_FIFO_NUM(BV_SFC_SR_FIFO_NUM__##e) | ||
287 | #define BFM_SFC_SR_FIFO_NUM_V(v) BM_SFC_SR_FIFO_NUM | ||
288 | #define BP_SFC_SR_BUSY 5 | ||
289 | #define BM_SFC_SR_BUSY 0x60 | ||
290 | #define BF_SFC_SR_BUSY(v) (((v) & 0x3) << 5) | ||
291 | #define BFM_SFC_SR_BUSY(v) BM_SFC_SR_BUSY | ||
292 | #define BF_SFC_SR_BUSY_V(e) BF_SFC_SR_BUSY(BV_SFC_SR_BUSY__##e) | ||
293 | #define BFM_SFC_SR_BUSY_V(v) BM_SFC_SR_BUSY | ||
294 | #define BP_SFC_SR_END 4 | ||
295 | #define BM_SFC_SR_END 0x10 | ||
296 | #define BF_SFC_SR_END(v) (((v) & 0x1) << 4) | ||
297 | #define BFM_SFC_SR_END(v) BM_SFC_SR_END | ||
298 | #define BF_SFC_SR_END_V(e) BF_SFC_SR_END(BV_SFC_SR_END__##e) | ||
299 | #define BFM_SFC_SR_END_V(v) BM_SFC_SR_END | ||
300 | #define BP_SFC_SR_TREQ 3 | ||
301 | #define BM_SFC_SR_TREQ 0x8 | ||
302 | #define BF_SFC_SR_TREQ(v) (((v) & 0x1) << 3) | ||
303 | #define BFM_SFC_SR_TREQ(v) BM_SFC_SR_TREQ | ||
304 | #define BF_SFC_SR_TREQ_V(e) BF_SFC_SR_TREQ(BV_SFC_SR_TREQ__##e) | ||
305 | #define BFM_SFC_SR_TREQ_V(v) BM_SFC_SR_TREQ | ||
306 | #define BP_SFC_SR_RREQ 2 | ||
307 | #define BM_SFC_SR_RREQ 0x4 | ||
308 | #define BF_SFC_SR_RREQ(v) (((v) & 0x1) << 2) | ||
309 | #define BFM_SFC_SR_RREQ(v) BM_SFC_SR_RREQ | ||
310 | #define BF_SFC_SR_RREQ_V(e) BF_SFC_SR_RREQ(BV_SFC_SR_RREQ__##e) | ||
311 | #define BFM_SFC_SR_RREQ_V(v) BM_SFC_SR_RREQ | ||
312 | #define BP_SFC_SR_OVER 1 | ||
313 | #define BM_SFC_SR_OVER 0x2 | ||
314 | #define BF_SFC_SR_OVER(v) (((v) & 0x1) << 1) | ||
315 | #define BFM_SFC_SR_OVER(v) BM_SFC_SR_OVER | ||
316 | #define BF_SFC_SR_OVER_V(e) BF_SFC_SR_OVER(BV_SFC_SR_OVER__##e) | ||
317 | #define BFM_SFC_SR_OVER_V(v) BM_SFC_SR_OVER | ||
318 | #define BP_SFC_SR_UNDER 0 | ||
319 | #define BM_SFC_SR_UNDER 0x1 | ||
320 | #define BF_SFC_SR_UNDER(v) (((v) & 0x1) << 0) | ||
321 | #define BFM_SFC_SR_UNDER(v) BM_SFC_SR_UNDER | ||
322 | #define BF_SFC_SR_UNDER_V(e) BF_SFC_SR_UNDER(BV_SFC_SR_UNDER__##e) | ||
323 | #define BFM_SFC_SR_UNDER_V(v) BM_SFC_SR_UNDER | ||
324 | |||
325 | #define REG_SFC_SCR jz_reg(SFC_SCR) | ||
326 | #define JA_SFC_SCR (0xb3440000 + 0x6c) | ||
327 | #define JT_SFC_SCR JIO_32_RW | ||
328 | #define JN_SFC_SCR SFC_SCR | ||
329 | #define JI_SFC_SCR | ||
330 | #define BP_SFC_SCR_CLR_END 4 | ||
331 | #define BM_SFC_SCR_CLR_END 0x10 | ||
332 | #define BF_SFC_SCR_CLR_END(v) (((v) & 0x1) << 4) | ||
333 | #define BFM_SFC_SCR_CLR_END(v) BM_SFC_SCR_CLR_END | ||
334 | #define BF_SFC_SCR_CLR_END_V(e) BF_SFC_SCR_CLR_END(BV_SFC_SCR_CLR_END__##e) | ||
335 | #define BFM_SFC_SCR_CLR_END_V(v) BM_SFC_SCR_CLR_END | ||
336 | #define BP_SFC_SCR_CLR_TREQ 3 | ||
337 | #define BM_SFC_SCR_CLR_TREQ 0x8 | ||
338 | #define BF_SFC_SCR_CLR_TREQ(v) (((v) & 0x1) << 3) | ||
339 | #define BFM_SFC_SCR_CLR_TREQ(v) BM_SFC_SCR_CLR_TREQ | ||
340 | #define BF_SFC_SCR_CLR_TREQ_V(e) BF_SFC_SCR_CLR_TREQ(BV_SFC_SCR_CLR_TREQ__##e) | ||
341 | #define BFM_SFC_SCR_CLR_TREQ_V(v) BM_SFC_SCR_CLR_TREQ | ||
342 | #define BP_SFC_SCR_CLR_RREQ 2 | ||
343 | #define BM_SFC_SCR_CLR_RREQ 0x4 | ||
344 | #define BF_SFC_SCR_CLR_RREQ(v) (((v) & 0x1) << 2) | ||
345 | #define BFM_SFC_SCR_CLR_RREQ(v) BM_SFC_SCR_CLR_RREQ | ||
346 | #define BF_SFC_SCR_CLR_RREQ_V(e) BF_SFC_SCR_CLR_RREQ(BV_SFC_SCR_CLR_RREQ__##e) | ||
347 | #define BFM_SFC_SCR_CLR_RREQ_V(v) BM_SFC_SCR_CLR_RREQ | ||
348 | #define BP_SFC_SCR_CLR_OVER 1 | ||
349 | #define BM_SFC_SCR_CLR_OVER 0x2 | ||
350 | #define BF_SFC_SCR_CLR_OVER(v) (((v) & 0x1) << 1) | ||
351 | #define BFM_SFC_SCR_CLR_OVER(v) BM_SFC_SCR_CLR_OVER | ||
352 | #define BF_SFC_SCR_CLR_OVER_V(e) BF_SFC_SCR_CLR_OVER(BV_SFC_SCR_CLR_OVER__##e) | ||
353 | #define BFM_SFC_SCR_CLR_OVER_V(v) BM_SFC_SCR_CLR_OVER | ||
354 | #define BP_SFC_SCR_CLR_UNDER 0 | ||
355 | #define BM_SFC_SCR_CLR_UNDER 0x1 | ||
356 | #define BF_SFC_SCR_CLR_UNDER(v) (((v) & 0x1) << 0) | ||
357 | #define BFM_SFC_SCR_CLR_UNDER(v) BM_SFC_SCR_CLR_UNDER | ||
358 | #define BF_SFC_SCR_CLR_UNDER_V(e) BF_SFC_SCR_CLR_UNDER(BV_SFC_SCR_CLR_UNDER__##e) | ||
359 | #define BFM_SFC_SCR_CLR_UNDER_V(v) BM_SFC_SCR_CLR_UNDER | ||
360 | |||
361 | #define REG_SFC_INTC jz_reg(SFC_INTC) | ||
362 | #define JA_SFC_INTC (0xb3440000 + 0x70) | ||
363 | #define JT_SFC_INTC JIO_32_RW | ||
364 | #define JN_SFC_INTC SFC_INTC | ||
365 | #define JI_SFC_INTC | ||
366 | #define BP_SFC_INTC_MSK_END 4 | ||
367 | #define BM_SFC_INTC_MSK_END 0x10 | ||
368 | #define BF_SFC_INTC_MSK_END(v) (((v) & 0x1) << 4) | ||
369 | #define BFM_SFC_INTC_MSK_END(v) BM_SFC_INTC_MSK_END | ||
370 | #define BF_SFC_INTC_MSK_END_V(e) BF_SFC_INTC_MSK_END(BV_SFC_INTC_MSK_END__##e) | ||
371 | #define BFM_SFC_INTC_MSK_END_V(v) BM_SFC_INTC_MSK_END | ||
372 | #define BP_SFC_INTC_MSK_TREQ 3 | ||
373 | #define BM_SFC_INTC_MSK_TREQ 0x8 | ||
374 | #define BF_SFC_INTC_MSK_TREQ(v) (((v) & 0x1) << 3) | ||
375 | #define BFM_SFC_INTC_MSK_TREQ(v) BM_SFC_INTC_MSK_TREQ | ||
376 | #define BF_SFC_INTC_MSK_TREQ_V(e) BF_SFC_INTC_MSK_TREQ(BV_SFC_INTC_MSK_TREQ__##e) | ||
377 | #define BFM_SFC_INTC_MSK_TREQ_V(v) BM_SFC_INTC_MSK_TREQ | ||
378 | #define BP_SFC_INTC_MSK_RREQ 2 | ||
379 | #define BM_SFC_INTC_MSK_RREQ 0x4 | ||
380 | #define BF_SFC_INTC_MSK_RREQ(v) (((v) & 0x1) << 2) | ||
381 | #define BFM_SFC_INTC_MSK_RREQ(v) BM_SFC_INTC_MSK_RREQ | ||
382 | #define BF_SFC_INTC_MSK_RREQ_V(e) BF_SFC_INTC_MSK_RREQ(BV_SFC_INTC_MSK_RREQ__##e) | ||
383 | #define BFM_SFC_INTC_MSK_RREQ_V(v) BM_SFC_INTC_MSK_RREQ | ||
384 | #define BP_SFC_INTC_MSK_OVER 1 | ||
385 | #define BM_SFC_INTC_MSK_OVER 0x2 | ||
386 | #define BF_SFC_INTC_MSK_OVER(v) (((v) & 0x1) << 1) | ||
387 | #define BFM_SFC_INTC_MSK_OVER(v) BM_SFC_INTC_MSK_OVER | ||
388 | #define BF_SFC_INTC_MSK_OVER_V(e) BF_SFC_INTC_MSK_OVER(BV_SFC_INTC_MSK_OVER__##e) | ||
389 | #define BFM_SFC_INTC_MSK_OVER_V(v) BM_SFC_INTC_MSK_OVER | ||
390 | #define BP_SFC_INTC_MSK_UNDER 0 | ||
391 | #define BM_SFC_INTC_MSK_UNDER 0x1 | ||
392 | #define BF_SFC_INTC_MSK_UNDER(v) (((v) & 0x1) << 0) | ||
393 | #define BFM_SFC_INTC_MSK_UNDER(v) BM_SFC_INTC_MSK_UNDER | ||
394 | #define BF_SFC_INTC_MSK_UNDER_V(e) BF_SFC_INTC_MSK_UNDER(BV_SFC_INTC_MSK_UNDER__##e) | ||
395 | #define BFM_SFC_INTC_MSK_UNDER_V(v) BM_SFC_INTC_MSK_UNDER | ||
396 | |||
397 | #define REG_SFC_FSM jz_reg(SFC_FSM) | ||
398 | #define JA_SFC_FSM (0xb3440000 + 0x74) | ||
399 | #define JT_SFC_FSM JIO_32_RW | ||
400 | #define JN_SFC_FSM SFC_FSM | ||
401 | #define JI_SFC_FSM | ||
402 | #define BP_SFC_FSM_STATE_AHB 16 | ||
403 | #define BM_SFC_FSM_STATE_AHB 0xf0000 | ||
404 | #define BF_SFC_FSM_STATE_AHB(v) (((v) & 0xf) << 16) | ||
405 | #define BFM_SFC_FSM_STATE_AHB(v) BM_SFC_FSM_STATE_AHB | ||
406 | #define BF_SFC_FSM_STATE_AHB_V(e) BF_SFC_FSM_STATE_AHB(BV_SFC_FSM_STATE_AHB__##e) | ||
407 | #define BFM_SFC_FSM_STATE_AHB_V(v) BM_SFC_FSM_STATE_AHB | ||
408 | #define BP_SFC_FSM_STATE_SPI 11 | ||
409 | #define BM_SFC_FSM_STATE_SPI 0xf800 | ||
410 | #define BF_SFC_FSM_STATE_SPI(v) (((v) & 0x1f) << 11) | ||
411 | #define BFM_SFC_FSM_STATE_SPI(v) BM_SFC_FSM_STATE_SPI | ||
412 | #define BF_SFC_FSM_STATE_SPI_V(e) BF_SFC_FSM_STATE_SPI(BV_SFC_FSM_STATE_SPI__##e) | ||
413 | #define BFM_SFC_FSM_STATE_SPI_V(v) BM_SFC_FSM_STATE_SPI | ||
414 | #define BP_SFC_FSM_STATE_CLK 6 | ||
415 | #define BM_SFC_FSM_STATE_CLK 0x3c0 | ||
416 | #define BF_SFC_FSM_STATE_CLK(v) (((v) & 0xf) << 6) | ||
417 | #define BFM_SFC_FSM_STATE_CLK(v) BM_SFC_FSM_STATE_CLK | ||
418 | #define BF_SFC_FSM_STATE_CLK_V(e) BF_SFC_FSM_STATE_CLK(BV_SFC_FSM_STATE_CLK__##e) | ||
419 | #define BFM_SFC_FSM_STATE_CLK_V(v) BM_SFC_FSM_STATE_CLK | ||
420 | #define BP_SFC_FSM_STATE_DMAC 3 | ||
421 | #define BM_SFC_FSM_STATE_DMAC 0x38 | ||
422 | #define BF_SFC_FSM_STATE_DMAC(v) (((v) & 0x7) << 3) | ||
423 | #define BFM_SFC_FSM_STATE_DMAC(v) BM_SFC_FSM_STATE_DMAC | ||
424 | #define BF_SFC_FSM_STATE_DMAC_V(e) BF_SFC_FSM_STATE_DMAC(BV_SFC_FSM_STATE_DMAC__##e) | ||
425 | #define BFM_SFC_FSM_STATE_DMAC_V(v) BM_SFC_FSM_STATE_DMAC | ||
426 | #define BP_SFC_FSM_STATE_RMC 0 | ||
427 | #define BM_SFC_FSM_STATE_RMC 0x7 | ||
428 | #define BF_SFC_FSM_STATE_RMC(v) (((v) & 0x7) << 0) | ||
429 | #define BFM_SFC_FSM_STATE_RMC(v) BM_SFC_FSM_STATE_RMC | ||
430 | #define BF_SFC_FSM_STATE_RMC_V(e) BF_SFC_FSM_STATE_RMC(BV_SFC_FSM_STATE_RMC__##e) | ||
431 | #define BFM_SFC_FSM_STATE_RMC_V(v) BM_SFC_FSM_STATE_RMC | ||
432 | |||
433 | #define REG_SFC_CGE jz_reg(SFC_CGE) | ||
434 | #define JA_SFC_CGE (0xb3440000 + 0x78) | ||
435 | #define JT_SFC_CGE JIO_32_RW | ||
436 | #define JN_SFC_CGE SFC_CGE | ||
437 | #define JI_SFC_CGE | ||
438 | #define BP_SFC_CGE_SFC 5 | ||
439 | #define BM_SFC_CGE_SFC 0x20 | ||
440 | #define BF_SFC_CGE_SFC(v) (((v) & 0x1) << 5) | ||
441 | #define BFM_SFC_CGE_SFC(v) BM_SFC_CGE_SFC | ||
442 | #define BF_SFC_CGE_SFC_V(e) BF_SFC_CGE_SFC(BV_SFC_CGE_SFC__##e) | ||
443 | #define BFM_SFC_CGE_SFC_V(v) BM_SFC_CGE_SFC | ||
444 | #define BP_SFC_CGE_FIFO 4 | ||
445 | #define BM_SFC_CGE_FIFO 0x10 | ||
446 | #define BF_SFC_CGE_FIFO(v) (((v) & 0x1) << 4) | ||
447 | #define BFM_SFC_CGE_FIFO(v) BM_SFC_CGE_FIFO | ||
448 | #define BF_SFC_CGE_FIFO_V(e) BF_SFC_CGE_FIFO(BV_SFC_CGE_FIFO__##e) | ||
449 | #define BFM_SFC_CGE_FIFO_V(v) BM_SFC_CGE_FIFO | ||
450 | #define BP_SFC_CGE_DMA 3 | ||
451 | #define BM_SFC_CGE_DMA 0x8 | ||
452 | #define BF_SFC_CGE_DMA(v) (((v) & 0x1) << 3) | ||
453 | #define BFM_SFC_CGE_DMA(v) BM_SFC_CGE_DMA | ||
454 | #define BF_SFC_CGE_DMA_V(e) BF_SFC_CGE_DMA(BV_SFC_CGE_DMA__##e) | ||
455 | #define BFM_SFC_CGE_DMA_V(v) BM_SFC_CGE_DMA | ||
456 | #define BP_SFC_CGE_RMC 2 | ||
457 | #define BM_SFC_CGE_RMC 0x4 | ||
458 | #define BF_SFC_CGE_RMC(v) (((v) & 0x1) << 2) | ||
459 | #define BFM_SFC_CGE_RMC(v) BM_SFC_CGE_RMC | ||
460 | #define BF_SFC_CGE_RMC_V(e) BF_SFC_CGE_RMC(BV_SFC_CGE_RMC__##e) | ||
461 | #define BFM_SFC_CGE_RMC_V(v) BM_SFC_CGE_RMC | ||
462 | #define BP_SFC_CGE_SPI 1 | ||
463 | #define BM_SFC_CGE_SPI 0x2 | ||
464 | #define BF_SFC_CGE_SPI(v) (((v) & 0x1) << 1) | ||
465 | #define BFM_SFC_CGE_SPI(v) BM_SFC_CGE_SPI | ||
466 | #define BF_SFC_CGE_SPI_V(e) BF_SFC_CGE_SPI(BV_SFC_CGE_SPI__##e) | ||
467 | #define BFM_SFC_CGE_SPI_V(v) BM_SFC_CGE_SPI | ||
468 | #define BP_SFC_CGE_REG 0 | ||
469 | #define BM_SFC_CGE_REG 0x1 | ||
470 | #define BF_SFC_CGE_REG(v) (((v) & 0x1) << 0) | ||
471 | #define BFM_SFC_CGE_REG(v) BM_SFC_CGE_REG | ||
472 | #define BF_SFC_CGE_REG_V(e) BF_SFC_CGE_REG(BV_SFC_CGE_REG__##e) | ||
473 | #define BFM_SFC_CGE_REG_V(v) BM_SFC_CGE_REG | ||
474 | |||
475 | #define REG_SFC_DATA jz_reg(SFC_DATA) | ||
476 | #define JA_SFC_DATA (0xb3440000 + 0x1000) | ||
477 | #define JT_SFC_DATA JIO_32_RW | ||
478 | #define JN_SFC_DATA SFC_DATA | ||
479 | #define JI_SFC_DATA | ||
480 | |||
481 | #endif /* __HEADERGEN_SFC_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/tcu.h b/firmware/target/mips/ingenic_x1000/x1000/tcu.h new file mode 100644 index 0000000000..9f00692660 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/tcu.h | |||
@@ -0,0 +1,192 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_TCU_H__ | ||
25 | #define __HEADERGEN_TCU_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_TCU_STATUS jz_reg(TCU_STATUS) | ||
30 | #define JA_TCU_STATUS (0xb0002000 + 0xf0) | ||
31 | #define JT_TCU_STATUS JIO_32_RW | ||
32 | #define JN_TCU_STATUS TCU_STATUS | ||
33 | #define JI_TCU_STATUS | ||
34 | #define REG_TCU_STATUS_SET jz_reg(TCU_STATUS_SET) | ||
35 | #define JA_TCU_STATUS_SET (JA_TCU_STATUS + 0x4) | ||
36 | #define JT_TCU_STATUS_SET JIO_32_WO | ||
37 | #define JN_TCU_STATUS_SET TCU_STATUS | ||
38 | #define JI_TCU_STATUS_SET | ||
39 | #define REG_TCU_STATUS_CLR jz_reg(TCU_STATUS_CLR) | ||
40 | #define JA_TCU_STATUS_CLR (JA_TCU_STATUS + 0x8) | ||
41 | #define JT_TCU_STATUS_CLR JIO_32_WO | ||
42 | #define JN_TCU_STATUS_CLR TCU_STATUS | ||
43 | #define JI_TCU_STATUS_CLR | ||
44 | |||
45 | #define REG_TCU_STOP jz_reg(TCU_STOP) | ||
46 | #define JA_TCU_STOP (0xb0002000 + 0x1c) | ||
47 | #define JT_TCU_STOP JIO_32_RW | ||
48 | #define JN_TCU_STOP TCU_STOP | ||
49 | #define JI_TCU_STOP | ||
50 | #define REG_TCU_STOP_SET jz_reg(TCU_STOP_SET) | ||
51 | #define JA_TCU_STOP_SET (JA_TCU_STOP + 0x10) | ||
52 | #define JT_TCU_STOP_SET JIO_32_WO | ||
53 | #define JN_TCU_STOP_SET TCU_STOP | ||
54 | #define JI_TCU_STOP_SET | ||
55 | #define REG_TCU_STOP_CLR jz_reg(TCU_STOP_CLR) | ||
56 | #define JA_TCU_STOP_CLR (JA_TCU_STOP + 0x20) | ||
57 | #define JT_TCU_STOP_CLR JIO_32_WO | ||
58 | #define JN_TCU_STOP_CLR TCU_STOP | ||
59 | #define JI_TCU_STOP_CLR | ||
60 | |||
61 | #define REG_TCU_ENABLE jz_reg(TCU_ENABLE) | ||
62 | #define JA_TCU_ENABLE (0xb0002000 + 0x10) | ||
63 | #define JT_TCU_ENABLE JIO_32_RW | ||
64 | #define JN_TCU_ENABLE TCU_ENABLE | ||
65 | #define JI_TCU_ENABLE | ||
66 | #define REG_TCU_ENABLE_SET jz_reg(TCU_ENABLE_SET) | ||
67 | #define JA_TCU_ENABLE_SET (JA_TCU_ENABLE + 0x4) | ||
68 | #define JT_TCU_ENABLE_SET JIO_32_WO | ||
69 | #define JN_TCU_ENABLE_SET TCU_ENABLE | ||
70 | #define JI_TCU_ENABLE_SET | ||
71 | #define REG_TCU_ENABLE_CLR jz_reg(TCU_ENABLE_CLR) | ||
72 | #define JA_TCU_ENABLE_CLR (JA_TCU_ENABLE + 0x8) | ||
73 | #define JT_TCU_ENABLE_CLR JIO_32_WO | ||
74 | #define JN_TCU_ENABLE_CLR TCU_ENABLE | ||
75 | #define JI_TCU_ENABLE_CLR | ||
76 | |||
77 | #define REG_TCU_FLAG jz_reg(TCU_FLAG) | ||
78 | #define JA_TCU_FLAG (0xb0002000 + 0x20) | ||
79 | #define JT_TCU_FLAG JIO_32_RW | ||
80 | #define JN_TCU_FLAG TCU_FLAG | ||
81 | #define JI_TCU_FLAG | ||
82 | #define REG_TCU_FLAG_SET jz_reg(TCU_FLAG_SET) | ||
83 | #define JA_TCU_FLAG_SET (JA_TCU_FLAG + 0x4) | ||
84 | #define JT_TCU_FLAG_SET JIO_32_WO | ||
85 | #define JN_TCU_FLAG_SET TCU_FLAG | ||
86 | #define JI_TCU_FLAG_SET | ||
87 | #define REG_TCU_FLAG_CLR jz_reg(TCU_FLAG_CLR) | ||
88 | #define JA_TCU_FLAG_CLR (JA_TCU_FLAG + 0x8) | ||
89 | #define JT_TCU_FLAG_CLR JIO_32_WO | ||
90 | #define JN_TCU_FLAG_CLR TCU_FLAG | ||
91 | #define JI_TCU_FLAG_CLR | ||
92 | |||
93 | #define REG_TCU_MASK jz_reg(TCU_MASK) | ||
94 | #define JA_TCU_MASK (0xb0002000 + 0x30) | ||
95 | #define JT_TCU_MASK JIO_32_RW | ||
96 | #define JN_TCU_MASK TCU_MASK | ||
97 | #define JI_TCU_MASK | ||
98 | #define REG_TCU_MASK_SET jz_reg(TCU_MASK_SET) | ||
99 | #define JA_TCU_MASK_SET (JA_TCU_MASK + 0x4) | ||
100 | #define JT_TCU_MASK_SET JIO_32_WO | ||
101 | #define JN_TCU_MASK_SET TCU_MASK | ||
102 | #define JI_TCU_MASK_SET | ||
103 | #define REG_TCU_MASK_CLR jz_reg(TCU_MASK_CLR) | ||
104 | #define JA_TCU_MASK_CLR (JA_TCU_MASK + 0x8) | ||
105 | #define JT_TCU_MASK_CLR JIO_32_WO | ||
106 | #define JN_TCU_MASK_CLR TCU_MASK | ||
107 | #define JI_TCU_MASK_CLR | ||
108 | |||
109 | #define REG_TCU_CMP_FULL(_n1) jz_reg(TCU_CMP_FULL(_n1)) | ||
110 | #define JA_TCU_CMP_FULL(_n1) (0xb0002000 + 0x40 + (_n1) * 0x10) | ||
111 | #define JT_TCU_CMP_FULL(_n1) JIO_32_RW | ||
112 | #define JN_TCU_CMP_FULL(_n1) TCU_CMP_FULL | ||
113 | #define JI_TCU_CMP_FULL(_n1) (_n1) | ||
114 | |||
115 | #define REG_TCU_CMP_HALF(_n1) jz_reg(TCU_CMP_HALF(_n1)) | ||
116 | #define JA_TCU_CMP_HALF(_n1) (0xb0002000 + 0x44 + (_n1) * 0x10) | ||
117 | #define JT_TCU_CMP_HALF(_n1) JIO_32_RW | ||
118 | #define JN_TCU_CMP_HALF(_n1) TCU_CMP_HALF | ||
119 | #define JI_TCU_CMP_HALF(_n1) (_n1) | ||
120 | |||
121 | #define REG_TCU_COUNT(_n1) jz_reg(TCU_COUNT(_n1)) | ||
122 | #define JA_TCU_COUNT(_n1) (0xb0002000 + 0x48 + (_n1) * 0x10) | ||
123 | #define JT_TCU_COUNT(_n1) JIO_32_RW | ||
124 | #define JN_TCU_COUNT(_n1) TCU_COUNT | ||
125 | #define JI_TCU_COUNT(_n1) (_n1) | ||
126 | |||
127 | #define REG_TCU_CTRL(_n1) jz_reg(TCU_CTRL(_n1)) | ||
128 | #define JA_TCU_CTRL(_n1) (0xb0002000 + 0x4c + (_n1) * 0x10) | ||
129 | #define JT_TCU_CTRL(_n1) JIO_32_RW | ||
130 | #define JN_TCU_CTRL(_n1) TCU_CTRL | ||
131 | #define JI_TCU_CTRL(_n1) (_n1) | ||
132 | #define BP_TCU_CTRL_PRESCALE 3 | ||
133 | #define BM_TCU_CTRL_PRESCALE 0x38 | ||
134 | #define BV_TCU_CTRL_PRESCALE__BY_1 0x0 | ||
135 | #define BV_TCU_CTRL_PRESCALE__BY_4 0x1 | ||
136 | #define BV_TCU_CTRL_PRESCALE__BY_16 0x2 | ||
137 | #define BV_TCU_CTRL_PRESCALE__BY_64 0x3 | ||
138 | #define BV_TCU_CTRL_PRESCALE__BY_256 0x4 | ||
139 | #define BV_TCU_CTRL_PRESCALE__BY_1024 0x5 | ||
140 | #define BF_TCU_CTRL_PRESCALE(v) (((v) & 0x7) << 3) | ||
141 | #define BFM_TCU_CTRL_PRESCALE(v) BM_TCU_CTRL_PRESCALE | ||
142 | #define BF_TCU_CTRL_PRESCALE_V(e) BF_TCU_CTRL_PRESCALE(BV_TCU_CTRL_PRESCALE__##e) | ||
143 | #define BFM_TCU_CTRL_PRESCALE_V(v) BM_TCU_CTRL_PRESCALE | ||
144 | #define BP_TCU_CTRL_SOURCE 0 | ||
145 | #define BM_TCU_CTRL_SOURCE 0x7 | ||
146 | #define BV_TCU_CTRL_SOURCE__EXT 0x4 | ||
147 | #define BV_TCU_CTRL_SOURCE__RTC 0x2 | ||
148 | #define BV_TCU_CTRL_SOURCE__PCLK 0x1 | ||
149 | #define BF_TCU_CTRL_SOURCE(v) (((v) & 0x7) << 0) | ||
150 | #define BFM_TCU_CTRL_SOURCE(v) BM_TCU_CTRL_SOURCE | ||
151 | #define BF_TCU_CTRL_SOURCE_V(e) BF_TCU_CTRL_SOURCE(BV_TCU_CTRL_SOURCE__##e) | ||
152 | #define BFM_TCU_CTRL_SOURCE_V(v) BM_TCU_CTRL_SOURCE | ||
153 | #define BP_TCU_CTRL_BYPASS 11 | ||
154 | #define BM_TCU_CTRL_BYPASS 0x800 | ||
155 | #define BF_TCU_CTRL_BYPASS(v) (((v) & 0x1) << 11) | ||
156 | #define BFM_TCU_CTRL_BYPASS(v) BM_TCU_CTRL_BYPASS | ||
157 | #define BF_TCU_CTRL_BYPASS_V(e) BF_TCU_CTRL_BYPASS(BV_TCU_CTRL_BYPASS__##e) | ||
158 | #define BFM_TCU_CTRL_BYPASS_V(v) BM_TCU_CTRL_BYPASS | ||
159 | #define BP_TCU_CTRL_CLRZ 10 | ||
160 | #define BM_TCU_CTRL_CLRZ 0x400 | ||
161 | #define BF_TCU_CTRL_CLRZ(v) (((v) & 0x1) << 10) | ||
162 | #define BFM_TCU_CTRL_CLRZ(v) BM_TCU_CTRL_CLRZ | ||
163 | #define BF_TCU_CTRL_CLRZ_V(e) BF_TCU_CTRL_CLRZ(BV_TCU_CTRL_CLRZ__##e) | ||
164 | #define BFM_TCU_CTRL_CLRZ_V(v) BM_TCU_CTRL_CLRZ | ||
165 | #define BP_TCU_CTRL_SHUTDOWN 9 | ||
166 | #define BM_TCU_CTRL_SHUTDOWN 0x200 | ||
167 | #define BV_TCU_CTRL_SHUTDOWN__GRACEFUL 0x0 | ||
168 | #define BV_TCU_CTRL_SHUTDOWN__ABRUPT 0x1 | ||
169 | #define BF_TCU_CTRL_SHUTDOWN(v) (((v) & 0x1) << 9) | ||
170 | #define BFM_TCU_CTRL_SHUTDOWN(v) BM_TCU_CTRL_SHUTDOWN | ||
171 | #define BF_TCU_CTRL_SHUTDOWN_V(e) BF_TCU_CTRL_SHUTDOWN(BV_TCU_CTRL_SHUTDOWN__##e) | ||
172 | #define BFM_TCU_CTRL_SHUTDOWN_V(v) BM_TCU_CTRL_SHUTDOWN | ||
173 | #define BP_TCU_CTRL_INIT_LVL 8 | ||
174 | #define BM_TCU_CTRL_INIT_LVL 0x100 | ||
175 | #define BF_TCU_CTRL_INIT_LVL(v) (((v) & 0x1) << 8) | ||
176 | #define BFM_TCU_CTRL_INIT_LVL(v) BM_TCU_CTRL_INIT_LVL | ||
177 | #define BF_TCU_CTRL_INIT_LVL_V(e) BF_TCU_CTRL_INIT_LVL(BV_TCU_CTRL_INIT_LVL__##e) | ||
178 | #define BFM_TCU_CTRL_INIT_LVL_V(v) BM_TCU_CTRL_INIT_LVL | ||
179 | #define BP_TCU_CTRL_PWM_EN 7 | ||
180 | #define BM_TCU_CTRL_PWM_EN 0x80 | ||
181 | #define BF_TCU_CTRL_PWM_EN(v) (((v) & 0x1) << 7) | ||
182 | #define BFM_TCU_CTRL_PWM_EN(v) BM_TCU_CTRL_PWM_EN | ||
183 | #define BF_TCU_CTRL_PWM_EN_V(e) BF_TCU_CTRL_PWM_EN(BV_TCU_CTRL_PWM_EN__##e) | ||
184 | #define BFM_TCU_CTRL_PWM_EN_V(v) BM_TCU_CTRL_PWM_EN | ||
185 | #define BP_TCU_CTRL_PWM_IN_EN 6 | ||
186 | #define BM_TCU_CTRL_PWM_IN_EN 0x40 | ||
187 | #define BF_TCU_CTRL_PWM_IN_EN(v) (((v) & 0x1) << 6) | ||
188 | #define BFM_TCU_CTRL_PWM_IN_EN(v) BM_TCU_CTRL_PWM_IN_EN | ||
189 | #define BF_TCU_CTRL_PWM_IN_EN_V(e) BF_TCU_CTRL_PWM_IN_EN(BV_TCU_CTRL_PWM_IN_EN__##e) | ||
190 | #define BFM_TCU_CTRL_PWM_IN_EN_V(v) BM_TCU_CTRL_PWM_IN_EN | ||
191 | |||
192 | #endif /* __HEADERGEN_TCU_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/wdt.h b/firmware/target/mips/ingenic_x1000/x1000/wdt.h new file mode 100644 index 0000000000..53225e3d7c --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/wdt.h | |||
@@ -0,0 +1,74 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_WDT_H__ | ||
25 | #define __HEADERGEN_WDT_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_WDT_DATA jz_reg(WDT_DATA) | ||
30 | #define JA_WDT_DATA (0xb0002000 + 0x0) | ||
31 | #define JT_WDT_DATA JIO_32_RW | ||
32 | #define JN_WDT_DATA WDT_DATA | ||
33 | #define JI_WDT_DATA | ||
34 | |||
35 | #define REG_WDT_ENABLE jz_reg(WDT_ENABLE) | ||
36 | #define JA_WDT_ENABLE (0xb0002000 + 0x4) | ||
37 | #define JT_WDT_ENABLE JIO_32_RW | ||
38 | #define JN_WDT_ENABLE WDT_ENABLE | ||
39 | #define JI_WDT_ENABLE | ||
40 | |||
41 | #define REG_WDT_COUNT jz_reg(WDT_COUNT) | ||
42 | #define JA_WDT_COUNT (0xb0002000 + 0x8) | ||
43 | #define JT_WDT_COUNT JIO_32_RW | ||
44 | #define JN_WDT_COUNT WDT_COUNT | ||
45 | #define JI_WDT_COUNT | ||
46 | |||
47 | #define REG_WDT_CTRL jz_reg(WDT_CTRL) | ||
48 | #define JA_WDT_CTRL (0xb0002000 + 0xc) | ||
49 | #define JT_WDT_CTRL JIO_32_RW | ||
50 | #define JN_WDT_CTRL WDT_CTRL | ||
51 | #define JI_WDT_CTRL | ||
52 | #define BP_WDT_CTRL_PRESCALE 3 | ||
53 | #define BM_WDT_CTRL_PRESCALE 0x38 | ||
54 | #define BV_WDT_CTRL_PRESCALE__BY_1 0x0 | ||
55 | #define BV_WDT_CTRL_PRESCALE__BY_4 0x1 | ||
56 | #define BV_WDT_CTRL_PRESCALE__BY_16 0x2 | ||
57 | #define BV_WDT_CTRL_PRESCALE__BY_64 0x3 | ||
58 | #define BV_WDT_CTRL_PRESCALE__BY_256 0x4 | ||
59 | #define BV_WDT_CTRL_PRESCALE__BY_1024 0x5 | ||
60 | #define BF_WDT_CTRL_PRESCALE(v) (((v) & 0x7) << 3) | ||
61 | #define BFM_WDT_CTRL_PRESCALE(v) BM_WDT_CTRL_PRESCALE | ||
62 | #define BF_WDT_CTRL_PRESCALE_V(e) BF_WDT_CTRL_PRESCALE(BV_WDT_CTRL_PRESCALE__##e) | ||
63 | #define BFM_WDT_CTRL_PRESCALE_V(v) BM_WDT_CTRL_PRESCALE | ||
64 | #define BP_WDT_CTRL_SOURCE 0 | ||
65 | #define BM_WDT_CTRL_SOURCE 0x7 | ||
66 | #define BV_WDT_CTRL_SOURCE__EXT 0x4 | ||
67 | #define BV_WDT_CTRL_SOURCE__RTC 0x2 | ||
68 | #define BV_WDT_CTRL_SOURCE__PLCK 0x1 | ||
69 | #define BF_WDT_CTRL_SOURCE(v) (((v) & 0x7) << 0) | ||
70 | #define BFM_WDT_CTRL_SOURCE(v) BM_WDT_CTRL_SOURCE | ||
71 | #define BF_WDT_CTRL_SOURCE_V(e) BF_WDT_CTRL_SOURCE(BV_WDT_CTRL_SOURCE__##e) | ||
72 | #define BFM_WDT_CTRL_SOURCE_V(v) BM_WDT_CTRL_SOURCE | ||
73 | |||
74 | #endif /* __HEADERGEN_WDT_H__*/ | ||
diff --git a/firmware/target/mips/mipsr2-endian.h b/firmware/target/mips/mipsr2-endian.h new file mode 100644 index 0000000000..08992bfcdd --- /dev/null +++ b/firmware/target/mips/mipsr2-endian.h | |||
@@ -0,0 +1,44 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef __MIPSR2_ENDIAN_H__ | ||
23 | #define __MIPSR2_ENDIAN_H__ | ||
24 | |||
25 | #include <stdint.h> | ||
26 | |||
27 | static inline uint32_t swap32_hw(uint32_t value) | ||
28 | { | ||
29 | register uint32_t out; | ||
30 | __asm__ ("wsbh %0, %1\n" | ||
31 | "rotr %0, %0, 16\n" | ||
32 | : "=r"(out) : "r"(value)); | ||
33 | return out; | ||
34 | } | ||
35 | |||
36 | static inline uint16_t swap16_hw(uint16_t value) | ||
37 | { | ||
38 | register uint32_t out, in; | ||
39 | in = value; | ||
40 | __asm__ ("wsbh %0, %1" : "=r"(out) : "r"(in)); | ||
41 | return (uint16_t)out; | ||
42 | } | ||
43 | |||
44 | #endif /* __MIPSR2_ENDIAN_H__ */ | ||
diff --git a/firmware/target/mips/mmu-mips.c b/firmware/target/mips/mmu-mips.c index 2daed5ed9e..f4770aa468 100644 --- a/firmware/target/mips/mmu-mips.c +++ b/firmware/target/mips/mmu-mips.c | |||
@@ -25,7 +25,7 @@ | |||
25 | #include "system.h" | 25 | #include "system.h" |
26 | #include "mmu-mips.h" | 26 | #include "mmu-mips.h" |
27 | 27 | ||
28 | #if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B | 28 | #if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B || CONFIG_CPU == X1000 |
29 | /* XBurst core has 32 JTLB entries */ | 29 | /* XBurst core has 32 JTLB entries */ |
30 | #define NR_TLB_ENTRIES 32 | 30 | #define NR_TLB_ENTRIES 32 |
31 | #else | 31 | #else |
@@ -134,7 +134,7 @@ void mmu_init(void) | |||
134 | /* Target specific operations: | 134 | /* Target specific operations: |
135 | * - invalidate BTB (Branch Table Buffer) | 135 | * - invalidate BTB (Branch Table Buffer) |
136 | * - sync barrier after cache operations */ | 136 | * - sync barrier after cache operations */ |
137 | #if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B | 137 | #if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B || CONFIG_CPU == X1000 |
138 | #define INVALIDATE_BTB() \ | 138 | #define INVALIDATE_BTB() \ |
139 | do { \ | 139 | do { \ |
140 | register unsigned long tmp; \ | 140 | register unsigned long tmp; \ |