diff options
Diffstat (limited to 'firmware/target/mips')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/erosqnative/audiohw-erosqnative.c | 1 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/pcm-x1000.c | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/firmware/target/mips/ingenic_x1000/erosqnative/audiohw-erosqnative.c b/firmware/target/mips/ingenic_x1000/erosqnative/audiohw-erosqnative.c index 7bb985650c..52265c9580 100644 --- a/firmware/target/mips/ingenic_x1000/erosqnative/audiohw-erosqnative.c +++ b/firmware/target/mips/ingenic_x1000/erosqnative/audiohw-erosqnative.c | |||
@@ -42,6 +42,7 @@ void audiohw_init(void) | |||
42 | gpio_set_level(GPIO_ISL54405_MUTE, 1); | 42 | gpio_set_level(GPIO_ISL54405_MUTE, 1); |
43 | gpio_set_level(GPIO_PCM5102A_XMIT, 0); | 43 | gpio_set_level(GPIO_PCM5102A_XMIT, 0); |
44 | 44 | ||
45 | aic_set_play_last_sample(true); | ||
45 | aic_set_external_codec(true); | 46 | aic_set_external_codec(true); |
46 | aic_set_i2s_mode(AIC_I2S_MASTER_MODE); | 47 | aic_set_i2s_mode(AIC_I2S_MASTER_MODE); |
47 | audiohw_set_frequency(HW_FREQ_48); | 48 | audiohw_set_frequency(HW_FREQ_48); |
diff --git a/firmware/target/mips/ingenic_x1000/pcm-x1000.c b/firmware/target/mips/ingenic_x1000/pcm-x1000.c index ce2fbb17a9..ef54d45e62 100644 --- a/firmware/target/mips/ingenic_x1000/pcm-x1000.c +++ b/firmware/target/mips/ingenic_x1000/pcm-x1000.c | |||
@@ -58,7 +58,7 @@ void pcm_play_dma_init(void) | |||
58 | /* Configure AIC with some sane defaults */ | 58 | /* Configure AIC with some sane defaults */ |
59 | jz_writef(AIC_CFG, RST(1)); | 59 | jz_writef(AIC_CFG, RST(1)); |
60 | jz_writef(AIC_I2SCR, STPBK(1)); | 60 | jz_writef(AIC_I2SCR, STPBK(1)); |
61 | jz_writef(AIC_CFG, MSB(0), LSMP(1), ICDC(0), AUSEL(1), BCKD(0), SYNCD(0)); | 61 | jz_writef(AIC_CFG, MSB(0), LSMP(0), ICDC(0), AUSEL(1), BCKD(0), SYNCD(0)); |
62 | jz_writef(AIC_CCR, ENDSW(0), ASVTSU(0)); | 62 | jz_writef(AIC_CCR, ENDSW(0), ASVTSU(0)); |
63 | jz_writef(AIC_I2SCR, RFIRST(0), ESCLK(0), AMSL(0)); | 63 | jz_writef(AIC_I2SCR, RFIRST(0), ESCLK(0), AMSL(0)); |
64 | jz_write(AIC_SPENA, 0); | 64 | jz_write(AIC_SPENA, 0); |