diff options
Diffstat (limited to 'firmware/target/mips')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/boot-x1000.h | 24 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/clk-x1000.c | 59 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/spl-x1000.c | 1 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/system-x1000.c | 1 |
4 files changed, 28 insertions, 57 deletions
diff --git a/firmware/target/mips/ingenic_x1000/boot-x1000.h b/firmware/target/mips/ingenic_x1000/boot-x1000.h index fa918a3ead..1b7a0db1e9 100644 --- a/firmware/target/mips/ingenic_x1000/boot-x1000.h +++ b/firmware/target/mips/ingenic_x1000/boot-x1000.h | |||
@@ -28,16 +28,6 @@ | |||
28 | #include <stddef.h> | 28 | #include <stddef.h> |
29 | 29 | ||
30 | enum { | 30 | enum { |
31 | BOOT_OPTION_ROCKBOX = 0, | ||
32 | BOOT_OPTION_OFW_PLAYER, | ||
33 | BOOT_OPTION_OFW_RECOVERY, | ||
34 | }; | ||
35 | |||
36 | enum { | ||
37 | /* 3 bits to store the boot option selected by the SPL */ | ||
38 | BOOT_OPTION_MASK = 0x7, | ||
39 | BOOT_OPTION_SHIFT = 0, | ||
40 | |||
41 | /* Set after running clk_init() and setting up system clocks */ | 31 | /* Set after running clk_init() and setting up system clocks */ |
42 | BOOT_FLAG_CLK_INIT = (1 << 31), | 32 | BOOT_FLAG_CLK_INIT = (1 << 31), |
43 | 33 | ||
@@ -88,18 +78,4 @@ static inline void clr_boot_flag(uint32_t bit) | |||
88 | cpm_scratch_set(REG_CPM_SCRATCH & ~bit); | 78 | cpm_scratch_set(REG_CPM_SCRATCH & ~bit); |
89 | } | 79 | } |
90 | 80 | ||
91 | static inline void set_boot_option(int opt) | ||
92 | { | ||
93 | uint32_t r = REG_CPM_SCRATCH; | ||
94 | r &= ~(BOOT_OPTION_MASK << BOOT_OPTION_SHIFT); | ||
95 | r |= (opt & BOOT_OPTION_MASK) << BOOT_OPTION_SHIFT; | ||
96 | cpm_scratch_set(r); | ||
97 | } | ||
98 | |||
99 | static inline int get_boot_option(void) | ||
100 | { | ||
101 | uint32_t r = REG_CPM_SCRATCH; | ||
102 | return (r >> BOOT_OPTION_SHIFT) & BOOT_OPTION_MASK; | ||
103 | } | ||
104 | |||
105 | #endif /* __BOOT_X1000_H__ */ | 81 | #endif /* __BOOT_X1000_H__ */ |
diff --git a/firmware/target/mips/ingenic_x1000/clk-x1000.c b/firmware/target/mips/ingenic_x1000/clk-x1000.c index 4988e7c3bf..e3b0f792bb 100644 --- a/firmware/target/mips/ingenic_x1000/clk-x1000.c +++ b/firmware/target/mips/ingenic_x1000/clk-x1000.c | |||
@@ -265,39 +265,36 @@ void clk_init(void) | |||
265 | jz_writef(CPM_APCR, BS(1), PLLM(42 - 1), PLLN(0), PLLOD(0), ENABLE(1)); | 265 | jz_writef(CPM_APCR, BS(1), PLLM(42 - 1), PLLN(0), PLLOD(0), ENABLE(1)); |
266 | while(jz_readf(CPM_APCR, ON) == 0); | 266 | while(jz_readf(CPM_APCR, ON) == 0); |
267 | 267 | ||
268 | #if (defined(FIIO_M3K) || defined(EROS_QN)) | 268 | #if defined(FIIO_M3K) || defined(EROS_QN) |
269 | /* TODO: Allow targets to define their clock frequencies in their config, | 269 | /* TODO: Allow targets to define their clock frequencies in their config, |
270 | * instead of having this be a random special case. */ | 270 | * instead of having this be a random special case. */ |
271 | if(get_boot_option() == BOOT_OPTION_ROCKBOX) { | 271 | clk_set_ccr_div(CLKDIV_CPU(1) | /* 1008 MHz */ |
272 | clk_set_ccr_div(CLKDIV_CPU(1) | /* 1008 MHz */ | 272 | CLKDIV_L2(2) | /* 504 MHz */ |
273 | CLKDIV_L2(2) | /* 504 MHz */ | 273 | CLKDIV_AHB0(5) | /* 201.6 MHz */ |
274 | CLKDIV_AHB0(5) | /* 201.6 MHz */ | 274 | CLKDIV_AHB2(5) | /* 201.6 MHz */ |
275 | CLKDIV_AHB2(5) | /* 201.6 MHz */ | 275 | CLKDIV_PCLK(10)); /* 100.8 MHz */ |
276 | CLKDIV_PCLK(10)); /* 100.8 MHz */ | 276 | clk_set_ccr_mux(CLKMUX_SCLK_A(APLL) | |
277 | clk_set_ccr_mux(CLKMUX_SCLK_A(APLL) | | 277 | CLKMUX_CPU(SCLK_A) | |
278 | CLKMUX_CPU(SCLK_A) | | 278 | CLKMUX_AHB0(SCLK_A) | |
279 | CLKMUX_AHB0(SCLK_A) | | 279 | CLKMUX_AHB2(SCLK_A)); |
280 | CLKMUX_AHB2(SCLK_A)); | 280 | |
281 | 281 | /* DDR to 201.6 MHz */ | |
282 | /* DDR to 201.6 MHz */ | 282 | clk_set_ddr(X1000_CLK_SCLK_A, 5); |
283 | clk_set_ddr(X1000_CLK_SCLK_A, 5); | 283 | |
284 | 284 | /* Disable MPLL */ | |
285 | /* Disable MPLL */ | 285 | jz_writef(CPM_MPCR, ENABLE(0)); |
286 | jz_writef(CPM_MPCR, ENABLE(0)); | 286 | while(jz_readf(CPM_MPCR, ON)); |
287 | while(jz_readf(CPM_MPCR, ON)); | 287 | #else |
288 | } else { | 288 | /* Default configuration matching the Ingenic OF */ |
289 | #endif | 289 | clk_set_ccr_div(CLKDIV_CPU(1) | /* 1008 MHz */ |
290 | clk_set_ccr_div(CLKDIV_CPU(1) | /* 1008 MHz */ | 290 | CLKDIV_L2(2) | /* 504 MHz */ |
291 | CLKDIV_L2(2) | /* 504 MHz */ | 291 | CLKDIV_AHB0(3) | /* 200 MHz */ |
292 | CLKDIV_AHB0(3) | /* 200 MHz */ | 292 | CLKDIV_AHB2(3) | /* 200 MHz */ |
293 | CLKDIV_AHB2(3) | /* 200 MHz */ | 293 | CLKDIV_PCLK(6)); /* 100 MHz */ |
294 | CLKDIV_PCLK(6)); /* 100 MHz */ | 294 | clk_set_ccr_mux(CLKMUX_SCLK_A(APLL) | |
295 | clk_set_ccr_mux(CLKMUX_SCLK_A(APLL) | | 295 | CLKMUX_CPU(SCLK_A) | |
296 | CLKMUX_CPU(SCLK_A) | | 296 | CLKMUX_AHB0(MPLL) | |
297 | CLKMUX_AHB0(MPLL) | | 297 | CLKMUX_AHB2(MPLL)); |
298 | CLKMUX_AHB2(MPLL)); | ||
299 | #if (defined(FIIO_M3K) || defined(EROS_QN)) | ||
300 | } | ||
301 | #endif | 298 | #endif |
302 | 299 | ||
303 | /* mark that clocks have been initialized */ | 300 | /* mark that clocks have been initialized */ |
diff --git a/firmware/target/mips/ingenic_x1000/spl-x1000.c b/firmware/target/mips/ingenic_x1000/spl-x1000.c index 05196e8270..b9ee6cc1c1 100644 --- a/firmware/target/mips/ingenic_x1000/spl-x1000.c +++ b/firmware/target/mips/ingenic_x1000/spl-x1000.c | |||
@@ -319,7 +319,6 @@ void spl_main(void) | |||
319 | 319 | ||
320 | /* set up boot flags */ | 320 | /* set up boot flags */ |
321 | init_boot_flags(); | 321 | init_boot_flags(); |
322 | set_boot_option(BOOT_OPTION_ROCKBOX); | ||
323 | 322 | ||
324 | /* early clock and DRAM init */ | 323 | /* early clock and DRAM init */ |
325 | clk_init_early(); | 324 | clk_init_early(); |
diff --git a/firmware/target/mips/ingenic_x1000/system-x1000.c b/firmware/target/mips/ingenic_x1000/system-x1000.c index d43c8e67e4..7542b97a3d 100644 --- a/firmware/target/mips/ingenic_x1000/system-x1000.c +++ b/firmware/target/mips/ingenic_x1000/system-x1000.c | |||
@@ -72,7 +72,6 @@ void system_early_init(void) | |||
72 | * This hack should keep everything working as usual. */ | 72 | * This hack should keep everything working as usual. */ |
73 | if(jz_readf(CPM_MPCR, ON) == 0) { | 73 | if(jz_readf(CPM_MPCR, ON) == 0) { |
74 | init_boot_flags(); | 74 | init_boot_flags(); |
75 | set_boot_option(BOOT_OPTION_ROCKBOX); | ||
76 | set_boot_flag(BOOT_FLAG_CLK_INIT); | 75 | set_boot_flag(BOOT_FLAG_CLK_INIT); |
77 | } | 76 | } |
78 | #endif | 77 | #endif |