2 files changed, 16 insertions, 9 deletions

diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.c b/firmware/target/mips/ingenic_x1000/nand-x1000.c
index 18d548ba8c..382fd761b3 100644
--- a/firmware/target/mips/ingenic_x1000/nand-x1000.c
+++ b/firmware/target/mips/ingenic_x1000/nand-x1000.c
@@ -98,21 +98,24 @@ static bool identify_chip(nand_drv* drv)
      * - 1 byte address, no dummy byte
      * - no address byte, 1 byte dummy
      *
-     * Right now there is only a need for the 2nd variation, as that is
-     * the method used by the ATO25D1GA.
-     *
-     * Some chips also output more than 2 ID bytes.
+     * Currently we use the 2nd method, aka. address read ID.
      */
-    sfc_exec(NANDCMD_READID(1, 0), 0, drv->scratch_buf, 2|SFC_READ);
+    sfc_exec(NANDCMD_READID(1, 0), 0, drv->scratch_buf, 4|SFC_READ);
     drv->mf_id = drv->scratch_buf[0];
     drv->dev_id = drv->scratch_buf[1];
+    drv->dev_id2 = drv->scratch_buf[2];
 
     for(size_t i = 0; i < nr_supported_nand_chips; ++i) {
         const nand_chip* chip = &supported_nand_chips[i];
-        if(chip->mf_id == drv->mf_id && chip->dev_id == drv->dev_id) {
-            drv->chip = chip;
-            return true;
-        }
+        if(chip->mf_id != drv->mf_id || chip->dev_id != drv->dev_id)
+            continue;
+
+        if((chip->flags & NAND_CHIPFLAG_HAS_DEVID2) &&
+           chip->dev_id2 != drv->dev_id2)
+            continue;
+
+        drv->chip = chip;
+        return true;
     }
 
     return false;
diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.h b/firmware/target/mips/ingenic_x1000/nand-x1000.h
index 5e6d1f09bc..176897e4f2 100644
--- a/firmware/target/mips/ingenic_x1000/nand-x1000.h
+++ b/firmware/target/mips/ingenic_x1000/nand-x1000.h
@@ -41,6 +41,8 @@
 #define NAND_CHIPFLAG_QUAD          0x0001
 /* Chip requires QE bit set to enable quad I/O mode */
 #define NAND_CHIPFLAG_HAS_QE_BIT    0x0002
+/* Chip has 2nd device ID byte */
+#define NAND_CHIPFLAG_HAS_DEVID2    0x0004
 
 /*                                          cmd   mode             a  d  phase format         has data */
 #define NANDCMD_RESET               SFC_CMD(0xff, SFC_TMODE_1_1_1, 0, 0, SFC_PFMT_ADDR_FIRST, 0)
@@ -97,6 +99,7 @@ typedef struct nand_chip {
     /* Manufacturer and device ID bytes */
     uint8_t mf_id;
     uint8_t dev_id;
+    uint8_t dev_id2;
 
     /* Row/column address width */
     uint8_t row_cycles;
@@ -158,6 +161,7 @@ typedef struct nand_drv {
     /* Probed mf_id / dev_id for debugging, in case identification fails. */
     uint8_t mf_id;
     uint8_t dev_id;
+    uint8_t dev_id2;
 
     /* SFC commands used for I/O, these are set based on chip data */
     uint32_t cmd_page_read;