diff options
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/x1000/sfc.h')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/sfc.h | 481 |
1 files changed, 481 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/x1000/sfc.h b/firmware/target/mips/ingenic_x1000/x1000/sfc.h new file mode 100644 index 0000000000..1a3c102c64 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/sfc.h | |||
@@ -0,0 +1,481 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_SFC_H__ | ||
25 | #define __HEADERGEN_SFC_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_SFC_GLB jz_reg(SFC_GLB) | ||
30 | #define JA_SFC_GLB (0xb3440000 + 0x0) | ||
31 | #define JT_SFC_GLB JIO_32_RW | ||
32 | #define JN_SFC_GLB SFC_GLB | ||
33 | #define JI_SFC_GLB | ||
34 | #define BP_SFC_GLB_THRESHOLD 7 | ||
35 | #define BM_SFC_GLB_THRESHOLD 0x1f80 | ||
36 | #define BF_SFC_GLB_THRESHOLD(v) (((v) & 0x3f) << 7) | ||
37 | #define BFM_SFC_GLB_THRESHOLD(v) BM_SFC_GLB_THRESHOLD | ||
38 | #define BF_SFC_GLB_THRESHOLD_V(e) BF_SFC_GLB_THRESHOLD(BV_SFC_GLB_THRESHOLD__##e) | ||
39 | #define BFM_SFC_GLB_THRESHOLD_V(v) BM_SFC_GLB_THRESHOLD | ||
40 | #define BP_SFC_GLB_PHASE_NUM 3 | ||
41 | #define BM_SFC_GLB_PHASE_NUM 0x38 | ||
42 | #define BF_SFC_GLB_PHASE_NUM(v) (((v) & 0x7) << 3) | ||
43 | #define BFM_SFC_GLB_PHASE_NUM(v) BM_SFC_GLB_PHASE_NUM | ||
44 | #define BF_SFC_GLB_PHASE_NUM_V(e) BF_SFC_GLB_PHASE_NUM(BV_SFC_GLB_PHASE_NUM__##e) | ||
45 | #define BFM_SFC_GLB_PHASE_NUM_V(v) BM_SFC_GLB_PHASE_NUM | ||
46 | #define BP_SFC_GLB_TRAN_DIR 13 | ||
47 | #define BM_SFC_GLB_TRAN_DIR 0x2000 | ||
48 | #define BV_SFC_GLB_TRAN_DIR__READ 0x0 | ||
49 | #define BV_SFC_GLB_TRAN_DIR__WRITE 0x1 | ||
50 | #define BF_SFC_GLB_TRAN_DIR(v) (((v) & 0x1) << 13) | ||
51 | #define BFM_SFC_GLB_TRAN_DIR(v) BM_SFC_GLB_TRAN_DIR | ||
52 | #define BF_SFC_GLB_TRAN_DIR_V(e) BF_SFC_GLB_TRAN_DIR(BV_SFC_GLB_TRAN_DIR__##e) | ||
53 | #define BFM_SFC_GLB_TRAN_DIR_V(v) BM_SFC_GLB_TRAN_DIR | ||
54 | #define BP_SFC_GLB_OP_MODE 6 | ||
55 | #define BM_SFC_GLB_OP_MODE 0x40 | ||
56 | #define BV_SFC_GLB_OP_MODE__SLAVE 0x0 | ||
57 | #define BV_SFC_GLB_OP_MODE__DMA 0x1 | ||
58 | #define BF_SFC_GLB_OP_MODE(v) (((v) & 0x1) << 6) | ||
59 | #define BFM_SFC_GLB_OP_MODE(v) BM_SFC_GLB_OP_MODE | ||
60 | #define BF_SFC_GLB_OP_MODE_V(e) BF_SFC_GLB_OP_MODE(BV_SFC_GLB_OP_MODE__##e) | ||
61 | #define BFM_SFC_GLB_OP_MODE_V(v) BM_SFC_GLB_OP_MODE | ||
62 | #define BP_SFC_GLB_WP_EN 2 | ||
63 | #define BM_SFC_GLB_WP_EN 0x4 | ||
64 | #define BF_SFC_GLB_WP_EN(v) (((v) & 0x1) << 2) | ||
65 | #define BFM_SFC_GLB_WP_EN(v) BM_SFC_GLB_WP_EN | ||
66 | #define BF_SFC_GLB_WP_EN_V(e) BF_SFC_GLB_WP_EN(BV_SFC_GLB_WP_EN__##e) | ||
67 | #define BFM_SFC_GLB_WP_EN_V(v) BM_SFC_GLB_WP_EN | ||
68 | #define BP_SFC_GLB_BURST_MD 0 | ||
69 | #define BM_SFC_GLB_BURST_MD 0x3 | ||
70 | #define BV_SFC_GLB_BURST_MD__INCR4 0x0 | ||
71 | #define BV_SFC_GLB_BURST_MD__INCR8 0x1 | ||
72 | #define BV_SFC_GLB_BURST_MD__INCR16 0x2 | ||
73 | #define BV_SFC_GLB_BURST_MD__INCR32 0x3 | ||
74 | #define BF_SFC_GLB_BURST_MD(v) (((v) & 0x3) << 0) | ||
75 | #define BFM_SFC_GLB_BURST_MD(v) BM_SFC_GLB_BURST_MD | ||
76 | #define BF_SFC_GLB_BURST_MD_V(e) BF_SFC_GLB_BURST_MD(BV_SFC_GLB_BURST_MD__##e) | ||
77 | #define BFM_SFC_GLB_BURST_MD_V(v) BM_SFC_GLB_BURST_MD | ||
78 | |||
79 | #define REG_SFC_DEV_CONF jz_reg(SFC_DEV_CONF) | ||
80 | #define JA_SFC_DEV_CONF (0xb3440000 + 0x4) | ||
81 | #define JT_SFC_DEV_CONF JIO_32_RW | ||
82 | #define JN_SFC_DEV_CONF SFC_DEV_CONF | ||
83 | #define JI_SFC_DEV_CONF | ||
84 | #define BP_SFC_DEV_CONF_SMP_DELAY 16 | ||
85 | #define BM_SFC_DEV_CONF_SMP_DELAY 0x30000 | ||
86 | #define BF_SFC_DEV_CONF_SMP_DELAY(v) (((v) & 0x3) << 16) | ||
87 | #define BFM_SFC_DEV_CONF_SMP_DELAY(v) BM_SFC_DEV_CONF_SMP_DELAY | ||
88 | #define BF_SFC_DEV_CONF_SMP_DELAY_V(e) BF_SFC_DEV_CONF_SMP_DELAY(BV_SFC_DEV_CONF_SMP_DELAY__##e) | ||
89 | #define BFM_SFC_DEV_CONF_SMP_DELAY_V(v) BM_SFC_DEV_CONF_SMP_DELAY | ||
90 | #define BP_SFC_DEV_CONF_STA_TYPE 13 | ||
91 | #define BM_SFC_DEV_CONF_STA_TYPE 0x6000 | ||
92 | #define BV_SFC_DEV_CONF_STA_TYPE__1BYTE 0x0 | ||
93 | #define BV_SFC_DEV_CONF_STA_TYPE__2BYTE 0x1 | ||
94 | #define BV_SFC_DEV_CONF_STA_TYPE__3BYTE 0x2 | ||
95 | #define BV_SFC_DEV_CONF_STA_TYPE__4BYTE 0x3 | ||
96 | #define BF_SFC_DEV_CONF_STA_TYPE(v) (((v) & 0x3) << 13) | ||
97 | #define BFM_SFC_DEV_CONF_STA_TYPE(v) BM_SFC_DEV_CONF_STA_TYPE | ||
98 | #define BF_SFC_DEV_CONF_STA_TYPE_V(e) BF_SFC_DEV_CONF_STA_TYPE(BV_SFC_DEV_CONF_STA_TYPE__##e) | ||
99 | #define BFM_SFC_DEV_CONF_STA_TYPE_V(v) BM_SFC_DEV_CONF_STA_TYPE | ||
100 | #define BP_SFC_DEV_CONF_THOLD 11 | ||
101 | #define BM_SFC_DEV_CONF_THOLD 0x1800 | ||
102 | #define BF_SFC_DEV_CONF_THOLD(v) (((v) & 0x3) << 11) | ||
103 | #define BFM_SFC_DEV_CONF_THOLD(v) BM_SFC_DEV_CONF_THOLD | ||
104 | #define BF_SFC_DEV_CONF_THOLD_V(e) BF_SFC_DEV_CONF_THOLD(BV_SFC_DEV_CONF_THOLD__##e) | ||
105 | #define BFM_SFC_DEV_CONF_THOLD_V(v) BM_SFC_DEV_CONF_THOLD | ||
106 | #define BP_SFC_DEV_CONF_TSETUP 9 | ||
107 | #define BM_SFC_DEV_CONF_TSETUP 0x600 | ||
108 | #define BF_SFC_DEV_CONF_TSETUP(v) (((v) & 0x3) << 9) | ||
109 | #define BFM_SFC_DEV_CONF_TSETUP(v) BM_SFC_DEV_CONF_TSETUP | ||
110 | #define BF_SFC_DEV_CONF_TSETUP_V(e) BF_SFC_DEV_CONF_TSETUP(BV_SFC_DEV_CONF_TSETUP__##e) | ||
111 | #define BFM_SFC_DEV_CONF_TSETUP_V(v) BM_SFC_DEV_CONF_TSETUP | ||
112 | #define BP_SFC_DEV_CONF_TSH 5 | ||
113 | #define BM_SFC_DEV_CONF_TSH 0x1e0 | ||
114 | #define BF_SFC_DEV_CONF_TSH(v) (((v) & 0xf) << 5) | ||
115 | #define BFM_SFC_DEV_CONF_TSH(v) BM_SFC_DEV_CONF_TSH | ||
116 | #define BF_SFC_DEV_CONF_TSH_V(e) BF_SFC_DEV_CONF_TSH(BV_SFC_DEV_CONF_TSH__##e) | ||
117 | #define BFM_SFC_DEV_CONF_TSH_V(v) BM_SFC_DEV_CONF_TSH | ||
118 | #define BP_SFC_DEV_CONF_CMD_TYPE 15 | ||
119 | #define BM_SFC_DEV_CONF_CMD_TYPE 0x8000 | ||
120 | #define BV_SFC_DEV_CONF_CMD_TYPE__8BITS 0x0 | ||
121 | #define BV_SFC_DEV_CONF_CMD_TYPE__16BITS 0x1 | ||
122 | #define BF_SFC_DEV_CONF_CMD_TYPE(v) (((v) & 0x1) << 15) | ||
123 | #define BFM_SFC_DEV_CONF_CMD_TYPE(v) BM_SFC_DEV_CONF_CMD_TYPE | ||
124 | #define BF_SFC_DEV_CONF_CMD_TYPE_V(e) BF_SFC_DEV_CONF_CMD_TYPE(BV_SFC_DEV_CONF_CMD_TYPE__##e) | ||
125 | #define BFM_SFC_DEV_CONF_CMD_TYPE_V(v) BM_SFC_DEV_CONF_CMD_TYPE | ||
126 | #define BP_SFC_DEV_CONF_CPHA 4 | ||
127 | #define BM_SFC_DEV_CONF_CPHA 0x10 | ||
128 | #define BF_SFC_DEV_CONF_CPHA(v) (((v) & 0x1) << 4) | ||
129 | #define BFM_SFC_DEV_CONF_CPHA(v) BM_SFC_DEV_CONF_CPHA | ||
130 | #define BF_SFC_DEV_CONF_CPHA_V(e) BF_SFC_DEV_CONF_CPHA(BV_SFC_DEV_CONF_CPHA__##e) | ||
131 | #define BFM_SFC_DEV_CONF_CPHA_V(v) BM_SFC_DEV_CONF_CPHA | ||
132 | #define BP_SFC_DEV_CONF_CPOL 3 | ||
133 | #define BM_SFC_DEV_CONF_CPOL 0x8 | ||
134 | #define BF_SFC_DEV_CONF_CPOL(v) (((v) & 0x1) << 3) | ||
135 | #define BFM_SFC_DEV_CONF_CPOL(v) BM_SFC_DEV_CONF_CPOL | ||
136 | #define BF_SFC_DEV_CONF_CPOL_V(e) BF_SFC_DEV_CONF_CPOL(BV_SFC_DEV_CONF_CPOL__##e) | ||
137 | #define BFM_SFC_DEV_CONF_CPOL_V(v) BM_SFC_DEV_CONF_CPOL | ||
138 | #define BP_SFC_DEV_CONF_CE_DL 2 | ||
139 | #define BM_SFC_DEV_CONF_CE_DL 0x4 | ||
140 | #define BF_SFC_DEV_CONF_CE_DL(v) (((v) & 0x1) << 2) | ||
141 | #define BFM_SFC_DEV_CONF_CE_DL(v) BM_SFC_DEV_CONF_CE_DL | ||
142 | #define BF_SFC_DEV_CONF_CE_DL_V(e) BF_SFC_DEV_CONF_CE_DL(BV_SFC_DEV_CONF_CE_DL__##e) | ||
143 | #define BFM_SFC_DEV_CONF_CE_DL_V(v) BM_SFC_DEV_CONF_CE_DL | ||
144 | #define BP_SFC_DEV_CONF_HOLD_DL 1 | ||
145 | #define BM_SFC_DEV_CONF_HOLD_DL 0x2 | ||
146 | #define BF_SFC_DEV_CONF_HOLD_DL(v) (((v) & 0x1) << 1) | ||
147 | #define BFM_SFC_DEV_CONF_HOLD_DL(v) BM_SFC_DEV_CONF_HOLD_DL | ||
148 | #define BF_SFC_DEV_CONF_HOLD_DL_V(e) BF_SFC_DEV_CONF_HOLD_DL(BV_SFC_DEV_CONF_HOLD_DL__##e) | ||
149 | #define BFM_SFC_DEV_CONF_HOLD_DL_V(v) BM_SFC_DEV_CONF_HOLD_DL | ||
150 | #define BP_SFC_DEV_CONF_WP_DL 0 | ||
151 | #define BM_SFC_DEV_CONF_WP_DL 0x1 | ||
152 | #define BF_SFC_DEV_CONF_WP_DL(v) (((v) & 0x1) << 0) | ||
153 | #define BFM_SFC_DEV_CONF_WP_DL(v) BM_SFC_DEV_CONF_WP_DL | ||
154 | #define BF_SFC_DEV_CONF_WP_DL_V(e) BF_SFC_DEV_CONF_WP_DL(BV_SFC_DEV_CONF_WP_DL__##e) | ||
155 | #define BFM_SFC_DEV_CONF_WP_DL_V(v) BM_SFC_DEV_CONF_WP_DL | ||
156 | |||
157 | #define REG_SFC_DEV_STA_EXP jz_reg(SFC_DEV_STA_EXP) | ||
158 | #define JA_SFC_DEV_STA_EXP (0xb3440000 + 0x8) | ||
159 | #define JT_SFC_DEV_STA_EXP JIO_32_RW | ||
160 | #define JN_SFC_DEV_STA_EXP SFC_DEV_STA_EXP | ||
161 | #define JI_SFC_DEV_STA_EXP | ||
162 | |||
163 | #define REG_SFC_DEV_STA_RT jz_reg(SFC_DEV_STA_RT) | ||
164 | #define JA_SFC_DEV_STA_RT (0xb3440000 + 0xc) | ||
165 | #define JT_SFC_DEV_STA_RT JIO_32_RW | ||
166 | #define JN_SFC_DEV_STA_RT SFC_DEV_STA_RT | ||
167 | #define JI_SFC_DEV_STA_RT | ||
168 | |||
169 | #define REG_SFC_DEV_STA_MSK jz_reg(SFC_DEV_STA_MSK) | ||
170 | #define JA_SFC_DEV_STA_MSK (0xb3440000 + 0x10) | ||
171 | #define JT_SFC_DEV_STA_MSK JIO_32_RW | ||
172 | #define JN_SFC_DEV_STA_MSK SFC_DEV_STA_MSK | ||
173 | #define JI_SFC_DEV_STA_MSK | ||
174 | |||
175 | #define REG_SFC_TRAN_CONF(_n1) jz_reg(SFC_TRAN_CONF(_n1)) | ||
176 | #define JA_SFC_TRAN_CONF(_n1) (0xb3440000 + 0x14 + (_n1) * 0x4) | ||
177 | #define JT_SFC_TRAN_CONF(_n1) JIO_32_RW | ||
178 | #define JN_SFC_TRAN_CONF(_n1) SFC_TRAN_CONF | ||
179 | #define JI_SFC_TRAN_CONF(_n1) (_n1) | ||
180 | #define BP_SFC_TRAN_CONF_MODE 29 | ||
181 | #define BM_SFC_TRAN_CONF_MODE 0xe0000000 | ||
182 | #define BF_SFC_TRAN_CONF_MODE(v) (((v) & 0x7) << 29) | ||
183 | #define BFM_SFC_TRAN_CONF_MODE(v) BM_SFC_TRAN_CONF_MODE | ||
184 | #define BF_SFC_TRAN_CONF_MODE_V(e) BF_SFC_TRAN_CONF_MODE(BV_SFC_TRAN_CONF_MODE__##e) | ||
185 | #define BFM_SFC_TRAN_CONF_MODE_V(v) BM_SFC_TRAN_CONF_MODE | ||
186 | #define BP_SFC_TRAN_CONF_ADDR_WIDTH 26 | ||
187 | #define BM_SFC_TRAN_CONF_ADDR_WIDTH 0x1c000000 | ||
188 | #define BF_SFC_TRAN_CONF_ADDR_WIDTH(v) (((v) & 0x7) << 26) | ||
189 | #define BFM_SFC_TRAN_CONF_ADDR_WIDTH(v) BM_SFC_TRAN_CONF_ADDR_WIDTH | ||
190 | #define BF_SFC_TRAN_CONF_ADDR_WIDTH_V(e) BF_SFC_TRAN_CONF_ADDR_WIDTH(BV_SFC_TRAN_CONF_ADDR_WIDTH__##e) | ||
191 | #define BFM_SFC_TRAN_CONF_ADDR_WIDTH_V(v) BM_SFC_TRAN_CONF_ADDR_WIDTH | ||
192 | #define BP_SFC_TRAN_CONF_DUMMY_BITS 17 | ||
193 | #define BM_SFC_TRAN_CONF_DUMMY_BITS 0x7e0000 | ||
194 | #define BF_SFC_TRAN_CONF_DUMMY_BITS(v) (((v) & 0x3f) << 17) | ||
195 | #define BFM_SFC_TRAN_CONF_DUMMY_BITS(v) BM_SFC_TRAN_CONF_DUMMY_BITS | ||
196 | #define BF_SFC_TRAN_CONF_DUMMY_BITS_V(e) BF_SFC_TRAN_CONF_DUMMY_BITS(BV_SFC_TRAN_CONF_DUMMY_BITS__##e) | ||
197 | #define BFM_SFC_TRAN_CONF_DUMMY_BITS_V(v) BM_SFC_TRAN_CONF_DUMMY_BITS | ||
198 | #define BP_SFC_TRAN_CONF_COMMAND 0 | ||
199 | #define BM_SFC_TRAN_CONF_COMMAND 0xffff | ||
200 | #define BF_SFC_TRAN_CONF_COMMAND(v) (((v) & 0xffff) << 0) | ||
201 | #define BFM_SFC_TRAN_CONF_COMMAND(v) BM_SFC_TRAN_CONF_COMMAND | ||
202 | #define BF_SFC_TRAN_CONF_COMMAND_V(e) BF_SFC_TRAN_CONF_COMMAND(BV_SFC_TRAN_CONF_COMMAND__##e) | ||
203 | #define BFM_SFC_TRAN_CONF_COMMAND_V(v) BM_SFC_TRAN_CONF_COMMAND | ||
204 | #define BP_SFC_TRAN_CONF_POLL_EN 25 | ||
205 | #define BM_SFC_TRAN_CONF_POLL_EN 0x2000000 | ||
206 | #define BF_SFC_TRAN_CONF_POLL_EN(v) (((v) & 0x1) << 25) | ||
207 | #define BFM_SFC_TRAN_CONF_POLL_EN(v) BM_SFC_TRAN_CONF_POLL_EN | ||
208 | #define BF_SFC_TRAN_CONF_POLL_EN_V(e) BF_SFC_TRAN_CONF_POLL_EN(BV_SFC_TRAN_CONF_POLL_EN__##e) | ||
209 | #define BFM_SFC_TRAN_CONF_POLL_EN_V(v) BM_SFC_TRAN_CONF_POLL_EN | ||
210 | #define BP_SFC_TRAN_CONF_CMD_EN 24 | ||
211 | #define BM_SFC_TRAN_CONF_CMD_EN 0x1000000 | ||
212 | #define BF_SFC_TRAN_CONF_CMD_EN(v) (((v) & 0x1) << 24) | ||
213 | #define BFM_SFC_TRAN_CONF_CMD_EN(v) BM_SFC_TRAN_CONF_CMD_EN | ||
214 | #define BF_SFC_TRAN_CONF_CMD_EN_V(e) BF_SFC_TRAN_CONF_CMD_EN(BV_SFC_TRAN_CONF_CMD_EN__##e) | ||
215 | #define BFM_SFC_TRAN_CONF_CMD_EN_V(v) BM_SFC_TRAN_CONF_CMD_EN | ||
216 | #define BP_SFC_TRAN_CONF_PHASE_FMT 23 | ||
217 | #define BM_SFC_TRAN_CONF_PHASE_FMT 0x800000 | ||
218 | #define BF_SFC_TRAN_CONF_PHASE_FMT(v) (((v) & 0x1) << 23) | ||
219 | #define BFM_SFC_TRAN_CONF_PHASE_FMT(v) BM_SFC_TRAN_CONF_PHASE_FMT | ||
220 | #define BF_SFC_TRAN_CONF_PHASE_FMT_V(e) BF_SFC_TRAN_CONF_PHASE_FMT(BV_SFC_TRAN_CONF_PHASE_FMT__##e) | ||
221 | #define BFM_SFC_TRAN_CONF_PHASE_FMT_V(v) BM_SFC_TRAN_CONF_PHASE_FMT | ||
222 | #define BP_SFC_TRAN_CONF_DATA_EN 16 | ||
223 | #define BM_SFC_TRAN_CONF_DATA_EN 0x10000 | ||
224 | #define BF_SFC_TRAN_CONF_DATA_EN(v) (((v) & 0x1) << 16) | ||
225 | #define BFM_SFC_TRAN_CONF_DATA_EN(v) BM_SFC_TRAN_CONF_DATA_EN | ||
226 | #define BF_SFC_TRAN_CONF_DATA_EN_V(e) BF_SFC_TRAN_CONF_DATA_EN(BV_SFC_TRAN_CONF_DATA_EN__##e) | ||
227 | #define BFM_SFC_TRAN_CONF_DATA_EN_V(v) BM_SFC_TRAN_CONF_DATA_EN | ||
228 | |||
229 | #define REG_SFC_TRAN_LENGTH jz_reg(SFC_TRAN_LENGTH) | ||
230 | #define JA_SFC_TRAN_LENGTH (0xb3440000 + 0x2c) | ||
231 | #define JT_SFC_TRAN_LENGTH JIO_32_RW | ||
232 | #define JN_SFC_TRAN_LENGTH SFC_TRAN_LENGTH | ||
233 | #define JI_SFC_TRAN_LENGTH | ||
234 | |||
235 | #define REG_SFC_DEV_ADDR(_n1) jz_reg(SFC_DEV_ADDR(_n1)) | ||
236 | #define JA_SFC_DEV_ADDR(_n1) (0xb3440000 + 0x30 + (_n1) * 0x4) | ||
237 | #define JT_SFC_DEV_ADDR(_n1) JIO_32_RW | ||
238 | #define JN_SFC_DEV_ADDR(_n1) SFC_DEV_ADDR | ||
239 | #define JI_SFC_DEV_ADDR(_n1) (_n1) | ||
240 | |||
241 | #define REG_SFC_DEV_PLUS(_n1) jz_reg(SFC_DEV_PLUS(_n1)) | ||
242 | #define JA_SFC_DEV_PLUS(_n1) (0xb3440000 + 0x48 + (_n1) * 0x40) | ||
243 | #define JT_SFC_DEV_PLUS(_n1) JIO_32_RW | ||
244 | #define JN_SFC_DEV_PLUS(_n1) SFC_DEV_PLUS | ||
245 | #define JI_SFC_DEV_PLUS(_n1) (_n1) | ||
246 | |||
247 | #define REG_SFC_MEM_ADDR jz_reg(SFC_MEM_ADDR) | ||
248 | #define JA_SFC_MEM_ADDR (0xb3440000 + 0x60) | ||
249 | #define JT_SFC_MEM_ADDR JIO_32_RW | ||
250 | #define JN_SFC_MEM_ADDR SFC_MEM_ADDR | ||
251 | #define JI_SFC_MEM_ADDR | ||
252 | |||
253 | #define REG_SFC_TRIG jz_reg(SFC_TRIG) | ||
254 | #define JA_SFC_TRIG (0xb3440000 + 0x64) | ||
255 | #define JT_SFC_TRIG JIO_32_RW | ||
256 | #define JN_SFC_TRIG SFC_TRIG | ||
257 | #define JI_SFC_TRIG | ||
258 | #define BP_SFC_TRIG_FLUSH 2 | ||
259 | #define BM_SFC_TRIG_FLUSH 0x4 | ||
260 | #define BF_SFC_TRIG_FLUSH(v) (((v) & 0x1) << 2) | ||
261 | #define BFM_SFC_TRIG_FLUSH(v) BM_SFC_TRIG_FLUSH | ||
262 | #define BF_SFC_TRIG_FLUSH_V(e) BF_SFC_TRIG_FLUSH(BV_SFC_TRIG_FLUSH__##e) | ||
263 | #define BFM_SFC_TRIG_FLUSH_V(v) BM_SFC_TRIG_FLUSH | ||
264 | #define BP_SFC_TRIG_STOP 1 | ||
265 | #define BM_SFC_TRIG_STOP 0x2 | ||
266 | #define BF_SFC_TRIG_STOP(v) (((v) & 0x1) << 1) | ||
267 | #define BFM_SFC_TRIG_STOP(v) BM_SFC_TRIG_STOP | ||
268 | #define BF_SFC_TRIG_STOP_V(e) BF_SFC_TRIG_STOP(BV_SFC_TRIG_STOP__##e) | ||
269 | #define BFM_SFC_TRIG_STOP_V(v) BM_SFC_TRIG_STOP | ||
270 | #define BP_SFC_TRIG_START 0 | ||
271 | #define BM_SFC_TRIG_START 0x1 | ||
272 | #define BF_SFC_TRIG_START(v) (((v) & 0x1) << 0) | ||
273 | #define BFM_SFC_TRIG_START(v) BM_SFC_TRIG_START | ||
274 | #define BF_SFC_TRIG_START_V(e) BF_SFC_TRIG_START(BV_SFC_TRIG_START__##e) | ||
275 | #define BFM_SFC_TRIG_START_V(v) BM_SFC_TRIG_START | ||
276 | |||
277 | #define REG_SFC_SR jz_reg(SFC_SR) | ||
278 | #define JA_SFC_SR (0xb3440000 + 0x68) | ||
279 | #define JT_SFC_SR JIO_32_RW | ||
280 | #define JN_SFC_SR SFC_SR | ||
281 | #define JI_SFC_SR | ||
282 | #define BP_SFC_SR_FIFO_NUM 16 | ||
283 | #define BM_SFC_SR_FIFO_NUM 0x7f0000 | ||
284 | #define BF_SFC_SR_FIFO_NUM(v) (((v) & 0x7f) << 16) | ||
285 | #define BFM_SFC_SR_FIFO_NUM(v) BM_SFC_SR_FIFO_NUM | ||
286 | #define BF_SFC_SR_FIFO_NUM_V(e) BF_SFC_SR_FIFO_NUM(BV_SFC_SR_FIFO_NUM__##e) | ||
287 | #define BFM_SFC_SR_FIFO_NUM_V(v) BM_SFC_SR_FIFO_NUM | ||
288 | #define BP_SFC_SR_BUSY 5 | ||
289 | #define BM_SFC_SR_BUSY 0x60 | ||
290 | #define BF_SFC_SR_BUSY(v) (((v) & 0x3) << 5) | ||
291 | #define BFM_SFC_SR_BUSY(v) BM_SFC_SR_BUSY | ||
292 | #define BF_SFC_SR_BUSY_V(e) BF_SFC_SR_BUSY(BV_SFC_SR_BUSY__##e) | ||
293 | #define BFM_SFC_SR_BUSY_V(v) BM_SFC_SR_BUSY | ||
294 | #define BP_SFC_SR_END 4 | ||
295 | #define BM_SFC_SR_END 0x10 | ||
296 | #define BF_SFC_SR_END(v) (((v) & 0x1) << 4) | ||
297 | #define BFM_SFC_SR_END(v) BM_SFC_SR_END | ||
298 | #define BF_SFC_SR_END_V(e) BF_SFC_SR_END(BV_SFC_SR_END__##e) | ||
299 | #define BFM_SFC_SR_END_V(v) BM_SFC_SR_END | ||
300 | #define BP_SFC_SR_TREQ 3 | ||
301 | #define BM_SFC_SR_TREQ 0x8 | ||
302 | #define BF_SFC_SR_TREQ(v) (((v) & 0x1) << 3) | ||
303 | #define BFM_SFC_SR_TREQ(v) BM_SFC_SR_TREQ | ||
304 | #define BF_SFC_SR_TREQ_V(e) BF_SFC_SR_TREQ(BV_SFC_SR_TREQ__##e) | ||
305 | #define BFM_SFC_SR_TREQ_V(v) BM_SFC_SR_TREQ | ||
306 | #define BP_SFC_SR_RREQ 2 | ||
307 | #define BM_SFC_SR_RREQ 0x4 | ||
308 | #define BF_SFC_SR_RREQ(v) (((v) & 0x1) << 2) | ||
309 | #define BFM_SFC_SR_RREQ(v) BM_SFC_SR_RREQ | ||
310 | #define BF_SFC_SR_RREQ_V(e) BF_SFC_SR_RREQ(BV_SFC_SR_RREQ__##e) | ||
311 | #define BFM_SFC_SR_RREQ_V(v) BM_SFC_SR_RREQ | ||
312 | #define BP_SFC_SR_OVER 1 | ||
313 | #define BM_SFC_SR_OVER 0x2 | ||
314 | #define BF_SFC_SR_OVER(v) (((v) & 0x1) << 1) | ||
315 | #define BFM_SFC_SR_OVER(v) BM_SFC_SR_OVER | ||
316 | #define BF_SFC_SR_OVER_V(e) BF_SFC_SR_OVER(BV_SFC_SR_OVER__##e) | ||
317 | #define BFM_SFC_SR_OVER_V(v) BM_SFC_SR_OVER | ||
318 | #define BP_SFC_SR_UNDER 0 | ||
319 | #define BM_SFC_SR_UNDER 0x1 | ||
320 | #define BF_SFC_SR_UNDER(v) (((v) & 0x1) << 0) | ||
321 | #define BFM_SFC_SR_UNDER(v) BM_SFC_SR_UNDER | ||
322 | #define BF_SFC_SR_UNDER_V(e) BF_SFC_SR_UNDER(BV_SFC_SR_UNDER__##e) | ||
323 | #define BFM_SFC_SR_UNDER_V(v) BM_SFC_SR_UNDER | ||
324 | |||
325 | #define REG_SFC_SCR jz_reg(SFC_SCR) | ||
326 | #define JA_SFC_SCR (0xb3440000 + 0x6c) | ||
327 | #define JT_SFC_SCR JIO_32_RW | ||
328 | #define JN_SFC_SCR SFC_SCR | ||
329 | #define JI_SFC_SCR | ||
330 | #define BP_SFC_SCR_CLR_END 4 | ||
331 | #define BM_SFC_SCR_CLR_END 0x10 | ||
332 | #define BF_SFC_SCR_CLR_END(v) (((v) & 0x1) << 4) | ||
333 | #define BFM_SFC_SCR_CLR_END(v) BM_SFC_SCR_CLR_END | ||
334 | #define BF_SFC_SCR_CLR_END_V(e) BF_SFC_SCR_CLR_END(BV_SFC_SCR_CLR_END__##e) | ||
335 | #define BFM_SFC_SCR_CLR_END_V(v) BM_SFC_SCR_CLR_END | ||
336 | #define BP_SFC_SCR_CLR_TREQ 3 | ||
337 | #define BM_SFC_SCR_CLR_TREQ 0x8 | ||
338 | #define BF_SFC_SCR_CLR_TREQ(v) (((v) & 0x1) << 3) | ||
339 | #define BFM_SFC_SCR_CLR_TREQ(v) BM_SFC_SCR_CLR_TREQ | ||
340 | #define BF_SFC_SCR_CLR_TREQ_V(e) BF_SFC_SCR_CLR_TREQ(BV_SFC_SCR_CLR_TREQ__##e) | ||
341 | #define BFM_SFC_SCR_CLR_TREQ_V(v) BM_SFC_SCR_CLR_TREQ | ||
342 | #define BP_SFC_SCR_CLR_RREQ 2 | ||
343 | #define BM_SFC_SCR_CLR_RREQ 0x4 | ||
344 | #define BF_SFC_SCR_CLR_RREQ(v) (((v) & 0x1) << 2) | ||
345 | #define BFM_SFC_SCR_CLR_RREQ(v) BM_SFC_SCR_CLR_RREQ | ||
346 | #define BF_SFC_SCR_CLR_RREQ_V(e) BF_SFC_SCR_CLR_RREQ(BV_SFC_SCR_CLR_RREQ__##e) | ||
347 | #define BFM_SFC_SCR_CLR_RREQ_V(v) BM_SFC_SCR_CLR_RREQ | ||
348 | #define BP_SFC_SCR_CLR_OVER 1 | ||
349 | #define BM_SFC_SCR_CLR_OVER 0x2 | ||
350 | #define BF_SFC_SCR_CLR_OVER(v) (((v) & 0x1) << 1) | ||
351 | #define BFM_SFC_SCR_CLR_OVER(v) BM_SFC_SCR_CLR_OVER | ||
352 | #define BF_SFC_SCR_CLR_OVER_V(e) BF_SFC_SCR_CLR_OVER(BV_SFC_SCR_CLR_OVER__##e) | ||
353 | #define BFM_SFC_SCR_CLR_OVER_V(v) BM_SFC_SCR_CLR_OVER | ||
354 | #define BP_SFC_SCR_CLR_UNDER 0 | ||
355 | #define BM_SFC_SCR_CLR_UNDER 0x1 | ||
356 | #define BF_SFC_SCR_CLR_UNDER(v) (((v) & 0x1) << 0) | ||
357 | #define BFM_SFC_SCR_CLR_UNDER(v) BM_SFC_SCR_CLR_UNDER | ||
358 | #define BF_SFC_SCR_CLR_UNDER_V(e) BF_SFC_SCR_CLR_UNDER(BV_SFC_SCR_CLR_UNDER__##e) | ||
359 | #define BFM_SFC_SCR_CLR_UNDER_V(v) BM_SFC_SCR_CLR_UNDER | ||
360 | |||
361 | #define REG_SFC_INTC jz_reg(SFC_INTC) | ||
362 | #define JA_SFC_INTC (0xb3440000 + 0x70) | ||
363 | #define JT_SFC_INTC JIO_32_RW | ||
364 | #define JN_SFC_INTC SFC_INTC | ||
365 | #define JI_SFC_INTC | ||
366 | #define BP_SFC_INTC_MSK_END 4 | ||
367 | #define BM_SFC_INTC_MSK_END 0x10 | ||
368 | #define BF_SFC_INTC_MSK_END(v) (((v) & 0x1) << 4) | ||
369 | #define BFM_SFC_INTC_MSK_END(v) BM_SFC_INTC_MSK_END | ||
370 | #define BF_SFC_INTC_MSK_END_V(e) BF_SFC_INTC_MSK_END(BV_SFC_INTC_MSK_END__##e) | ||
371 | #define BFM_SFC_INTC_MSK_END_V(v) BM_SFC_INTC_MSK_END | ||
372 | #define BP_SFC_INTC_MSK_TREQ 3 | ||
373 | #define BM_SFC_INTC_MSK_TREQ 0x8 | ||
374 | #define BF_SFC_INTC_MSK_TREQ(v) (((v) & 0x1) << 3) | ||
375 | #define BFM_SFC_INTC_MSK_TREQ(v) BM_SFC_INTC_MSK_TREQ | ||
376 | #define BF_SFC_INTC_MSK_TREQ_V(e) BF_SFC_INTC_MSK_TREQ(BV_SFC_INTC_MSK_TREQ__##e) | ||
377 | #define BFM_SFC_INTC_MSK_TREQ_V(v) BM_SFC_INTC_MSK_TREQ | ||
378 | #define BP_SFC_INTC_MSK_RREQ 2 | ||
379 | #define BM_SFC_INTC_MSK_RREQ 0x4 | ||
380 | #define BF_SFC_INTC_MSK_RREQ(v) (((v) & 0x1) << 2) | ||
381 | #define BFM_SFC_INTC_MSK_RREQ(v) BM_SFC_INTC_MSK_RREQ | ||
382 | #define BF_SFC_INTC_MSK_RREQ_V(e) BF_SFC_INTC_MSK_RREQ(BV_SFC_INTC_MSK_RREQ__##e) | ||
383 | #define BFM_SFC_INTC_MSK_RREQ_V(v) BM_SFC_INTC_MSK_RREQ | ||
384 | #define BP_SFC_INTC_MSK_OVER 1 | ||
385 | #define BM_SFC_INTC_MSK_OVER 0x2 | ||
386 | #define BF_SFC_INTC_MSK_OVER(v) (((v) & 0x1) << 1) | ||
387 | #define BFM_SFC_INTC_MSK_OVER(v) BM_SFC_INTC_MSK_OVER | ||
388 | #define BF_SFC_INTC_MSK_OVER_V(e) BF_SFC_INTC_MSK_OVER(BV_SFC_INTC_MSK_OVER__##e) | ||
389 | #define BFM_SFC_INTC_MSK_OVER_V(v) BM_SFC_INTC_MSK_OVER | ||
390 | #define BP_SFC_INTC_MSK_UNDER 0 | ||
391 | #define BM_SFC_INTC_MSK_UNDER 0x1 | ||
392 | #define BF_SFC_INTC_MSK_UNDER(v) (((v) & 0x1) << 0) | ||
393 | #define BFM_SFC_INTC_MSK_UNDER(v) BM_SFC_INTC_MSK_UNDER | ||
394 | #define BF_SFC_INTC_MSK_UNDER_V(e) BF_SFC_INTC_MSK_UNDER(BV_SFC_INTC_MSK_UNDER__##e) | ||
395 | #define BFM_SFC_INTC_MSK_UNDER_V(v) BM_SFC_INTC_MSK_UNDER | ||
396 | |||
397 | #define REG_SFC_FSM jz_reg(SFC_FSM) | ||
398 | #define JA_SFC_FSM (0xb3440000 + 0x74) | ||
399 | #define JT_SFC_FSM JIO_32_RW | ||
400 | #define JN_SFC_FSM SFC_FSM | ||
401 | #define JI_SFC_FSM | ||
402 | #define BP_SFC_FSM_STATE_AHB 16 | ||
403 | #define BM_SFC_FSM_STATE_AHB 0xf0000 | ||
404 | #define BF_SFC_FSM_STATE_AHB(v) (((v) & 0xf) << 16) | ||
405 | #define BFM_SFC_FSM_STATE_AHB(v) BM_SFC_FSM_STATE_AHB | ||
406 | #define BF_SFC_FSM_STATE_AHB_V(e) BF_SFC_FSM_STATE_AHB(BV_SFC_FSM_STATE_AHB__##e) | ||
407 | #define BFM_SFC_FSM_STATE_AHB_V(v) BM_SFC_FSM_STATE_AHB | ||
408 | #define BP_SFC_FSM_STATE_SPI 11 | ||
409 | #define BM_SFC_FSM_STATE_SPI 0xf800 | ||
410 | #define BF_SFC_FSM_STATE_SPI(v) (((v) & 0x1f) << 11) | ||
411 | #define BFM_SFC_FSM_STATE_SPI(v) BM_SFC_FSM_STATE_SPI | ||
412 | #define BF_SFC_FSM_STATE_SPI_V(e) BF_SFC_FSM_STATE_SPI(BV_SFC_FSM_STATE_SPI__##e) | ||
413 | #define BFM_SFC_FSM_STATE_SPI_V(v) BM_SFC_FSM_STATE_SPI | ||
414 | #define BP_SFC_FSM_STATE_CLK 6 | ||
415 | #define BM_SFC_FSM_STATE_CLK 0x3c0 | ||
416 | #define BF_SFC_FSM_STATE_CLK(v) (((v) & 0xf) << 6) | ||
417 | #define BFM_SFC_FSM_STATE_CLK(v) BM_SFC_FSM_STATE_CLK | ||
418 | #define BF_SFC_FSM_STATE_CLK_V(e) BF_SFC_FSM_STATE_CLK(BV_SFC_FSM_STATE_CLK__##e) | ||
419 | #define BFM_SFC_FSM_STATE_CLK_V(v) BM_SFC_FSM_STATE_CLK | ||
420 | #define BP_SFC_FSM_STATE_DMAC 3 | ||
421 | #define BM_SFC_FSM_STATE_DMAC 0x38 | ||
422 | #define BF_SFC_FSM_STATE_DMAC(v) (((v) & 0x7) << 3) | ||
423 | #define BFM_SFC_FSM_STATE_DMAC(v) BM_SFC_FSM_STATE_DMAC | ||
424 | #define BF_SFC_FSM_STATE_DMAC_V(e) BF_SFC_FSM_STATE_DMAC(BV_SFC_FSM_STATE_DMAC__##e) | ||
425 | #define BFM_SFC_FSM_STATE_DMAC_V(v) BM_SFC_FSM_STATE_DMAC | ||
426 | #define BP_SFC_FSM_STATE_RMC 0 | ||
427 | #define BM_SFC_FSM_STATE_RMC 0x7 | ||
428 | #define BF_SFC_FSM_STATE_RMC(v) (((v) & 0x7) << 0) | ||
429 | #define BFM_SFC_FSM_STATE_RMC(v) BM_SFC_FSM_STATE_RMC | ||
430 | #define BF_SFC_FSM_STATE_RMC_V(e) BF_SFC_FSM_STATE_RMC(BV_SFC_FSM_STATE_RMC__##e) | ||
431 | #define BFM_SFC_FSM_STATE_RMC_V(v) BM_SFC_FSM_STATE_RMC | ||
432 | |||
433 | #define REG_SFC_CGE jz_reg(SFC_CGE) | ||
434 | #define JA_SFC_CGE (0xb3440000 + 0x78) | ||
435 | #define JT_SFC_CGE JIO_32_RW | ||
436 | #define JN_SFC_CGE SFC_CGE | ||
437 | #define JI_SFC_CGE | ||
438 | #define BP_SFC_CGE_SFC 5 | ||
439 | #define BM_SFC_CGE_SFC 0x20 | ||
440 | #define BF_SFC_CGE_SFC(v) (((v) & 0x1) << 5) | ||
441 | #define BFM_SFC_CGE_SFC(v) BM_SFC_CGE_SFC | ||
442 | #define BF_SFC_CGE_SFC_V(e) BF_SFC_CGE_SFC(BV_SFC_CGE_SFC__##e) | ||
443 | #define BFM_SFC_CGE_SFC_V(v) BM_SFC_CGE_SFC | ||
444 | #define BP_SFC_CGE_FIFO 4 | ||
445 | #define BM_SFC_CGE_FIFO 0x10 | ||
446 | #define BF_SFC_CGE_FIFO(v) (((v) & 0x1) << 4) | ||
447 | #define BFM_SFC_CGE_FIFO(v) BM_SFC_CGE_FIFO | ||
448 | #define BF_SFC_CGE_FIFO_V(e) BF_SFC_CGE_FIFO(BV_SFC_CGE_FIFO__##e) | ||
449 | #define BFM_SFC_CGE_FIFO_V(v) BM_SFC_CGE_FIFO | ||
450 | #define BP_SFC_CGE_DMA 3 | ||
451 | #define BM_SFC_CGE_DMA 0x8 | ||
452 | #define BF_SFC_CGE_DMA(v) (((v) & 0x1) << 3) | ||
453 | #define BFM_SFC_CGE_DMA(v) BM_SFC_CGE_DMA | ||
454 | #define BF_SFC_CGE_DMA_V(e) BF_SFC_CGE_DMA(BV_SFC_CGE_DMA__##e) | ||
455 | #define BFM_SFC_CGE_DMA_V(v) BM_SFC_CGE_DMA | ||
456 | #define BP_SFC_CGE_RMC 2 | ||
457 | #define BM_SFC_CGE_RMC 0x4 | ||
458 | #define BF_SFC_CGE_RMC(v) (((v) & 0x1) << 2) | ||
459 | #define BFM_SFC_CGE_RMC(v) BM_SFC_CGE_RMC | ||
460 | #define BF_SFC_CGE_RMC_V(e) BF_SFC_CGE_RMC(BV_SFC_CGE_RMC__##e) | ||
461 | #define BFM_SFC_CGE_RMC_V(v) BM_SFC_CGE_RMC | ||
462 | #define BP_SFC_CGE_SPI 1 | ||
463 | #define BM_SFC_CGE_SPI 0x2 | ||
464 | #define BF_SFC_CGE_SPI(v) (((v) & 0x1) << 1) | ||
465 | #define BFM_SFC_CGE_SPI(v) BM_SFC_CGE_SPI | ||
466 | #define BF_SFC_CGE_SPI_V(e) BF_SFC_CGE_SPI(BV_SFC_CGE_SPI__##e) | ||
467 | #define BFM_SFC_CGE_SPI_V(v) BM_SFC_CGE_SPI | ||
468 | #define BP_SFC_CGE_REG 0 | ||
469 | #define BM_SFC_CGE_REG 0x1 | ||
470 | #define BF_SFC_CGE_REG(v) (((v) & 0x1) << 0) | ||
471 | #define BFM_SFC_CGE_REG(v) BM_SFC_CGE_REG | ||
472 | #define BF_SFC_CGE_REG_V(e) BF_SFC_CGE_REG(BV_SFC_CGE_REG__##e) | ||
473 | #define BFM_SFC_CGE_REG_V(v) BM_SFC_CGE_REG | ||
474 | |||
475 | #define REG_SFC_DATA jz_reg(SFC_DATA) | ||
476 | #define JA_SFC_DATA (0xb3440000 + 0x1000) | ||
477 | #define JT_SFC_DATA JIO_32_RW | ||
478 | #define JN_SFC_DATA SFC_DATA | ||
479 | #define JI_SFC_DATA | ||
480 | |||
481 | #endif /* __HEADERGEN_SFC_H__*/ | ||