1 files changed, 221 insertions, 0 deletions

diff --git a/firmware/target/mips/ingenic_x1000/x1000/rtc.h b/firmware/target/mips/ingenic_x1000/x1000/rtc.h
new file mode 100644
index 0000000000..38f82e7d0d
--- /dev/null
+++ b/firmware/target/mips/ingenic_x1000/x1000/rtc.h
@@ -0,0 +1,221 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * x1000 version: 1.0
+ * x1000 authors: Aidan MacDonald
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN_RTC_H__
+#define __HEADERGEN_RTC_H__
+
+#include "macro.h"
+
+#define REG_RTC_CR              jz_reg(RTC_CR)
+#define JA_RTC_CR               (0xb0003000 + 0x0)
+#define JT_RTC_CR               JIO_32_RW
+#define JN_RTC_CR               RTC_CR
+#define JI_RTC_CR               
+#define BP_RTC_CR_WRDY          7
+#define BM_RTC_CR_WRDY          0x80
+#define BF_RTC_CR_WRDY(v)       (((v) & 0x1) << 7)
+#define BFM_RTC_CR_WRDY(v)      BM_RTC_CR_WRDY
+#define BF_RTC_CR_WRDY_V(e)     BF_RTC_CR_WRDY(BV_RTC_CR_WRDY__##e)
+#define BFM_RTC_CR_WRDY_V(v)    BM_RTC_CR_WRDY
+#define BP_RTC_CR_1HZ           6
+#define BM_RTC_CR_1HZ           0x40
+#define BF_RTC_CR_1HZ(v)        (((v) & 0x1) << 6)
+#define BFM_RTC_CR_1HZ(v)       BM_RTC_CR_1HZ
+#define BF_RTC_CR_1HZ_V(e)      BF_RTC_CR_1HZ(BV_RTC_CR_1HZ__##e)
+#define BFM_RTC_CR_1HZ_V(v)     BM_RTC_CR_1HZ
+#define BP_RTC_CR_1HZIE         5
+#define BM_RTC_CR_1HZIE         0x20
+#define BF_RTC_CR_1HZIE(v)      (((v) & 0x1) << 5)
+#define BFM_RTC_CR_1HZIE(v)     BM_RTC_CR_1HZIE
+#define BF_RTC_CR_1HZIE_V(e)    BF_RTC_CR_1HZIE(BV_RTC_CR_1HZIE__##e)
+#define BFM_RTC_CR_1HZIE_V(v)   BM_RTC_CR_1HZIE
+#define BP_RTC_CR_AF            4
+#define BM_RTC_CR_AF            0x10
+#define BF_RTC_CR_AF(v)         (((v) & 0x1) << 4)
+#define BFM_RTC_CR_AF(v)        BM_RTC_CR_AF
+#define BF_RTC_CR_AF_V(e)       BF_RTC_CR_AF(BV_RTC_CR_AF__##e)
+#define BFM_RTC_CR_AF_V(v)      BM_RTC_CR_AF
+#define BP_RTC_CR_AIE           3
+#define BM_RTC_CR_AIE           0x8
+#define BF_RTC_CR_AIE(v)        (((v) & 0x1) << 3)
+#define BFM_RTC_CR_AIE(v)       BM_RTC_CR_AIE
+#define BF_RTC_CR_AIE_V(e)      BF_RTC_CR_AIE(BV_RTC_CR_AIE__##e)
+#define BFM_RTC_CR_AIE_V(v)     BM_RTC_CR_AIE
+#define BP_RTC_CR_AE            2
+#define BM_RTC_CR_AE            0x4
+#define BF_RTC_CR_AE(v)         (((v) & 0x1) << 2)
+#define BFM_RTC_CR_AE(v)        BM_RTC_CR_AE
+#define BF_RTC_CR_AE_V(e)       BF_RTC_CR_AE(BV_RTC_CR_AE__##e)
+#define BFM_RTC_CR_AE_V(v)      BM_RTC_CR_AE
+#define BP_RTC_CR_SELEXC        1
+#define BM_RTC_CR_SELEXC        0x2
+#define BF_RTC_CR_SELEXC(v)     (((v) & 0x1) << 1)
+#define BFM_RTC_CR_SELEXC(v)    BM_RTC_CR_SELEXC
+#define BF_RTC_CR_SELEXC_V(e)   BF_RTC_CR_SELEXC(BV_RTC_CR_SELEXC__##e)
+#define BFM_RTC_CR_SELEXC_V(v)  BM_RTC_CR_SELEXC
+#define BP_RTC_CR_ENABLE        0
+#define BM_RTC_CR_ENABLE        0x1
+#define BF_RTC_CR_ENABLE(v)     (((v) & 0x1) << 0)
+#define BFM_RTC_CR_ENABLE(v)    BM_RTC_CR_ENABLE
+#define BF_RTC_CR_ENABLE_V(e)   BF_RTC_CR_ENABLE(BV_RTC_CR_ENABLE__##e)
+#define BFM_RTC_CR_ENABLE_V(v)  BM_RTC_CR_ENABLE
+
+#define REG_RTC_SR  jz_reg(RTC_SR)
+#define JA_RTC_SR   (0xb0003000 + 0x4)
+#define JT_RTC_SR   JIO_32_RW
+#define JN_RTC_SR   RTC_SR
+#define JI_RTC_SR   
+
+#define REG_RTC_SAR jz_reg(RTC_SAR)
+#define JA_RTC_SAR  (0xb0003000 + 0x8)
+#define JT_RTC_SAR  JIO_32_RW
+#define JN_RTC_SAR  RTC_SAR
+#define JI_RTC_SAR  
+
+#define REG_RTC_GR              jz_reg(RTC_GR)
+#define JA_RTC_GR               (0xb0003000 + 0xc)
+#define JT_RTC_GR               JIO_32_RW
+#define JN_RTC_GR               RTC_GR
+#define JI_RTC_GR               
+#define BP_RTC_GR_ADJC          16
+#define BM_RTC_GR_ADJC          0x3ff0000
+#define BF_RTC_GR_ADJC(v)       (((v) & 0x3ff) << 16)
+#define BFM_RTC_GR_ADJC(v)      BM_RTC_GR_ADJC
+#define BF_RTC_GR_ADJC_V(e)     BF_RTC_GR_ADJC(BV_RTC_GR_ADJC__##e)
+#define BFM_RTC_GR_ADJC_V(v)    BM_RTC_GR_ADJC
+#define BP_RTC_GR_NC1HZ         0
+#define BM_RTC_GR_NC1HZ         0xffff
+#define BF_RTC_GR_NC1HZ(v)      (((v) & 0xffff) << 0)
+#define BFM_RTC_GR_NC1HZ(v)     BM_RTC_GR_NC1HZ
+#define BF_RTC_GR_NC1HZ_V(e)    BF_RTC_GR_NC1HZ(BV_RTC_GR_NC1HZ__##e)
+#define BFM_RTC_GR_NC1HZ_V(v)   BM_RTC_GR_NC1HZ
+#define BP_RTC_GR_LOCK          31
+#define BM_RTC_GR_LOCK          0x80000000
+#define BF_RTC_GR_LOCK(v)       (((v) & 0x1) << 31)
+#define BFM_RTC_GR_LOCK(v)      BM_RTC_GR_LOCK
+#define BF_RTC_GR_LOCK_V(e)     BF_RTC_GR_LOCK(BV_RTC_GR_LOCK__##e)
+#define BFM_RTC_GR_LOCK_V(v)    BM_RTC_GR_LOCK
+
+#define REG_RTC_HCR jz_reg(RTC_HCR)
+#define JA_RTC_HCR  (0xb0003000 + 0x20)
+#define JT_RTC_HCR  JIO_32_RW
+#define JN_RTC_HCR  RTC_HCR
+#define JI_RTC_HCR  
+
+#define REG_RTC_HWFCR   jz_reg(RTC_HWFCR)
+#define JA_RTC_HWFCR    (0xb0003000 + 0x24)
+#define JT_RTC_HWFCR    JIO_32_RW
+#define JN_RTC_HWFCR    RTC_HWFCR
+#define JI_RTC_HWFCR    
+
+#define REG_RTC_HRCR    jz_reg(RTC_HRCR)
+#define JA_RTC_HRCR     (0xb0003000 + 0x28)
+#define JT_RTC_HRCR     JIO_32_RW
+#define JN_RTC_HRCR     RTC_HRCR
+#define JI_RTC_HRCR     
+
+#define REG_RTC_HWCR            jz_reg(RTC_HWCR)
+#define JA_RTC_HWCR             (0xb0003000 + 0x2c)
+#define JT_RTC_HWCR             JIO_32_RW
+#define JN_RTC_HWCR             RTC_HWCR
+#define JI_RTC_HWCR             
+#define BP_RTC_HWCR_EPDET       3
+#define BM_RTC_HWCR_EPDET       0xfffffff8
+#define BF_RTC_HWCR_EPDET(v)    (((v) & 0x1fffffff) << 3)
+#define BFM_RTC_HWCR_EPDET(v)   BM_RTC_HWCR_EPDET
+#define BF_RTC_HWCR_EPDET_V(e)  BF_RTC_HWCR_EPDET(BV_RTC_HWCR_EPDET__##e)
+#define BFM_RTC_HWCR_EPDET_V(v) BM_RTC_HWCR_EPDET
+#define BP_RTC_HWCR_EALM        1
+#define BM_RTC_HWCR_EALM        0x2
+#define BF_RTC_HWCR_EALM(v)     (((v) & 0x1) << 1)
+#define BFM_RTC_HWCR_EALM(v)    BM_RTC_HWCR_EALM
+#define BF_RTC_HWCR_EALM_V(e)   BF_RTC_HWCR_EALM(BV_RTC_HWCR_EALM__##e)
+#define BFM_RTC_HWCR_EALM_V(v)  BM_RTC_HWCR_EALM
+
+#define REG_RTC_HWRSR           jz_reg(RTC_HWRSR)
+#define JA_RTC_HWRSR            (0xb0003000 + 0x30)
+#define JT_RTC_HWRSR            JIO_32_RW
+#define JN_RTC_HWRSR            RTC_HWRSR
+#define JI_RTC_HWRSR            
+#define BP_RTC_HWRSR_APD        8
+#define BM_RTC_HWRSR_APD        0x100
+#define BF_RTC_HWRSR_APD(v)     (((v) & 0x1) << 8)
+#define BFM_RTC_HWRSR_APD(v)    BM_RTC_HWRSR_APD
+#define BF_RTC_HWRSR_APD_V(e)   BF_RTC_HWRSR_APD(BV_RTC_HWRSR_APD__##e)
+#define BFM_RTC_HWRSR_APD_V(v)  BM_RTC_HWRSR_APD
+#define BP_RTC_HWRSR_HR         5
+#define BM_RTC_HWRSR_HR         0x20
+#define BF_RTC_HWRSR_HR(v)      (((v) & 0x1) << 5)
+#define BFM_RTC_HWRSR_HR(v)     BM_RTC_HWRSR_HR
+#define BF_RTC_HWRSR_HR_V(e)    BF_RTC_HWRSR_HR(BV_RTC_HWRSR_HR__##e)
+#define BFM_RTC_HWRSR_HR_V(v)   BM_RTC_HWRSR_HR
+#define BP_RTC_HWRSR_PPR        4
+#define BM_RTC_HWRSR_PPR        0x10
+#define BF_RTC_HWRSR_PPR(v)     (((v) & 0x1) << 4)
+#define BFM_RTC_HWRSR_PPR(v)    BM_RTC_HWRSR_PPR
+#define BF_RTC_HWRSR_PPR_V(e)   BF_RTC_HWRSR_PPR(BV_RTC_HWRSR_PPR__##e)
+#define BFM_RTC_HWRSR_PPR_V(v)  BM_RTC_HWRSR_PPR
+#define BP_RTC_HWRSR_PIN        1
+#define BM_RTC_HWRSR_PIN        0x2
+#define BF_RTC_HWRSR_PIN(v)     (((v) & 0x1) << 1)
+#define BFM_RTC_HWRSR_PIN(v)    BM_RTC_HWRSR_PIN
+#define BF_RTC_HWRSR_PIN_V(e)   BF_RTC_HWRSR_PIN(BV_RTC_HWRSR_PIN__##e)
+#define BFM_RTC_HWRSR_PIN_V(v)  BM_RTC_HWRSR_PIN
+#define BP_RTC_HWRSR_ALM        0
+#define BM_RTC_HWRSR_ALM        0x1
+#define BF_RTC_HWRSR_ALM(v)     (((v) & 0x1) << 0)
+#define BFM_RTC_HWRSR_ALM(v)    BM_RTC_HWRSR_ALM
+#define BF_RTC_HWRSR_ALM_V(e)   BF_RTC_HWRSR_ALM(BV_RTC_HWRSR_ALM__##e)
+#define BFM_RTC_HWRSR_ALM_V(v)  BM_RTC_HWRSR_ALM
+
+#define REG_RTC_HSPR    jz_reg(RTC_HSPR)
+#define JA_RTC_HSPR     (0xb0003000 + 0x34)
+#define JT_RTC_HSPR     JIO_32_RW
+#define JN_RTC_HSPR     RTC_HSPR
+#define JI_RTC_HSPR     
+
+#define REG_RTC_WENR                jz_reg(RTC_WENR)
+#define JA_RTC_WENR                 (0xb0003000 + 0x3c)
+#define JT_RTC_WENR                 JIO_32_RW
+#define JN_RTC_WENR                 RTC_WENR
+#define JI_RTC_WENR                 
+#define BP_RTC_WENR_WEN             31
+#define BM_RTC_WENR_WEN             0x80000000
+#define BF_RTC_WENR_WEN(v)          (((v) & 0x1) << 31)
+#define BFM_RTC_WENR_WEN(v)         BM_RTC_WENR_WEN
+#define BF_RTC_WENR_WEN_V(e)        BF_RTC_WENR_WEN(BV_RTC_WENR_WEN__##e)
+#define BFM_RTC_WENR_WEN_V(v)       BM_RTC_WENR_WEN
+#define BP_RTC_WENR_WENPAT          0
+#define BM_RTC_WENR_WENPAT          0xffff
+#define BF_RTC_WENR_WENPAT(v)       (((v) & 0xffff) << 0)
+#define BFM_RTC_WENR_WENPAT(v)      BM_RTC_WENR_WENPAT
+#define BF_RTC_WENR_WENPAT_V(e)     BF_RTC_WENR_WENPAT(BV_RTC_WENR_WENPAT__##e)
+#define BFM_RTC_WENR_WENPAT_V(v)    BM_RTC_WENR_WENPAT
+
+#define REG_RTC_WKUPPINCR   jz_reg(RTC_WKUPPINCR)
+#define JA_RTC_WKUPPINCR    (0xb0003000 + 0x48)
+#define JT_RTC_WKUPPINCR    JIO_32_RW
+#define JN_RTC_WKUPPINCR    RTC_WKUPPINCR
+#define JI_RTC_WKUPPINCR    
+
+#endif /* __HEADERGEN_RTC_H__*/