diff options
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/x1000/dma.h')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/dma.h | 112 |
1 files changed, 112 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/x1000/dma.h b/firmware/target/mips/ingenic_x1000/x1000/dma.h new file mode 100644 index 0000000000..516c6e6849 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/dma.h | |||
@@ -0,0 +1,112 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_DMA_H__ | ||
25 | #define __HEADERGEN_DMA_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_DMA_CTRL jz_reg(DMA_CTRL) | ||
30 | #define JA_DMA_CTRL (0xb3421000 + 0x0) | ||
31 | #define JT_DMA_CTRL JIO_32_RW | ||
32 | #define JN_DMA_CTRL DMA_CTRL | ||
33 | #define JI_DMA_CTRL | ||
34 | #define BP_DMA_CTRL_FMSC 31 | ||
35 | #define BM_DMA_CTRL_FMSC 0x80000000 | ||
36 | #define BF_DMA_CTRL_FMSC(v) (((v) & 0x1) << 31) | ||
37 | #define BFM_DMA_CTRL_FMSC(v) BM_DMA_CTRL_FMSC | ||
38 | #define BF_DMA_CTRL_FMSC_V(e) BF_DMA_CTRL_FMSC(BV_DMA_CTRL_FMSC__##e) | ||
39 | #define BFM_DMA_CTRL_FMSC_V(v) BM_DMA_CTRL_FMSC | ||
40 | #define BP_DMA_CTRL_FSSI 30 | ||
41 | #define BM_DMA_CTRL_FSSI 0x40000000 | ||
42 | #define BF_DMA_CTRL_FSSI(v) (((v) & 0x1) << 30) | ||
43 | #define BFM_DMA_CTRL_FSSI(v) BM_DMA_CTRL_FSSI | ||
44 | #define BF_DMA_CTRL_FSSI_V(e) BF_DMA_CTRL_FSSI(BV_DMA_CTRL_FSSI__##e) | ||
45 | #define BFM_DMA_CTRL_FSSI_V(v) BM_DMA_CTRL_FSSI | ||
46 | #define BP_DMA_CTRL_FTSSI 29 | ||
47 | #define BM_DMA_CTRL_FTSSI 0x20000000 | ||
48 | #define BF_DMA_CTRL_FTSSI(v) (((v) & 0x1) << 29) | ||
49 | #define BFM_DMA_CTRL_FTSSI(v) BM_DMA_CTRL_FTSSI | ||
50 | #define BF_DMA_CTRL_FTSSI_V(e) BF_DMA_CTRL_FTSSI(BV_DMA_CTRL_FTSSI__##e) | ||
51 | #define BFM_DMA_CTRL_FTSSI_V(v) BM_DMA_CTRL_FTSSI | ||
52 | #define BP_DMA_CTRL_FUART 28 | ||
53 | #define BM_DMA_CTRL_FUART 0x10000000 | ||
54 | #define BF_DMA_CTRL_FUART(v) (((v) & 0x1) << 28) | ||
55 | #define BFM_DMA_CTRL_FUART(v) BM_DMA_CTRL_FUART | ||
56 | #define BF_DMA_CTRL_FUART_V(e) BF_DMA_CTRL_FUART(BV_DMA_CTRL_FUART__##e) | ||
57 | #define BFM_DMA_CTRL_FUART_V(v) BM_DMA_CTRL_FUART | ||
58 | #define BP_DMA_CTRL_FAIC 27 | ||
59 | #define BM_DMA_CTRL_FAIC 0x8000000 | ||
60 | #define BF_DMA_CTRL_FAIC(v) (((v) & 0x1) << 27) | ||
61 | #define BFM_DMA_CTRL_FAIC(v) BM_DMA_CTRL_FAIC | ||
62 | #define BF_DMA_CTRL_FAIC_V(e) BF_DMA_CTRL_FAIC(BV_DMA_CTRL_FAIC__##e) | ||
63 | #define BFM_DMA_CTRL_FAIC_V(v) BM_DMA_CTRL_FAIC | ||
64 | #define BP_DMA_CTRL_HALT 3 | ||
65 | #define BM_DMA_CTRL_HALT 0x8 | ||
66 | #define BF_DMA_CTRL_HALT(v) (((v) & 0x1) << 3) | ||
67 | #define BFM_DMA_CTRL_HALT(v) BM_DMA_CTRL_HALT | ||
68 | #define BF_DMA_CTRL_HALT_V(e) BF_DMA_CTRL_HALT(BV_DMA_CTRL_HALT__##e) | ||
69 | #define BFM_DMA_CTRL_HALT_V(v) BM_DMA_CTRL_HALT | ||
70 | #define BP_DMA_CTRL_AR 2 | ||
71 | #define BM_DMA_CTRL_AR 0x4 | ||
72 | #define BF_DMA_CTRL_AR(v) (((v) & 0x1) << 2) | ||
73 | #define BFM_DMA_CTRL_AR(v) BM_DMA_CTRL_AR | ||
74 | #define BF_DMA_CTRL_AR_V(e) BF_DMA_CTRL_AR(BV_DMA_CTRL_AR__##e) | ||
75 | #define BFM_DMA_CTRL_AR_V(v) BM_DMA_CTRL_AR | ||
76 | #define BP_DMA_CTRL_ENABLE 0 | ||
77 | #define BM_DMA_CTRL_ENABLE 0x1 | ||
78 | #define BF_DMA_CTRL_ENABLE(v) (((v) & 0x1) << 0) | ||
79 | #define BFM_DMA_CTRL_ENABLE(v) BM_DMA_CTRL_ENABLE | ||
80 | #define BF_DMA_CTRL_ENABLE_V(e) BF_DMA_CTRL_ENABLE(BV_DMA_CTRL_ENABLE__##e) | ||
81 | #define BFM_DMA_CTRL_ENABLE_V(v) BM_DMA_CTRL_ENABLE | ||
82 | |||
83 | #define REG_DMA_IRQP jz_reg(DMA_IRQP) | ||
84 | #define JA_DMA_IRQP (0xb3421000 + 0x4) | ||
85 | #define JT_DMA_IRQP JIO_32_RW | ||
86 | #define JN_DMA_IRQP DMA_IRQP | ||
87 | #define JI_DMA_IRQP | ||
88 | |||
89 | #define REG_DMA_DB jz_reg(DMA_DB) | ||
90 | #define JA_DMA_DB (0xb3421000 + 0x8) | ||
91 | #define JT_DMA_DB JIO_32_RW | ||
92 | #define JN_DMA_DB DMA_DB | ||
93 | #define JI_DMA_DB | ||
94 | #define REG_DMA_DB_SET jz_reg(DMA_DB_SET) | ||
95 | #define JA_DMA_DB_SET (JA_DMA_DB + 0x4) | ||
96 | #define JT_DMA_DB_SET JIO_32_WO | ||
97 | #define JN_DMA_DB_SET DMA_DB | ||
98 | #define JI_DMA_DB_SET | ||
99 | |||
100 | #define REG_DMA_DIP jz_reg(DMA_DIP) | ||
101 | #define JA_DMA_DIP (0xb3421000 + 0x10) | ||
102 | #define JT_DMA_DIP JIO_32_RW | ||
103 | #define JN_DMA_DIP DMA_DIP | ||
104 | #define JI_DMA_DIP | ||
105 | |||
106 | #define REG_DMA_DIC jz_reg(DMA_DIC) | ||
107 | #define JA_DMA_DIC (0xb3421000 + 0x14) | ||
108 | #define JT_DMA_DIC JIO_32_RW | ||
109 | #define JN_DMA_DIC DMA_DIC | ||
110 | #define JI_DMA_DIC | ||
111 | |||
112 | #endif /* __HEADERGEN_DMA_H__*/ | ||