diff options
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/x1000/aic.h')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/aic.h | 258 |
1 files changed, 258 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/x1000/aic.h b/firmware/target/mips/ingenic_x1000/x1000/aic.h index e9c68511d7..d212ddc4e1 100644 --- a/firmware/target/mips/ingenic_x1000/x1000/aic.h +++ b/firmware/target/mips/ingenic_x1000/x1000/aic.h | |||
@@ -356,4 +356,262 @@ | |||
356 | #define JN_AIC_DR AIC_DR | 356 | #define JN_AIC_DR AIC_DR |
357 | #define JI_AIC_DR | 357 | #define JI_AIC_DR |
358 | 358 | ||
359 | #define REG_AIC_SPENA jz_reg(AIC_SPENA) | ||
360 | #define JA_AIC_SPENA (0xb0020000 + 0x80) | ||
361 | #define JT_AIC_SPENA JIO_32_RW | ||
362 | #define JN_AIC_SPENA AIC_SPENA | ||
363 | #define JI_AIC_SPENA | ||
364 | |||
365 | #define REG_AIC_SPCTRL jz_reg(AIC_SPCTRL) | ||
366 | #define JA_AIC_SPCTRL (0xb0020000 + 0x84) | ||
367 | #define JT_AIC_SPCTRL JIO_32_RW | ||
368 | #define JN_AIC_SPCTRL AIC_SPCTRL | ||
369 | #define JI_AIC_SPCTRL | ||
370 | #define BP_AIC_SPCTRL_DMA_EN 15 | ||
371 | #define BM_AIC_SPCTRL_DMA_EN 0x8000 | ||
372 | #define BF_AIC_SPCTRL_DMA_EN(v) (((v) & 0x1) << 15) | ||
373 | #define BFM_AIC_SPCTRL_DMA_EN(v) BM_AIC_SPCTRL_DMA_EN | ||
374 | #define BF_AIC_SPCTRL_DMA_EN_V(e) BF_AIC_SPCTRL_DMA_EN(BV_AIC_SPCTRL_DMA_EN__##e) | ||
375 | #define BFM_AIC_SPCTRL_DMA_EN_V(v) BM_AIC_SPCTRL_DMA_EN | ||
376 | #define BP_AIC_SPCTRL_D_TYPE 14 | ||
377 | #define BM_AIC_SPCTRL_D_TYPE 0x4000 | ||
378 | #define BF_AIC_SPCTRL_D_TYPE(v) (((v) & 0x1) << 14) | ||
379 | #define BFM_AIC_SPCTRL_D_TYPE(v) BM_AIC_SPCTRL_D_TYPE | ||
380 | #define BF_AIC_SPCTRL_D_TYPE_V(e) BF_AIC_SPCTRL_D_TYPE(BV_AIC_SPCTRL_D_TYPE__##e) | ||
381 | #define BFM_AIC_SPCTRL_D_TYPE_V(v) BM_AIC_SPCTRL_D_TYPE | ||
382 | #define BP_AIC_SPCTRL_SIGN_N 13 | ||
383 | #define BM_AIC_SPCTRL_SIGN_N 0x2000 | ||
384 | #define BF_AIC_SPCTRL_SIGN_N(v) (((v) & 0x1) << 13) | ||
385 | #define BFM_AIC_SPCTRL_SIGN_N(v) BM_AIC_SPCTRL_SIGN_N | ||
386 | #define BF_AIC_SPCTRL_SIGN_N_V(e) BF_AIC_SPCTRL_SIGN_N(BV_AIC_SPCTRL_SIGN_N__##e) | ||
387 | #define BFM_AIC_SPCTRL_SIGN_N_V(v) BM_AIC_SPCTRL_SIGN_N | ||
388 | #define BP_AIC_SPCTRL_INVALID 12 | ||
389 | #define BM_AIC_SPCTRL_INVALID 0x1000 | ||
390 | #define BF_AIC_SPCTRL_INVALID(v) (((v) & 0x1) << 12) | ||
391 | #define BFM_AIC_SPCTRL_INVALID(v) BM_AIC_SPCTRL_INVALID | ||
392 | #define BF_AIC_SPCTRL_INVALID_V(e) BF_AIC_SPCTRL_INVALID(BV_AIC_SPCTRL_INVALID__##e) | ||
393 | #define BFM_AIC_SPCTRL_INVALID_V(v) BM_AIC_SPCTRL_INVALID | ||
394 | #define BP_AIC_SPCTRL_SFT_RST 11 | ||
395 | #define BM_AIC_SPCTRL_SFT_RST 0x800 | ||
396 | #define BF_AIC_SPCTRL_SFT_RST(v) (((v) & 0x1) << 11) | ||
397 | #define BFM_AIC_SPCTRL_SFT_RST(v) BM_AIC_SPCTRL_SFT_RST | ||
398 | #define BF_AIC_SPCTRL_SFT_RST_V(e) BF_AIC_SPCTRL_SFT_RST(BV_AIC_SPCTRL_SFT_RST__##e) | ||
399 | #define BFM_AIC_SPCTRL_SFT_RST_V(v) BM_AIC_SPCTRL_SFT_RST | ||
400 | #define BP_AIC_SPCTRL_SPDIF_I2S 10 | ||
401 | #define BM_AIC_SPCTRL_SPDIF_I2S 0x400 | ||
402 | #define BF_AIC_SPCTRL_SPDIF_I2S(v) (((v) & 0x1) << 10) | ||
403 | #define BFM_AIC_SPCTRL_SPDIF_I2S(v) BM_AIC_SPCTRL_SPDIF_I2S | ||
404 | #define BF_AIC_SPCTRL_SPDIF_I2S_V(e) BF_AIC_SPCTRL_SPDIF_I2S(BV_AIC_SPCTRL_SPDIF_I2S__##e) | ||
405 | #define BFM_AIC_SPCTRL_SPDIF_I2S_V(v) BM_AIC_SPCTRL_SPDIF_I2S | ||
406 | #define BP_AIC_SPCTRL_M_TRIG 1 | ||
407 | #define BM_AIC_SPCTRL_M_TRIG 0x2 | ||
408 | #define BF_AIC_SPCTRL_M_TRIG(v) (((v) & 0x1) << 1) | ||
409 | #define BFM_AIC_SPCTRL_M_TRIG(v) BM_AIC_SPCTRL_M_TRIG | ||
410 | #define BF_AIC_SPCTRL_M_TRIG_V(e) BF_AIC_SPCTRL_M_TRIG(BV_AIC_SPCTRL_M_TRIG__##e) | ||
411 | #define BFM_AIC_SPCTRL_M_TRIG_V(v) BM_AIC_SPCTRL_M_TRIG | ||
412 | #define BP_AIC_SPCTRL_M_FFUR 0 | ||
413 | #define BM_AIC_SPCTRL_M_FFUR 0x1 | ||
414 | #define BF_AIC_SPCTRL_M_FFUR(v) (((v) & 0x1) << 0) | ||
415 | #define BFM_AIC_SPCTRL_M_FFUR(v) BM_AIC_SPCTRL_M_FFUR | ||
416 | #define BF_AIC_SPCTRL_M_FFUR_V(e) BF_AIC_SPCTRL_M_FFUR(BV_AIC_SPCTRL_M_FFUR__##e) | ||
417 | #define BFM_AIC_SPCTRL_M_FFUR_V(v) BM_AIC_SPCTRL_M_FFUR | ||
418 | |||
419 | #define REG_AIC_SPSTATE jz_reg(AIC_SPSTATE) | ||
420 | #define JA_AIC_SPSTATE (0xb0020000 + 0x88) | ||
421 | #define JT_AIC_SPSTATE JIO_32_RW | ||
422 | #define JN_AIC_SPSTATE AIC_SPSTATE | ||
423 | #define JI_AIC_SPSTATE | ||
424 | #define BP_AIC_SPSTATE_FIFO_LEVEL 8 | ||
425 | #define BM_AIC_SPSTATE_FIFO_LEVEL 0x7f00 | ||
426 | #define BF_AIC_SPSTATE_FIFO_LEVEL(v) (((v) & 0x7f) << 8) | ||
427 | #define BFM_AIC_SPSTATE_FIFO_LEVEL(v) BM_AIC_SPSTATE_FIFO_LEVEL | ||
428 | #define BF_AIC_SPSTATE_FIFO_LEVEL_V(e) BF_AIC_SPSTATE_FIFO_LEVEL(BV_AIC_SPSTATE_FIFO_LEVEL__##e) | ||
429 | #define BFM_AIC_SPSTATE_FIFO_LEVEL_V(v) BM_AIC_SPSTATE_FIFO_LEVEL | ||
430 | #define BP_AIC_SPSTATE_BUSY 7 | ||
431 | #define BM_AIC_SPSTATE_BUSY 0x80 | ||
432 | #define BF_AIC_SPSTATE_BUSY(v) (((v) & 0x1) << 7) | ||
433 | #define BFM_AIC_SPSTATE_BUSY(v) BM_AIC_SPSTATE_BUSY | ||
434 | #define BF_AIC_SPSTATE_BUSY_V(e) BF_AIC_SPSTATE_BUSY(BV_AIC_SPSTATE_BUSY__##e) | ||
435 | #define BFM_AIC_SPSTATE_BUSY_V(v) BM_AIC_SPSTATE_BUSY | ||
436 | #define BP_AIC_SPSTATE_F_TRIG 1 | ||
437 | #define BM_AIC_SPSTATE_F_TRIG 0x2 | ||
438 | #define BF_AIC_SPSTATE_F_TRIG(v) (((v) & 0x1) << 1) | ||
439 | #define BFM_AIC_SPSTATE_F_TRIG(v) BM_AIC_SPSTATE_F_TRIG | ||
440 | #define BF_AIC_SPSTATE_F_TRIG_V(e) BF_AIC_SPSTATE_F_TRIG(BV_AIC_SPSTATE_F_TRIG__##e) | ||
441 | #define BFM_AIC_SPSTATE_F_TRIG_V(v) BM_AIC_SPSTATE_F_TRIG | ||
442 | #define BP_AIC_SPSTATE_F_FFUR 0 | ||
443 | #define BM_AIC_SPSTATE_F_FFUR 0x1 | ||
444 | #define BF_AIC_SPSTATE_F_FFUR(v) (((v) & 0x1) << 0) | ||
445 | #define BFM_AIC_SPSTATE_F_FFUR(v) BM_AIC_SPSTATE_F_FFUR | ||
446 | #define BF_AIC_SPSTATE_F_FFUR_V(e) BF_AIC_SPSTATE_F_FFUR(BV_AIC_SPSTATE_F_FFUR__##e) | ||
447 | #define BFM_AIC_SPSTATE_F_FFUR_V(v) BM_AIC_SPSTATE_F_FFUR | ||
448 | |||
449 | #define REG_AIC_SPCFG1 jz_reg(AIC_SPCFG1) | ||
450 | #define JA_AIC_SPCFG1 (0xb0020000 + 0x8c) | ||
451 | #define JT_AIC_SPCFG1 JIO_32_RW | ||
452 | #define JN_AIC_SPCFG1 AIC_SPCFG1 | ||
453 | #define JI_AIC_SPCFG1 | ||
454 | #define BP_AIC_SPCFG1_TRIG 12 | ||
455 | #define BM_AIC_SPCFG1_TRIG 0x3000 | ||
456 | #define BF_AIC_SPCFG1_TRIG(v) (((v) & 0x3) << 12) | ||
457 | #define BFM_AIC_SPCFG1_TRIG(v) BM_AIC_SPCFG1_TRIG | ||
458 | #define BF_AIC_SPCFG1_TRIG_V(e) BF_AIC_SPCFG1_TRIG(BV_AIC_SPCFG1_TRIG__##e) | ||
459 | #define BFM_AIC_SPCFG1_TRIG_V(v) BM_AIC_SPCFG1_TRIG | ||
460 | #define BP_AIC_SPCFG1_SRC_NUM 8 | ||
461 | #define BM_AIC_SPCFG1_SRC_NUM 0xf00 | ||
462 | #define BF_AIC_SPCFG1_SRC_NUM(v) (((v) & 0xf) << 8) | ||
463 | #define BFM_AIC_SPCFG1_SRC_NUM(v) BM_AIC_SPCFG1_SRC_NUM | ||
464 | #define BF_AIC_SPCFG1_SRC_NUM_V(e) BF_AIC_SPCFG1_SRC_NUM(BV_AIC_SPCFG1_SRC_NUM__##e) | ||
465 | #define BFM_AIC_SPCFG1_SRC_NUM_V(v) BM_AIC_SPCFG1_SRC_NUM | ||
466 | #define BP_AIC_SPCFG1_CH1_NUM 4 | ||
467 | #define BM_AIC_SPCFG1_CH1_NUM 0xf0 | ||
468 | #define BF_AIC_SPCFG1_CH1_NUM(v) (((v) & 0xf) << 4) | ||
469 | #define BFM_AIC_SPCFG1_CH1_NUM(v) BM_AIC_SPCFG1_CH1_NUM | ||
470 | #define BF_AIC_SPCFG1_CH1_NUM_V(e) BF_AIC_SPCFG1_CH1_NUM(BV_AIC_SPCFG1_CH1_NUM__##e) | ||
471 | #define BFM_AIC_SPCFG1_CH1_NUM_V(v) BM_AIC_SPCFG1_CH1_NUM | ||
472 | #define BP_AIC_SPCFG1_CH2_NUM 0 | ||
473 | #define BM_AIC_SPCFG1_CH2_NUM 0xf | ||
474 | #define BF_AIC_SPCFG1_CH2_NUM(v) (((v) & 0xf) << 0) | ||
475 | #define BFM_AIC_SPCFG1_CH2_NUM(v) BM_AIC_SPCFG1_CH2_NUM | ||
476 | #define BF_AIC_SPCFG1_CH2_NUM_V(e) BF_AIC_SPCFG1_CH2_NUM(BV_AIC_SPCFG1_CH2_NUM__##e) | ||
477 | #define BFM_AIC_SPCFG1_CH2_NUM_V(v) BM_AIC_SPCFG1_CH2_NUM | ||
478 | #define BP_AIC_SPCFG1_INIT_LEVEL 17 | ||
479 | #define BM_AIC_SPCFG1_INIT_LEVEL 0x20000 | ||
480 | #define BF_AIC_SPCFG1_INIT_LEVEL(v) (((v) & 0x1) << 17) | ||
481 | #define BFM_AIC_SPCFG1_INIT_LEVEL(v) BM_AIC_SPCFG1_INIT_LEVEL | ||
482 | #define BF_AIC_SPCFG1_INIT_LEVEL_V(e) BF_AIC_SPCFG1_INIT_LEVEL(BV_AIC_SPCFG1_INIT_LEVEL__##e) | ||
483 | #define BFM_AIC_SPCFG1_INIT_LEVEL_V(v) BM_AIC_SPCFG1_INIT_LEVEL | ||
484 | #define BP_AIC_SPCFG1_ZERO_VALID 16 | ||
485 | #define BM_AIC_SPCFG1_ZERO_VALID 0x10000 | ||
486 | #define BF_AIC_SPCFG1_ZERO_VALID(v) (((v) & 0x1) << 16) | ||
487 | #define BFM_AIC_SPCFG1_ZERO_VALID(v) BM_AIC_SPCFG1_ZERO_VALID | ||
488 | #define BF_AIC_SPCFG1_ZERO_VALID_V(e) BF_AIC_SPCFG1_ZERO_VALID(BV_AIC_SPCFG1_ZERO_VALID__##e) | ||
489 | #define BFM_AIC_SPCFG1_ZERO_VALID_V(v) BM_AIC_SPCFG1_ZERO_VALID | ||
490 | |||
491 | #define REG_AIC_SPCFG2 jz_reg(AIC_SPCFG2) | ||
492 | #define JA_AIC_SPCFG2 (0xb0020000 + 0x90) | ||
493 | #define JT_AIC_SPCFG2 JIO_32_RW | ||
494 | #define JN_AIC_SPCFG2 AIC_SPCFG2 | ||
495 | #define JI_AIC_SPCFG2 | ||
496 | #define BP_AIC_SPCFG2_FS 26 | ||
497 | #define BM_AIC_SPCFG2_FS 0x3c000000 | ||
498 | #define BF_AIC_SPCFG2_FS(v) (((v) & 0xf) << 26) | ||
499 | #define BFM_AIC_SPCFG2_FS(v) BM_AIC_SPCFG2_FS | ||
500 | #define BF_AIC_SPCFG2_FS_V(e) BF_AIC_SPCFG2_FS(BV_AIC_SPCFG2_FS__##e) | ||
501 | #define BFM_AIC_SPCFG2_FS_V(v) BM_AIC_SPCFG2_FS | ||
502 | #define BP_AIC_SPCFG2_ORG_FRQ 22 | ||
503 | #define BM_AIC_SPCFG2_ORG_FRQ 0x3c00000 | ||
504 | #define BF_AIC_SPCFG2_ORG_FRQ(v) (((v) & 0xf) << 22) | ||
505 | #define BFM_AIC_SPCFG2_ORG_FRQ(v) BM_AIC_SPCFG2_ORG_FRQ | ||
506 | #define BF_AIC_SPCFG2_ORG_FRQ_V(e) BF_AIC_SPCFG2_ORG_FRQ(BV_AIC_SPCFG2_ORG_FRQ__##e) | ||
507 | #define BFM_AIC_SPCFG2_ORG_FRQ_V(v) BM_AIC_SPCFG2_ORG_FRQ | ||
508 | #define BP_AIC_SPCFG2_SAMPL_WL 19 | ||
509 | #define BM_AIC_SPCFG2_SAMPL_WL 0x380000 | ||
510 | #define BF_AIC_SPCFG2_SAMPL_WL(v) (((v) & 0x7) << 19) | ||
511 | #define BFM_AIC_SPCFG2_SAMPL_WL(v) BM_AIC_SPCFG2_SAMPL_WL | ||
512 | #define BF_AIC_SPCFG2_SAMPL_WL_V(e) BF_AIC_SPCFG2_SAMPL_WL(BV_AIC_SPCFG2_SAMPL_WL__##e) | ||
513 | #define BFM_AIC_SPCFG2_SAMPL_WL_V(v) BM_AIC_SPCFG2_SAMPL_WL | ||
514 | #define BP_AIC_SPCFG2_CLK_ACU 16 | ||
515 | #define BM_AIC_SPCFG2_CLK_ACU 0x30000 | ||
516 | #define BF_AIC_SPCFG2_CLK_ACU(v) (((v) & 0x3) << 16) | ||
517 | #define BFM_AIC_SPCFG2_CLK_ACU(v) BM_AIC_SPCFG2_CLK_ACU | ||
518 | #define BF_AIC_SPCFG2_CLK_ACU_V(e) BF_AIC_SPCFG2_CLK_ACU(BV_AIC_SPCFG2_CLK_ACU__##e) | ||
519 | #define BFM_AIC_SPCFG2_CLK_ACU_V(v) BM_AIC_SPCFG2_CLK_ACU | ||
520 | #define BP_AIC_SPCFG2_CAT_CODE 8 | ||
521 | #define BM_AIC_SPCFG2_CAT_CODE 0xff00 | ||
522 | #define BF_AIC_SPCFG2_CAT_CODE(v) (((v) & 0xff) << 8) | ||
523 | #define BFM_AIC_SPCFG2_CAT_CODE(v) BM_AIC_SPCFG2_CAT_CODE | ||
524 | #define BF_AIC_SPCFG2_CAT_CODE_V(e) BF_AIC_SPCFG2_CAT_CODE(BV_AIC_SPCFG2_CAT_CODE__##e) | ||
525 | #define BFM_AIC_SPCFG2_CAT_CODE_V(v) BM_AIC_SPCFG2_CAT_CODE | ||
526 | #define BP_AIC_SPCFG2_CH_MD 6 | ||
527 | #define BM_AIC_SPCFG2_CH_MD 0xc0 | ||
528 | #define BF_AIC_SPCFG2_CH_MD(v) (((v) & 0x3) << 6) | ||
529 | #define BFM_AIC_SPCFG2_CH_MD(v) BM_AIC_SPCFG2_CH_MD | ||
530 | #define BF_AIC_SPCFG2_CH_MD_V(e) BF_AIC_SPCFG2_CH_MD(BV_AIC_SPCFG2_CH_MD__##e) | ||
531 | #define BFM_AIC_SPCFG2_CH_MD_V(v) BM_AIC_SPCFG2_CH_MD | ||
532 | #define BP_AIC_SPCFG2_MAX_WL 18 | ||
533 | #define BM_AIC_SPCFG2_MAX_WL 0x40000 | ||
534 | #define BF_AIC_SPCFG2_MAX_WL(v) (((v) & 0x1) << 18) | ||
535 | #define BFM_AIC_SPCFG2_MAX_WL(v) BM_AIC_SPCFG2_MAX_WL | ||
536 | #define BF_AIC_SPCFG2_MAX_WL_V(e) BF_AIC_SPCFG2_MAX_WL(BV_AIC_SPCFG2_MAX_WL__##e) | ||
537 | #define BFM_AIC_SPCFG2_MAX_WL_V(v) BM_AIC_SPCFG2_MAX_WL | ||
538 | #define BP_AIC_SPCFG2_PRE 3 | ||
539 | #define BM_AIC_SPCFG2_PRE 0x8 | ||
540 | #define BF_AIC_SPCFG2_PRE(v) (((v) & 0x1) << 3) | ||
541 | #define BFM_AIC_SPCFG2_PRE(v) BM_AIC_SPCFG2_PRE | ||
542 | #define BF_AIC_SPCFG2_PRE_V(e) BF_AIC_SPCFG2_PRE(BV_AIC_SPCFG2_PRE__##e) | ||
543 | #define BFM_AIC_SPCFG2_PRE_V(v) BM_AIC_SPCFG2_PRE | ||
544 | #define BP_AIC_SPCFG2_COPY_N 2 | ||
545 | #define BM_AIC_SPCFG2_COPY_N 0x4 | ||
546 | #define BF_AIC_SPCFG2_COPY_N(v) (((v) & 0x1) << 2) | ||
547 | #define BFM_AIC_SPCFG2_COPY_N(v) BM_AIC_SPCFG2_COPY_N | ||
548 | #define BF_AIC_SPCFG2_COPY_N_V(e) BF_AIC_SPCFG2_COPY_N(BV_AIC_SPCFG2_COPY_N__##e) | ||
549 | #define BFM_AIC_SPCFG2_COPY_N_V(v) BM_AIC_SPCFG2_COPY_N | ||
550 | #define BP_AIC_SPCFG2_AUDIO_N 1 | ||
551 | #define BM_AIC_SPCFG2_AUDIO_N 0x2 | ||
552 | #define BF_AIC_SPCFG2_AUDIO_N(v) (((v) & 0x1) << 1) | ||
553 | #define BFM_AIC_SPCFG2_AUDIO_N(v) BM_AIC_SPCFG2_AUDIO_N | ||
554 | #define BF_AIC_SPCFG2_AUDIO_N_V(e) BF_AIC_SPCFG2_AUDIO_N(BV_AIC_SPCFG2_AUDIO_N__##e) | ||
555 | #define BFM_AIC_SPCFG2_AUDIO_N_V(v) BM_AIC_SPCFG2_AUDIO_N | ||
556 | #define BP_AIC_SPCFG2_CON_PRO 0 | ||
557 | #define BM_AIC_SPCFG2_CON_PRO 0x1 | ||
558 | #define BF_AIC_SPCFG2_CON_PRO(v) (((v) & 0x1) << 0) | ||
559 | #define BFM_AIC_SPCFG2_CON_PRO(v) BM_AIC_SPCFG2_CON_PRO | ||
560 | #define BF_AIC_SPCFG2_CON_PRO_V(e) BF_AIC_SPCFG2_CON_PRO(BV_AIC_SPCFG2_CON_PRO__##e) | ||
561 | #define BFM_AIC_SPCFG2_CON_PRO_V(v) BM_AIC_SPCFG2_CON_PRO | ||
562 | |||
563 | #define REG_AIC_SPFIFO jz_reg(AIC_SPFIFO) | ||
564 | #define JA_AIC_SPFIFO (0xb0020000 + 0x94) | ||
565 | #define JT_AIC_SPFIFO JIO_32_RW | ||
566 | #define JN_AIC_SPFIFO AIC_SPFIFO | ||
567 | #define JI_AIC_SPFIFO | ||
568 | |||
569 | #define REG_AIC_RGADW jz_reg(AIC_RGADW) | ||
570 | #define JA_AIC_RGADW (0xb0020000 + 0xa4) | ||
571 | #define JT_AIC_RGADW JIO_32_RW | ||
572 | #define JN_AIC_RGADW AIC_RGADW | ||
573 | #define JI_AIC_RGADW | ||
574 | #define BP_AIC_RGADW_ADDR 8 | ||
575 | #define BM_AIC_RGADW_ADDR 0x7f00 | ||
576 | #define BF_AIC_RGADW_ADDR(v) (((v) & 0x7f) << 8) | ||
577 | #define BFM_AIC_RGADW_ADDR(v) BM_AIC_RGADW_ADDR | ||
578 | #define BF_AIC_RGADW_ADDR_V(e) BF_AIC_RGADW_ADDR(BV_AIC_RGADW_ADDR__##e) | ||
579 | #define BFM_AIC_RGADW_ADDR_V(v) BM_AIC_RGADW_ADDR | ||
580 | #define BP_AIC_RGADW_DATA 0 | ||
581 | #define BM_AIC_RGADW_DATA 0xff | ||
582 | #define BF_AIC_RGADW_DATA(v) (((v) & 0xff) << 0) | ||
583 | #define BFM_AIC_RGADW_DATA(v) BM_AIC_RGADW_DATA | ||
584 | #define BF_AIC_RGADW_DATA_V(e) BF_AIC_RGADW_DATA(BV_AIC_RGADW_DATA__##e) | ||
585 | #define BFM_AIC_RGADW_DATA_V(v) BM_AIC_RGADW_DATA | ||
586 | #define BP_AIC_RGADW_ICRST 31 | ||
587 | #define BM_AIC_RGADW_ICRST 0x80000000 | ||
588 | #define BF_AIC_RGADW_ICRST(v) (((v) & 0x1) << 31) | ||
589 | #define BFM_AIC_RGADW_ICRST(v) BM_AIC_RGADW_ICRST | ||
590 | #define BF_AIC_RGADW_ICRST_V(e) BF_AIC_RGADW_ICRST(BV_AIC_RGADW_ICRST__##e) | ||
591 | #define BFM_AIC_RGADW_ICRST_V(v) BM_AIC_RGADW_ICRST | ||
592 | #define BP_AIC_RGADW_RGWR 16 | ||
593 | #define BM_AIC_RGADW_RGWR 0x10000 | ||
594 | #define BF_AIC_RGADW_RGWR(v) (((v) & 0x1) << 16) | ||
595 | #define BFM_AIC_RGADW_RGWR(v) BM_AIC_RGADW_RGWR | ||
596 | #define BF_AIC_RGADW_RGWR_V(e) BF_AIC_RGADW_RGWR(BV_AIC_RGADW_RGWR__##e) | ||
597 | #define BFM_AIC_RGADW_RGWR_V(v) BM_AIC_RGADW_RGWR | ||
598 | |||
599 | #define REG_AIC_RGDATA jz_reg(AIC_RGDATA) | ||
600 | #define JA_AIC_RGDATA (0xb0020000 + 0xa8) | ||
601 | #define JT_AIC_RGDATA JIO_32_RW | ||
602 | #define JN_AIC_RGDATA AIC_RGDATA | ||
603 | #define JI_AIC_RGDATA | ||
604 | #define BP_AIC_RGDATA_DATA 0 | ||
605 | #define BM_AIC_RGDATA_DATA 0xff | ||
606 | #define BF_AIC_RGDATA_DATA(v) (((v) & 0xff) << 0) | ||
607 | #define BFM_AIC_RGDATA_DATA(v) BM_AIC_RGDATA_DATA | ||
608 | #define BF_AIC_RGDATA_DATA_V(e) BF_AIC_RGDATA_DATA(BV_AIC_RGDATA_DATA__##e) | ||
609 | #define BFM_AIC_RGDATA_DATA_V(v) BM_AIC_RGDATA_DATA | ||
610 | #define BP_AIC_RGDATA_IRQ 8 | ||
611 | #define BM_AIC_RGDATA_IRQ 0x100 | ||
612 | #define BF_AIC_RGDATA_IRQ(v) (((v) & 0x1) << 8) | ||
613 | #define BFM_AIC_RGDATA_IRQ(v) BM_AIC_RGDATA_IRQ | ||
614 | #define BF_AIC_RGDATA_IRQ_V(e) BF_AIC_RGDATA_IRQ(BV_AIC_RGDATA_IRQ__##e) | ||
615 | #define BFM_AIC_RGDATA_IRQ_V(v) BM_AIC_RGDATA_IRQ | ||
616 | |||
359 | #endif /* __HEADERGEN_AIC_H__*/ | 617 | #endif /* __HEADERGEN_AIC_H__*/ |