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Diffstat (limited to 'firmware/target/mips/ingenic_x1000/nand-x1000.c')
-rw-r--r--firmware/target/mips/ingenic_x1000/nand-x1000.c17
1 files changed, 9 insertions, 8 deletions
diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.c b/firmware/target/mips/ingenic_x1000/nand-x1000.c
index fbac824789..5a21b1f8c2 100644
--- a/firmware/target/mips/ingenic_x1000/nand-x1000.c
+++ b/firmware/target/mips/ingenic_x1000/nand-x1000.c
@@ -46,9 +46,9 @@
46#define NAND_FREG_PROTECTION_BRWD 0x80 46#define NAND_FREG_PROTECTION_BRWD 0x80
47#define NAND_FREG_PROTECTION_BP2 0x20 47#define NAND_FREG_PROTECTION_BP2 0x20
48#define NAND_FREG_PROTECTION_BP1 0x10 48#define NAND_FREG_PROTECTION_BP1 0x10
49#define NAND_FREG_PROTECTION_BP0 0x80 49#define NAND_FREG_PROTECTION_BP0 0x08
50/* Mask of BP bits 0-2 */ 50/* Mask of BP bits 0-2 */
51#define NAND_FREG_PROTECTION_ALLBP (0x38) 51#define NAND_FREG_PROTECTION_ALLBP 0x38
52 52
53/* Feature register bits */ 53/* Feature register bits */
54#define NAND_FREG_FEATURE_QE 0x01 54#define NAND_FREG_FEATURE_QE 0x01
@@ -129,6 +129,7 @@ int nand_open(void)
129 sfc_set_dev_conf(chip_data->dev_conf); 129 sfc_set_dev_conf(chip_data->dev_conf);
130 sfc_set_clock(chip_data->clock_freq); 130 sfc_set_clock(chip_data->clock_freq);
131 131
132 sfc_unlock();
132 return NAND_SUCCESS; 133 return NAND_SUCCESS;
133} 134}
134 135
@@ -237,7 +238,7 @@ int nand_erase(uint32_t addr, uint32_t size)
237{ 238{
238 const uint32_t page_size = 1 << nand_drv.chip_data->log2_page_size; 239 const uint32_t page_size = 1 << nand_drv.chip_data->log2_page_size;
239 const uint32_t block_size = page_size << nand_drv.chip_data->log2_block_size; 240 const uint32_t block_size = page_size << nand_drv.chip_data->log2_block_size;
240 const uint32_t pages_per_block = 1 << nand_drv.chip_data->log2_page_size; 241 const uint32_t pages_per_block = 1 << nand_drv.chip_data->log2_block_size;
241 242
242 if(addr & (block_size - 1)) 243 if(addr & (block_size - 1))
243 return NAND_ERR_UNALIGNED; 244 return NAND_ERR_UNALIGNED;
@@ -333,13 +334,13 @@ static int nandop_set_write_protect(bool en)
333 return val; 334 return val;
334 335
335 if(en) { 336 if(en) {
336 val &= ~NAND_FREG_PROTECTION_ALLBP;
337 if(nand_drv.chip_data->flags & NANDCHIP_FLAG_USE_BRWD)
338 val &= ~NAND_FREG_PROTECTION_BRWD;
339 } else {
340 val |= NAND_FREG_PROTECTION_ALLBP; 337 val |= NAND_FREG_PROTECTION_ALLBP;
341 if(nand_drv.chip_data->flags & NANDCHIP_FLAG_USE_BRWD) 338 if(nand_drv.chip_data->flags & NANDCHIP_FLAG_USE_BRWD)
342 val |= NAND_FREG_PROTECTION_BRWD; 339 val |= NAND_FREG_PROTECTION_BRWD;
340 } else {
341 val &= ~NAND_FREG_PROTECTION_ALLBP;
342 if(nand_drv.chip_data->flags & NANDCHIP_FLAG_USE_BRWD)
343 val &= ~NAND_FREG_PROTECTION_BRWD;
343 } 344 }
344 345
345 /* NOTE: The WP pin typically only protects changes to the protection 346 /* NOTE: The WP pin typically only protects changes to the protection
@@ -406,7 +407,7 @@ static int nandcmd_set_feature(uint8_t reg, uint8_t val)
406{ 407{
407 sfc_op op = {0}; 408 sfc_op op = {0};
408 op.command = NAND_CMD_SET_FEATURE; 409 op.command = NAND_CMD_SET_FEATURE;
409 op.flags = SFC_FLAG_READ; 410 op.flags = SFC_FLAG_WRITE;
410 op.addr_bytes = 1; 411 op.addr_bytes = 1;
411 op.addr_lo = reg; 412 op.addr_lo = reg;
412 op.data_bytes = 1; 413 op.data_bytes = 1;