1 files changed, 34 insertions, 1 deletions

diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c b/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c
index 0ebe11e24d..7f4441c109 100644
--- a/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c
+++ b/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c
@@ -21,7 +21,7 @@
 
 #include "spl-x1000.h"
 #include "gpio-x1000.h"
-#include "nand-x1000.h"
+#include "clk-x1000.h"
 #include "system.h"
 #include <string.h>
 
@@ -130,3 +130,36 @@ int spl_get_boot_option(void)
     /* Default is to boot Rockbox */
     return SPL_BOOTOPT_ROCKBOX;
 }
+
+void spl_handle_pre_boot(int bootopt)
+{
+    /* Move system to EXCLK so we can manipulate the PLLs */
+    clk_set_ccr_mux(CLKMUX_SCLK_A(EXCLK) | CLKMUX_CPU(SCLK_A) |
+                    CLKMUX_AHB0(SCLK_A) | CLKMUX_AHB2(SCLK_A));
+    clk_set_ccr_div(1, 1, 1, 1, 1);
+
+    /* Enable APLL @ 1008 MHz (24 MHz EXCLK * 42 = 1008 MHz) */
+    jz_writef(CPM_APCR, BS(1), PLLM(41), PLLN(0), PLLOD(0), ENABLE(1));
+    while(jz_readf(CPM_APCR, ON) == 0);
+
+    /* System clock setup -- common to Rockbox and FiiO firmware
+     * ----
+     * CPU at 1 GHz, L2 cache at 500 MHz
+     * AHB0 and AHB2 and 200 MHz
+     * PCLK at 100 MHz
+     * DDR at 200 MHz
+     */
+    clk_set_ccr_div(1, 2, 5, 5, 10);
+    clk_set_ccr_mux(CLKMUX_SCLK_A(APLL) | CLKMUX_CPU(SCLK_A) |
+                    CLKMUX_AHB0(SCLK_A) | CLKMUX_AHB2(SCLK_A));
+
+    if(bootopt == SPL_BOOTOPT_ROCKBOX) {
+        /* We don't use MPLL in Rockbox, so switch DDR memory to APLL */
+        clk_set_ddr(X1000_CLK_SCLK_A, 5);
+
+        /* Turn off MPLL */
+        jz_writef(CPM_MPCR, ENABLE(0));
+    } else {
+        /* TODO: Original firmware needs a lot of other clocks turned on */
+    }
+}