diff options
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c | 38 |
1 files changed, 23 insertions, 15 deletions
diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c b/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c index bdd0ffc2e0..efea5aa323 100644 --- a/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c +++ b/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c | |||
@@ -25,6 +25,11 @@ | |||
25 | #include "system.h" | 25 | #include "system.h" |
26 | #include <string.h> | 26 | #include <string.h> |
27 | 27 | ||
28 | /* Available boot options */ | ||
29 | #define BOOTOPTION_ROCKBOX 0 | ||
30 | #define BOOTOPTION_ORIG_FW 1 | ||
31 | #define BOOTOPTION_RECOVERY 2 | ||
32 | |||
28 | /* Boot select button state must remain stable for this duration | 33 | /* Boot select button state must remain stable for this duration |
29 | * before the choice will be accepted. Currently 100ms. | 34 | * before the choice will be accepted. Currently 100ms. |
30 | */ | 35 | */ |
@@ -56,7 +61,7 @@ const struct spl_boot_option spl_boot_options[] = { | |||
56 | */ | 61 | */ |
57 | .nand_addr = 0x6800, | 62 | .nand_addr = 0x6800, |
58 | .nand_size = 0x19800, | 63 | .nand_size = 0x19800, |
59 | .load_addr = X1000_DRAM_BASE - 8, /* first 8 bytes are bootloader ID */ | 64 | .load_addr = X1000_DRAM_END - 0x19800, |
60 | .exec_addr = X1000_DRAM_BASE, | 65 | .exec_addr = X1000_DRAM_BASE, |
61 | .cmdline = NULL, | 66 | .cmdline = NULL, |
62 | }, | 67 | }, |
@@ -80,7 +85,7 @@ const struct spl_boot_option spl_boot_options[] = { | |||
80 | 85 | ||
81 | void spl_error(void) | 86 | void spl_error(void) |
82 | { | 87 | { |
83 | const int pin = (1 << 24); | 88 | const uint32_t pin = (1 << 24); |
84 | 89 | ||
85 | /* Turn on button light */ | 90 | /* Turn on button light */ |
86 | jz_clr(GPIO_INT(GPIO_C), pin); | 91 | jz_clr(GPIO_INT(GPIO_C), pin); |
@@ -105,6 +110,10 @@ int spl_get_boot_option(void) | |||
105 | 110 | ||
106 | uint32_t pin = 1, lastpin = 0; | 111 | uint32_t pin = 1, lastpin = 0; |
107 | uint32_t deadline = 0; | 112 | uint32_t deadline = 0; |
113 | /* Iteration count guards against unlikely case of broken buttons | ||
114 | * which never stabilize; if this occurs, we always boot Rockbox. */ | ||
115 | int iter_count = 0; | ||
116 | const int max_iter_count = 30; | ||
108 | 117 | ||
109 | /* Configure the button GPIOs as inputs */ | 118 | /* Configure the button GPIOs as inputs */ |
110 | gpio_config(GPIO_A, pinmask, GPIO_INPUT); | 119 | gpio_config(GPIO_A, pinmask, GPIO_INPUT); |
@@ -116,19 +125,18 @@ int spl_get_boot_option(void) | |||
116 | if(pin != lastpin) { | 125 | if(pin != lastpin) { |
117 | /* This will always be set on the first iteration */ | 126 | /* This will always be set on the first iteration */ |
118 | deadline = __ost_read32() + BTN_STABLE_TIME; | 127 | deadline = __ost_read32() + BTN_STABLE_TIME; |
128 | iter_count += 1; | ||
119 | } | 129 | } |
120 | } while(__ost_read32() < deadline); | 130 | } while(iter_count < max_iter_count && __ost_read32() < deadline); |
121 | |||
122 | /* Play button boots original firmware */ | ||
123 | if(pin == (1 << 17)) | ||
124 | return SPL_BOOTOPT_ORIG_FW; | ||
125 | |||
126 | /* Volume up boots recovery */ | ||
127 | if(pin == (1 << 19)) | ||
128 | return SPL_BOOTOPT_RECOVERY; | ||
129 | 131 | ||
130 | /* Default is to boot Rockbox */ | 132 | if(iter_count < max_iter_count && (pin & (1 << 17))) { |
131 | return SPL_BOOTOPT_ROCKBOX; | 133 | if(pin & (1 << 19)) |
134 | return BOOTOPTION_RECOVERY; /* Play+Volume Up */ | ||
135 | else | ||
136 | return BOOTOPTION_ORIG_FW; /* Play */ | ||
137 | } else { | ||
138 | return BOOTOPTION_ROCKBOX; /* Volume Up or no buttons */ | ||
139 | } | ||
132 | } | 140 | } |
133 | 141 | ||
134 | void spl_handle_pre_boot(int bootopt) | 142 | void spl_handle_pre_boot(int bootopt) |
@@ -145,7 +153,7 @@ void spl_handle_pre_boot(int bootopt) | |||
145 | /* System clock setup -- common to Rockbox and FiiO firmware | 153 | /* System clock setup -- common to Rockbox and FiiO firmware |
146 | * ---- | 154 | * ---- |
147 | * CPU at 1 GHz, L2 cache at 500 MHz | 155 | * CPU at 1 GHz, L2 cache at 500 MHz |
148 | * AHB0 and AHB2 and 200 MHz | 156 | * AHB0 and AHB2 at 200 MHz |
149 | * PCLK at 100 MHz | 157 | * PCLK at 100 MHz |
150 | * DDR at 200 MHz | 158 | * DDR at 200 MHz |
151 | */ | 159 | */ |
@@ -153,7 +161,7 @@ void spl_handle_pre_boot(int bootopt) | |||
153 | clk_set_ccr_mux(CLKMUX_SCLK_A(APLL) | CLKMUX_CPU(SCLK_A) | | 161 | clk_set_ccr_mux(CLKMUX_SCLK_A(APLL) | CLKMUX_CPU(SCLK_A) | |
154 | CLKMUX_AHB0(SCLK_A) | CLKMUX_AHB2(SCLK_A)); | 162 | CLKMUX_AHB0(SCLK_A) | CLKMUX_AHB2(SCLK_A)); |
155 | 163 | ||
156 | if(bootopt == SPL_BOOTOPT_ROCKBOX) { | 164 | if(bootopt == BOOTOPTION_ROCKBOX) { |
157 | /* We don't use MPLL in Rockbox, so switch DDR memory to APLL */ | 165 | /* We don't use MPLL in Rockbox, so switch DDR memory to APLL */ |
158 | clk_set_ddr(X1000_CLK_SCLK_A, 5); | 166 | clk_set_ddr(X1000_CLK_SCLK_A, 5); |
159 | 167 | ||