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Diffstat (limited to 'firmware/target/mips/ingenic_x1000/erosqnative/audiohw-erosqnative.c')
-rw-r--r--firmware/target/mips/ingenic_x1000/erosqnative/audiohw-erosqnative.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/erosqnative/audiohw-erosqnative.c b/firmware/target/mips/ingenic_x1000/erosqnative/audiohw-erosqnative.c
index 4bd3316889..6968a19a1c 100644
--- a/firmware/target/mips/ingenic_x1000/erosqnative/audiohw-erosqnative.c
+++ b/firmware/target/mips/ingenic_x1000/erosqnative/audiohw-erosqnative.c
@@ -104,6 +104,30 @@ void audiohw_postinit(void)
104 * for 24-bit data... */ 104 * for 24-bit data... */
105 // es9018k2m_write_reg(ES9018K2M_REG1_INPUT_CONFIG, 0b01001100); // 24-bit data 105 // es9018k2m_write_reg(ES9018K2M_REG1_INPUT_CONFIG, 0b01001100); // 24-bit data
106 106
107 /* Datasheet: Sets the number os FSR edges that must occur before *
108 * the DPLL and ASRC can lock on to the the incoming Signal. *
109 * When Samplerates >= 96khz could be used, STOP_DIV should be set *
110 * to 0 (= 16384 FSR Edges). *
111 * Reg #10 [3:0] (0x05 default, 2730 FSR Edges) */
112 es9018k2m_write_reg(ES9018K2M_REG10_MASTER_MODE_CTRL, 0x00);
113
114 /* Datasheet: The ES90x8Q2M/K2M contains a Jitter Eliminator block, *
115 * which employs the use of a digital phase locked loop (DPLL) to *
116 * lock to the incoming audio clock rate. When in I2S or SPDIF mode, *
117 * the DPLL will lock to the frame clock (1 x fs). However, when in *
118 * DSD mode, the DPLL has no frame clock information, and must in- *
119 * stead lock to the bit clock rate (BCK). For this reason, there are *
120 * two bandwidth settings for the DPLL. *
121 Reg #12 [7:4] (0x05 default) bandwidth for I2S / SPDIF mode.
122 Reg #12 [3:0] (0x0A default) bandwidth for DSD mode.
123 * The DPLL bandwidth sets how quickly the DPLL can adjust its intern *
124 * representation of the audio clock. The higher the jitter or *
125 * frequency drift on the audio clock, the higher the bandwidth must *
126 * be so that the DPLL can react. *
127 * ! If the bandwidth is “too low”, the DPLL will loose lock and you *
128 * ! will hear random dropouts. (Fixed my SurfansF20 v3.2 dropouts) */
129 es9018k2m_write_reg(ES9018K2M_REG12_DPLL_SETTINGS, 0xda);
130
107 } else { /* Default to SWVOL for PCM5102A DAC */ 131 } else { /* Default to SWVOL for PCM5102A DAC */
108 logf("Default to SWVOL: ret=%d", ret); 132 logf("Default to SWVOL: ret=%d", ret);
109 } 133 }