diff options
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/crt0.S')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/crt0.S | 33 |
1 files changed, 0 insertions, 33 deletions
diff --git a/firmware/target/mips/ingenic_x1000/crt0.S b/firmware/target/mips/ingenic_x1000/crt0.S index b717f96692..b36500b462 100644 --- a/firmware/target/mips/ingenic_x1000/crt0.S +++ b/firmware/target/mips/ingenic_x1000/crt0.S | |||
@@ -34,33 +34,6 @@ | |||
34 | .section .init.text | 34 | .section .init.text |
35 | 35 | ||
36 | _start: | 36 | _start: |
37 | /* Clear data watchpoint */ | ||
38 | mtc0 zero, C0_WATCHLO | ||
39 | mtc0 zero, C0_WATCHHI | ||
40 | |||
41 | /* Set BEV, ERL, mask interrupts */ | ||
42 | li v0, 0x40fc04 | ||
43 | mtc0 v0, C0_Status | ||
44 | |||
45 | /* Set Cause_IV to 1 (use special interrupt vector) */ | ||
46 | li v0, M_CauseIV | ||
47 | mtc0 v0, C0_Cause | ||
48 | |||
49 | /* Set CPU_MODE and BUS_MODE to 1 in CPM_OPCR (Ingenic does this) */ | ||
50 | lui v0, 0xb000 | ||
51 | lw v1, 0x24(v0) | ||
52 | ori v1, v1, 0x22 | ||
53 | sw v1, 0x24(v0) | ||
54 | |||
55 | /* Enable kseg0 cacheability */ | ||
56 | li v0, 3 | ||
57 | mtc0 v0, C0_Config | ||
58 | nop | ||
59 | |||
60 | /* According to ingenic: "enable idx-store-data cache insn" */ | ||
61 | li v0, 0x20000000 | ||
62 | mtc0 v0, C0_ErrCtl | ||
63 | |||
64 | /* Cache init */ | 37 | /* Cache init */ |
65 | li v0, 0x80000000 | 38 | li v0, 0x80000000 |
66 | ori v1, v0, 0x4000 | 39 | ori v1, v0, 0x4000 |
@@ -80,7 +53,6 @@ _cache_loop: | |||
80 | mtc0 v0, C0_Config, 7 | 53 | mtc0 v0, C0_Config, 7 |
81 | nop | 54 | nop |
82 | 55 | ||
83 | #ifndef BOOTLOADER_SPL | ||
84 | /* Copy IRAM from BSS to low memory. */ | 56 | /* Copy IRAM from BSS to low memory. */ |
85 | la t0, _iramcopy | 57 | la t0, _iramcopy |
86 | la t1, _iramstart | 58 | la t1, _iramstart |
@@ -91,7 +63,6 @@ _iram_loop: | |||
91 | addiu t0, 4 | 63 | addiu t0, 4 |
92 | bne t1, t2, _iram_loop | 64 | bne t1, t2, _iram_loop |
93 | sw t3, -4(t1) | 65 | sw t3, -4(t1) |
94 | #endif | ||
95 | 66 | ||
96 | /* Clear the BSS segment (needed to zero-initialize C static values) */ | 67 | /* Clear the BSS segment (needed to zero-initialize C static values) */ |
97 | la t0, _bssbegin | 68 | la t0, _bssbegin |
@@ -103,7 +74,6 @@ _bss_loop: | |||
103 | sw zero, -4(t0) | 74 | sw zero, -4(t0) |
104 | _bss_done: | 75 | _bss_done: |
105 | 76 | ||
106 | #ifndef BOOTLOADER_SPL | ||
107 | /* Set stack pointer and clear the stack */ | 77 | /* Set stack pointer and clear the stack */ |
108 | la sp, stackend | 78 | la sp, stackend |
109 | la t0, stackbegin | 79 | la t0, stackbegin |
@@ -120,13 +90,11 @@ _irqstack_loop: | |||
120 | addiu t0, 4 | 90 | addiu t0, 4 |
121 | bne t0, k0, _irqstack_loop | 91 | bne t0, k0, _irqstack_loop |
122 | sw t1, -4(t0) | 92 | sw t1, -4(t0) |
123 | #endif | ||
124 | 93 | ||
125 | /* Jump to C code */ | 94 | /* Jump to C code */ |
126 | j main | 95 | j main |
127 | nop | 96 | nop |
128 | 97 | ||
129 | #ifndef BOOTLOADER_SPL | ||
130 | /* Exception entry points */ | 98 | /* Exception entry points */ |
131 | .section .vectors.1, "ax", %progbits | 99 | .section .vectors.1, "ax", %progbits |
132 | j tlb_refill_handler | 100 | j tlb_refill_handler |
@@ -260,6 +228,5 @@ _exception_return: | |||
260 | lw sp, 0x80(sp) | 228 | lw sp, 0x80(sp) |
261 | eret | 229 | eret |
262 | nop | 230 | nop |
263 | #endif | ||
264 | 231 | ||
265 | .set pop | 232 | .set pop |