summaryrefslogtreecommitdiff
path: root/firmware/target/mips/ingenic_x1000/aic-x1000.h
diff options
context:
space:
mode:
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/aic-x1000.h')
-rw-r--r--firmware/target/mips/ingenic_x1000/aic-x1000.h46
1 files changed, 46 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/aic-x1000.h b/firmware/target/mips/ingenic_x1000/aic-x1000.h
new file mode 100644
index 0000000000..eda0f80f04
--- /dev/null
+++ b/firmware/target/mips/ingenic_x1000/aic-x1000.h
@@ -0,0 +1,46 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2021 Aidan MacDonald
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21
22#ifndef __AIC_X1000_H__
23#define __AIC_X1000_H__
24
25#include "clk-x1000.h"
26#include <stdbool.h>
27
28/* Set frequency of I2S master clock supplied by AIC. Has no use if an
29 * external DAC is supplying the master clock. Must be called with the
30 * bit clock disabled.
31 *
32 * - clksrc can be one of EXCLK, SCLK_A, MPLL.
33 * - This function does not modify PLL settings. It's the caller's job
34 * to ensure the PLL is configured and runing.
35 * - fs is the audio sampling frequency (8 KHz - 192 KHz)
36 * - mult is multiplied by fs to get the master clock rate.
37 * - mult must be a multiple of 64 due to AIC bit clock requirements.
38 * - Note: EXCLK bypasses the decimal divider so it is not very flexible.
39 * If using EXCLK you must set mult=0. If EXCLK is not a multiple of
40 * the bit clock (= 64*fs), then the clock rate will be inaccurate.
41 *
42 * Returns zero on success and nonzero if the frequency is not achievable.
43 */
44extern int aic_i2s_set_mclk(x1000_clk_t clksrc, unsigned fs, unsigned mult);
45
46#endif /* __AIC_X1000_H__ */