diff options
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/system-jz4740.c')
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/system-jz4740.c | 72 |
1 files changed, 19 insertions, 53 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c index 61be6c60de..1a41723ffc 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c | |||
@@ -324,7 +324,7 @@ static int get_irq_number(void) | |||
324 | 324 | ||
325 | void intr_handler(void) | 325 | void intr_handler(void) |
326 | { | 326 | { |
327 | irq = get_irq_number(); | 327 | int irq = get_irq_number(); |
328 | if(irq < 0) | 328 | if(irq < 0) |
329 | return; | 329 | return; |
330 | 330 | ||
@@ -361,7 +361,7 @@ static char* parse_exception(unsigned int cause) | |||
361 | } | 361 | } |
362 | 362 | ||
363 | void exception_handler(void* stack_ptr, unsigned int cause, unsigned int epc) | 363 | void exception_handler(void* stack_ptr, unsigned int cause, unsigned int epc) |
364 | { | 364 | { |
365 | panicf("Exception occurred: %s [0x%08x] at 0x%08x (stack at 0x%08x)", parse_exception(cause), cause, epc, (unsigned int)stack_ptr); | 365 | panicf("Exception occurred: %s [0x%08x] at 0x%08x (stack at 0x%08x)", parse_exception(cause), cause, epc, (unsigned int)stack_ptr); |
366 | } | 366 | } |
367 | 367 | ||
@@ -457,23 +457,6 @@ void __icache_invalidate_all(void) | |||
457 | { | 457 | { |
458 | unsigned int i; | 458 | unsigned int i; |
459 | 459 | ||
460 | /* | ||
461 | do | ||
462 | { | ||
463 | unsigned long __k0_addr; | ||
464 | |||
465 | __asm__ __volatile__( | ||
466 | "la %0, 1f \n" | ||
467 | "or %0, %0, %1 \n" | ||
468 | "jr %0 \n" | ||
469 | "nop \n" | ||
470 | "1: nop \n" | ||
471 | : "=&r"(__k0_addr) | ||
472 | : "r" (0x20000000) | ||
473 | ); | ||
474 | } while(0); | ||
475 | */ | ||
476 | |||
477 | asm volatile (".set noreorder \n" | 460 | asm volatile (".set noreorder \n" |
478 | ".set mips32 \n" | 461 | ".set mips32 \n" |
479 | "mtc0 $0, $28 \n" /* TagLo */ | 462 | "mtc0 $0, $28 \n" /* TagLo */ |
@@ -484,34 +467,16 @@ void __icache_invalidate_all(void) | |||
484 | for(i=KSEG0; i<KSEG0+CACHE_SIZE; i+=CACHE_LINE_SIZE) | 467 | for(i=KSEG0; i<KSEG0+CACHE_SIZE; i+=CACHE_LINE_SIZE) |
485 | __CACHE_OP(Index_Store_Tag_I, i); | 468 | __CACHE_OP(Index_Store_Tag_I, i); |
486 | 469 | ||
487 | /* | 470 | /* invalidate btb */ |
488 | do | 471 | asm volatile ( |
489 | { | 472 | ".set mips32 \n" |
490 | unsigned long __k0_addr; | 473 | "mfc0 %0, $16, 7 \n" |
491 | __asm__ __volatile__( | 474 | "nop \n" |
492 | "nop;nop;nop;nop;nop;nop;nop \n" | 475 | "ori %0, 2 \n" |
493 | "la %0, 1f \n" | 476 | "mtc0 %0, $16, 7 \n" |
494 | "jr %0 \n" | 477 | ".set mips0 \n" |
495 | "nop \n" | 478 | : |
496 | "1: nop \n" | 479 | : "r" (i)); |
497 | : "=&r" (__k0_addr) | ||
498 | ); | ||
499 | } while(0); | ||
500 | */ | ||
501 | |||
502 | do | ||
503 | { | ||
504 | unsigned long tmp; | ||
505 | __asm__ __volatile__( | ||
506 | ".set mips32 \n" | ||
507 | "mfc0 %0, $16, 7 \n" /* Config */ | ||
508 | "nop \n" | ||
509 | "ori %0, 2 \n" | ||
510 | "mtc0 %0, $16, 7 \n" /* Config */ | ||
511 | "nop \n" | ||
512 | ".set mips0 \n" | ||
513 | : "=&r" (tmp)); | ||
514 | } while(0); | ||
515 | } | 480 | } |
516 | 481 | ||
517 | void __dcache_invalidate_all(void) | 482 | void __dcache_invalidate_all(void) |
@@ -657,13 +622,14 @@ static void tlb_init(void) | |||
657 | 622 | ||
658 | void tlb_refill_handler(void) | 623 | void tlb_refill_handler(void) |
659 | { | 624 | { |
660 | panicf("TLB refill handler! [0x%x] [0x%lx]", read_c0_badvaddr(), read_c0_epc()); | 625 | panicf("TLB refill handler at 0x%08lx! [0x%x]", read_c0_epc(), read_c0_badvaddr()); |
661 | } | 626 | } |
662 | 627 | ||
663 | static void tlb_call_refill(void) | 628 | static void tlb_call_refill(void) |
664 | { | 629 | { |
665 | asm("la $8, tlb_refill_handler \n" | 630 | asm("la $8, tlb_refill_handler \n" |
666 | "jr $8 \n"); | 631 | "jr $8 \n" |
632 | ); | ||
667 | } | 633 | } |
668 | 634 | ||
669 | extern int main(void); | 635 | extern int main(void); |
@@ -687,18 +653,18 @@ void system_main(void) | |||
687 | __dcache_writeback_all(); | 653 | __dcache_writeback_all(); |
688 | __icache_invalidate_all(); | 654 | __icache_invalidate_all(); |
689 | 655 | ||
690 | write_c0_status(1 << 28 | 1 << 10 | 1 << 3); /* Enable CP | Mask interrupt 2 | Supervisor mode */ | 656 | write_c0_status(1 << 28 | 1 << 10 ); /* Enable CP | Mask interrupt 2 */ |
691 | 657 | ||
692 | /* Disable all interrupts */ | 658 | /* Disable all interrupts */ |
693 | for(i=0; i<IRQ_MAX; i++) | 659 | for(i=0; i<IRQ_MAX; i++) |
694 | dis_irq(i); | 660 | dis_irq(i); |
695 | 661 | ||
696 | //tlb_init(); | 662 | tlb_init(); |
697 | |||
698 | sti(); | ||
699 | 663 | ||
700 | detect_clock(); | 664 | detect_clock(); |
701 | 665 | ||
666 | sti(); | ||
667 | |||
702 | main(); | 668 | main(); |
703 | 669 | ||
704 | while(1); | 670 | while(1); |