diff options
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c')
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c | 34 |
1 files changed, 9 insertions, 25 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c index 881c83066e..8da1313cf8 100644 --- a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c | |||
@@ -689,12 +689,18 @@ void DMA_CALLBACK(DMA_SD_TX_CHANNEL1)(void) | |||
689 | #endif /* SD_DMA_INTERRUPT */ | 689 | #endif /* SD_DMA_INTERRUPT */ |
690 | #endif /* SD_DMA_ENABLE */ | 690 | #endif /* SD_DMA_ENABLE */ |
691 | 691 | ||
692 | #ifndef HAVE_ADJUSTABLE_CPU_FREQ | ||
693 | #define cpu_frequency __cpm_get_pllout2() | ||
694 | #endif | ||
695 | |||
692 | static inline unsigned int jz_sd_calc_clkrt(const int drive, unsigned int rate) | 696 | static inline unsigned int jz_sd_calc_clkrt(const int drive, unsigned int rate) |
693 | { | 697 | { |
694 | unsigned int clkrt; | 698 | unsigned int clkrt = 0; |
695 | unsigned int clk_src = sd2_0[drive] ? SD_CLOCK_HIGH : SD_CLOCK_FAST; | 699 | unsigned int clk_src = cpu_frequency / __cpm_get_mscdiv(); /* MSC_CLK */ |
700 | |||
701 | if (!sd2_0[drive] && rate > SD_CLOCK_FAST) | ||
702 | rate = SD_CLOCK_FAST; | ||
696 | 703 | ||
697 | clkrt = 0; | ||
698 | while (rate < clk_src) | 704 | while (rate < clk_src) |
699 | { | 705 | { |
700 | clkrt++; | 706 | clkrt++; |
@@ -703,33 +709,11 @@ static inline unsigned int jz_sd_calc_clkrt(const int drive, unsigned int rate) | |||
703 | return clkrt; | 709 | return clkrt; |
704 | } | 710 | } |
705 | 711 | ||
706 | #ifndef HAVE_ADJUSTABLE_CPU_FREQ | ||
707 | #define cpu_frequency __cpm_get_pllout2() | ||
708 | #endif | ||
709 | |||
710 | void cpm_select_msc_clk(void) | ||
711 | { | ||
712 | unsigned int div = cpu_frequency / SD_CLOCK_FAST; | ||
713 | |||
714 | if (div == 0) | ||
715 | div = 1; | ||
716 | |||
717 | if (div == __cpm_get_mscdiv()) | ||
718 | return; | ||
719 | |||
720 | REG_CPM_MSCCDR = MSCCDR_MCS | (div - 1); | ||
721 | DEBUG("MSCCLK == %x\n", REG_CPM_MSCCDR); | ||
722 | __cpm_enable_pll_change(); | ||
723 | } | ||
724 | |||
725 | /* Set the MMC clock frequency */ | 712 | /* Set the MMC clock frequency */ |
726 | static void jz_sd_set_clock(const int drive, unsigned int rate) | 713 | static void jz_sd_set_clock(const int drive, unsigned int rate) |
727 | { | 714 | { |
728 | int clkrt; | 715 | int clkrt; |
729 | 716 | ||
730 | /* select clock source from CPM */ | ||
731 | cpm_select_msc_clk(); | ||
732 | |||
733 | clkrt = jz_sd_calc_clkrt(drive, rate); | 717 | clkrt = jz_sd_calc_clkrt(drive, rate); |
734 | REG_MSC_CLKRT(MSC_CHN(drive)) = clkrt; | 718 | REG_MSC_CLKRT(MSC_CHN(drive)) = clkrt; |
735 | 719 | ||