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Diffstat (limited to 'firmware/target/hosted/samsungypr/ypr1/ioctl-ypr1.h')
-rw-r--r--firmware/target/hosted/samsungypr/ypr1/ioctl-ypr1.h180
1 files changed, 0 insertions, 180 deletions
diff --git a/firmware/target/hosted/samsungypr/ypr1/ioctl-ypr1.h b/firmware/target/hosted/samsungypr/ypr1/ioctl-ypr1.h
index 4ac7a1c4b5..95b882f0d1 100644
--- a/firmware/target/hosted/samsungypr/ypr1/ioctl-ypr1.h
+++ b/firmware/target/hosted/samsungypr/ypr1/ioctl-ypr1.h
@@ -47,184 +47,4 @@ void max17040_init(void);
47void max17040_close(void); 47void max17040_close(void);
48int max17040_ioctl(int request, int *data); 48int max17040_ioctl(int request, int *data);
49 49
50/**
51 * This is the wrapper to r1Gpio.ko module with the possible
52 * ioctl calls
53 * TODO move this into a more generic file for ypr platform
54 */
55
56struct gpio_info {
57 int num;
58 int mode;
59 int val;
60} __attribute__((packed));
61
62/* Strangely for whatever reason magic differs from R0 (A vs. G) */
63#define IOCTL_GPIO_MAGIC 'A'
64
65#define E_IOCTL_GPIO_SET_MUX 0
66#define E_IOCTL_GPIO_UNSET_MUX 1
67#define E_IOCTL_GPIO_SET_TYPE 2
68#define E_IOCTL_GPIO_SET_OUTPUT 3
69#define E_IOCTL_GPIO_SET_INPUT 4
70#define E_IOCTL_GPIO_SET_HIGH 5
71#define E_IOCTL_GPIO_SET_LOW 6
72#define E_IOCTL_GPIO_GET_VAL 7
73#define E_IOCTL_GPIO_IS_HIGH 8
74#define E_IOCTL_GPIO_MAX_NR 9
75
76#define DEV_CTRL_GPIO_SET_MUX _IOW(IOCTL_GPIO_MAGIC, 0, struct gpio_info)
77#define DEV_CTRL_GPIO_UNSET_MUX _IOW(IOCTL_GPIO_MAGIC, 1, struct gpio_info)
78#define DEV_CTRL_GPIO_SET_TYPE _IOW(IOCTL_GPIO_MAGIC, 2, struct gpio_info)
79#define DEV_CTRL_GPIO_SET_OUTPUT _IOW(IOCTL_GPIO_MAGIC, 3, struct gpio_info)
80#define DEV_CTRL_GPIO_SET_INPUT _IOW(IOCTL_GPIO_MAGIC, 4, struct gpio_info)
81#define DEV_CTRL_GPIO_SET_HIGH _IOW(IOCTL_GPIO_MAGIC, 5, struct gpio_info)
82#define DEV_CTRL_GPIO_SET_LOW _IOW(IOCTL_GPIO_MAGIC, 6, struct gpio_info)
83#define DEV_CTRL_GPIO_GET_VAL _IOW(IOCTL_GPIO_MAGIC, 7, struct gpio_info)
84#define DEV_CTRL_GPIO_IS_HIGH _IOW(IOCTL_GPIO_MAGIC, 8, struct gpio_info)
85
86
87typedef enum
88{
89 GPIO1_0 = 0, /* GPIO group 1 start */
90 GPIO1_1,
91 GPIO1_2,
92 GPIO1_3,
93 GPIO1_4,
94 GPIO1_5,
95 GPIO1_6,
96 GPIO1_7,
97 GPIO1_8,
98 GPIO1_9,
99 GPIO1_10,
100 GPIO1_11,
101 GPIO1_12,
102 GPIO1_13,
103 GPIO1_14,
104 GPIO1_15,
105 GPIO1_16,
106 GPIO1_17,
107 GPIO1_18,
108 GPIO1_19,
109 GPIO1_20,
110 GPIO1_21,
111 GPIO1_22,
112 GPIO1_23,
113 GPIO1_24,
114 GPIO1_25,
115 GPIO1_26,
116 GPIO1_27,
117 GPIO1_28,
118 GPIO1_29,
119 GPIO1_30,
120 GPIO1_31,
121 GPIO2_0, /* GPIO group 2 start */
122 GPIO2_1,
123 GPIO2_2,
124 GPIO2_3,
125 GPIO2_4,
126 GPIO2_5,
127 GPIO2_6,
128 GPIO2_7,
129 GPIO2_8,
130 GPIO2_9,
131 GPIO2_10,
132 GPIO2_11,
133 GPIO2_12,
134 GPIO2_13,
135 GPIO2_14,
136 GPIO2_15,
137 GPIO2_16,
138 GPIO2_17,
139 GPIO2_18,
140 GPIO2_19,
141 GPIO2_20,
142 GPIO2_21,
143 GPIO2_22,
144 GPIO2_23,
145 GPIO2_24,
146 GPIO2_25,
147 GPIO2_26,
148 GPIO2_27,
149 GPIO2_28,
150 GPIO2_29,
151 GPIO2_30,
152 GPIO2_31,
153 GPIO3_0, /* GPIO group 3 start */
154 GPIO3_1,
155 GPIO3_2,
156 GPIO3_3,
157 GPIO3_4,
158 GPIO3_5,
159 GPIO3_6,
160 GPIO3_7,
161 GPIO3_8,
162 GPIO3_9,
163 GPIO3_10,
164 GPIO3_11,
165 GPIO3_12,
166 GPIO3_13,
167 GPIO3_14,
168 GPIO3_15,
169 GPIO3_16,
170 GPIO3_17,
171 GPIO3_18,
172 GPIO3_19,
173 GPIO3_20,
174 GPIO3_21,
175 GPIO3_22,
176 GPIO3_23,
177 GPIO3_24,
178 GPIO3_25,
179 GPIO3_26,
180 GPIO3_27,
181 GPIO3_28,
182 GPIO3_29,
183 GPIO3_30,
184 GPIO3_31,
185}R0_MX37_GPIO;
186
187typedef enum
188{
189 CONFIG_ALT0,
190 CONFIG_ALT1,
191 CONFIG_ALT2,
192 CONFIG_ALT3,
193 CONFIG_ALT4,
194 CONFIG_ALT5,
195 CONFIG_ALT6,
196 CONFIG_ALT7,
197 CONFIG_GPIO,
198 CONFIG_SION = 0x01 << 4,
199 CONFIG_DEFAULT
200} R0_MX37_PIN_CONFIG;
201
202#ifndef __MACH_MX37_IOMUX_H__
203typedef enum
204{
205 PAD_CTL_SRE_SLOW = 0x0 << 0,
206 PAD_CTL_SRE_FAST = 0x1 << 0,
207 PAD_CTL_DRV_LOW = 0x0 << 1,
208 PAD_CTL_DRV_MEDIUM = 0x1 << 1,
209 PAD_CTL_DRV_HIGH = 0x2 << 1,
210 PAD_CTL_DRV_MAX = 0x3 << 1,
211 PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3,
212 PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,
213 PAD_CTL_100K_PD = 0x0 << 4,
214 PAD_CTL_47K_PU = 0x1 << 4,
215 PAD_CTL_100K_PU = 0x2 << 4,
216 PAD_CTL_22K_PU = 0x3 << 4,
217 PAD_CTL_PUE_KEEPER = 0x0 << 6,
218 PAD_CTL_PUE_PULL = 0x1 << 6,
219 PAD_CTL_PKE_NONE = 0x0 << 7,
220 PAD_CTL_PKE_ENABLE = 0x1 << 7,
221 PAD_CTL_HYS_NONE = 0x0 << 8,
222 PAD_CTL_HYS_ENABLE = 0x1 << 8,
223 PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,
224 PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,
225 PAD_CTL_DRV_VOT_LOW = 0x0 << 13,
226 PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,
227} R0_MX37_PAD_CONFIG;
228#endif
229
230#endif /* __DEV_IOCTL_YPR0_H__ */ 50#endif /* __DEV_IOCTL_YPR0_H__ */