diff options
Diffstat (limited to 'firmware/target/coldfire')
-rw-r--r-- | firmware/target/coldfire/crt0.S | 4 | ||||
-rw-r--r-- | firmware/target/coldfire/iriver/system-iriver.c | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/firmware/target/coldfire/crt0.S b/firmware/target/coldfire/crt0.S index 7734970ff0..e6717710b1 100644 --- a/firmware/target/coldfire/crt0.S +++ b/firmware/target/coldfire/crt0.S | |||
@@ -138,7 +138,7 @@ start: | |||
138 | 138 | ||
139 | /* Set up the DRAM controller. The refresh is based on the 11.2896MHz | 139 | /* Set up the DRAM controller. The refresh is based on the 11.2896MHz |
140 | clock (5.6448MHz bus frequency). We haven't yet started the PLL */ | 140 | clock (5.6448MHz bus frequency). We haven't yet started the PLL */ |
141 | #if MEM < 32 | 141 | #if MEMORYSIZE < 32 |
142 | move.w #0x8004,%d0 /* DCR - Synchronous, 80 cycle refresh */ | 142 | move.w #0x8004,%d0 /* DCR - Synchronous, 80 cycle refresh */ |
143 | #else | 143 | #else |
144 | move.w #0x8001,%d0 /* DCR - Synchronous, 32 cycle refresh */ | 144 | move.w #0x8001,%d0 /* DCR - Synchronous, 32 cycle refresh */ |
@@ -153,7 +153,7 @@ start: | |||
153 | In our case this means that we set the base address 16M ahead and | 153 | In our case this means that we set the base address 16M ahead and |
154 | use a 64M mask. | 154 | use a 64M mask. |
155 | */ | 155 | */ |
156 | #if MEM < 32 | 156 | #if MEMORYSIZE < 32 |
157 | move.l #0x31002324,%d0 /* DACR0 - Base 0x31000000, Banks on 21 and up, | 157 | move.l #0x31002324,%d0 /* DACR0 - Base 0x31000000, Banks on 21 and up, |
158 | CAS latency 2, Page mode, No refresh yet */ | 158 | CAS latency 2, Page mode, No refresh yet */ |
159 | move.l %d0,(0x108,%a0) | 159 | move.l %d0,(0x108,%a0) |
diff --git a/firmware/target/coldfire/iriver/system-iriver.c b/firmware/target/coldfire/iriver/system-iriver.c index 1916eec0cd..1ceb89bd16 100644 --- a/firmware/target/coldfire/iriver/system-iriver.c +++ b/firmware/target/coldfire/iriver/system-iriver.c | |||
@@ -49,7 +49,7 @@ | |||
49 | * 124185600 11 0x018ae025 59 29 0x1180 0x1580 0x2180 3 1 1 | 49 | * 124185600 11 0x018ae025 59 29 0x1180 0x1580 0x2180 3 1 1 |
50 | */ | 50 | */ |
51 | 51 | ||
52 | #if MEM < 32 | 52 | #if MEMORYSIZE < 32 |
53 | #define MAX_REFRESH_TIMER 59 | 53 | #define MAX_REFRESH_TIMER 59 |
54 | #define NORMAL_REFRESH_TIMER 21 | 54 | #define NORMAL_REFRESH_TIMER 21 |
55 | #define DEFAULT_REFRESH_TIMER 4 | 55 | #define DEFAULT_REFRESH_TIMER 4 |