diff options
Diffstat (limited to 'firmware/target/coldfire/iaudio/system-iaudio.c')
-rw-r--r-- | firmware/target/coldfire/iaudio/system-iaudio.c | 35 |
1 files changed, 30 insertions, 5 deletions
diff --git a/firmware/target/coldfire/iaudio/system-iaudio.c b/firmware/target/coldfire/iaudio/system-iaudio.c index 30a4f6e71b..565f75aa6d 100644 --- a/firmware/target/coldfire/iaudio/system-iaudio.c +++ b/firmware/target/coldfire/iaudio/system-iaudio.c | |||
@@ -24,6 +24,28 @@ | |||
24 | #include "timer.h" | 24 | #include "timer.h" |
25 | #include "pcf50606.h" | 25 | #include "pcf50606.h" |
26 | 26 | ||
27 | /* Settings for all possible clock frequencies (with properly working timers) | ||
28 | * | ||
29 | * xxx_REFRESH_TIMER below | ||
30 | * system.h, CPUFREQ_xxx_MULT | | ||
31 | * | | | ||
32 | * V V | ||
33 | * PLLCR & Rftim. IDECONFIG1/IDECONFIG2 | ||
34 | * CPUCLK/Hz MULT ~0x70c00000 16MB CSCR0 CSCR1 CS2Pre CS2Post CS2Wait | ||
35 | * ------------------------------------------------------------------------- | ||
36 | * 11289600 1 0x00000200 4 0x0180 0x0180 1 1 0 | ||
37 | * 22579200 2 0x05028049 10 0x0180 0x0180 1 1 0 | ||
38 | * 33868800 3 0x03024049 15 0x0180 0x0180 1 1 0 | ||
39 | * 45158400 4 0x05028045 21 0x0180 0x0180 1 1 0 | ||
40 | * 56448000 5 0x02028049 26 0x0580 0x0580 2 1 0 | ||
41 | * 67737600 6 0x03024045 32 0x0580 0x0980 2 1 0 | ||
42 | * 79027200 7 0x0302a045 37 0x0580 0x0d80 2 1 0 | ||
43 | * 90316800 8 0x03030045 43 0x0980 0x0d80 2 1 0 | ||
44 | * 101606400 9 0x01024049 48 0x0980 0x1180 2 1 0 | ||
45 | * 112896000 10 0x01028049 54 0x0980 0x1580 3 1 0 | ||
46 | * 124185600 11 0x0102c049 59 0x0980 0x1180 3 1 1 | ||
47 | */ | ||
48 | |||
27 | #define MAX_REFRESH_TIMER 59 | 49 | #define MAX_REFRESH_TIMER 59 |
28 | #define NORMAL_REFRESH_TIMER 21 | 50 | #define NORMAL_REFRESH_TIMER 21 |
29 | #define DEFAULT_REFRESH_TIMER 4 | 51 | #define DEFAULT_REFRESH_TIMER 4 |
@@ -42,7 +64,7 @@ void set_cpu_frequency(long frequency) | |||
42 | PLLCR &= ~1; /* Bypass mode */ | 64 | PLLCR &= ~1; /* Bypass mode */ |
43 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); | 65 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); |
44 | RECALC_DELAYS(CPUFREQ_MAX); | 66 | RECALC_DELAYS(CPUFREQ_MAX); |
45 | PLLCR = 0x03042045 | (PLLCR & 0x70C00000); | 67 | PLLCR = 0x0102c049 | (PLLCR & 0x70C00000); |
46 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ | 68 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ |
47 | CSCR1 = 0x00000980; /* LCD: 2 wait states */ | 69 | CSCR1 = 0x00000980; /* LCD: 2 wait states */ |
48 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | 70 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
@@ -50,7 +72,8 @@ void set_cpu_frequency(long frequency) | |||
50 | timers_adjust_prescale(CPUFREQ_MAX_MULT, true); | 72 | timers_adjust_prescale(CPUFREQ_MAX_MULT, true); |
51 | DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */ | 73 | DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */ |
52 | cpu_frequency = CPUFREQ_MAX; | 74 | cpu_frequency = CPUFREQ_MAX; |
53 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ | 75 | IDECONFIG1 = 0x100000 | (1 << 13) | (3 << 10); |
76 | /* BUFEN2 enable | CS2Post | CS2Pre */ | ||
54 | IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */ | 77 | IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */ |
55 | break; | 78 | break; |
56 | 79 | ||
@@ -60,7 +83,7 @@ void set_cpu_frequency(long frequency) | |||
60 | PLLCR &= ~1; /* Bypass mode */ | 83 | PLLCR &= ~1; /* Bypass mode */ |
61 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); | 84 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); |
62 | RECALC_DELAYS(CPUFREQ_NORMAL); | 85 | RECALC_DELAYS(CPUFREQ_NORMAL); |
63 | PLLCR = 0x06030045 | (PLLCR & 0x70C00000); | 86 | PLLCR = 0x05028045 | (PLLCR & 0x70C00000); |
64 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ | 87 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ |
65 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | 88 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ |
66 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | 89 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
@@ -68,7 +91,8 @@ void set_cpu_frequency(long frequency) | |||
68 | timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true); | 91 | timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true); |
69 | DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */ | 92 | DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */ |
70 | cpu_frequency = CPUFREQ_NORMAL; | 93 | cpu_frequency = CPUFREQ_NORMAL; |
71 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ | 94 | IDECONFIG1 = 0x100000 | (1 << 13) | (1 << 10); |
95 | /* BUFEN2 enable | CS2Post | CS2Pre */ | ||
72 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ | 96 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ |
73 | break; | 97 | break; |
74 | default: | 98 | default: |
@@ -83,7 +107,8 @@ void set_cpu_frequency(long frequency) | |||
83 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | 107 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ |
84 | DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ | 108 | DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ |
85 | cpu_frequency = CPUFREQ_DEFAULT; | 109 | cpu_frequency = CPUFREQ_DEFAULT; |
86 | IDECONFIG1 = 0x106000 | (1 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ | 110 | IDECONFIG1 = 0x100000 | (1 << 13) | (1 << 10); |
111 | /* BUFEN2 enable | CS2Post | CS2Pre */ | ||
87 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ | 112 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ |
88 | break; | 113 | break; |
89 | } | 114 | } |