diff options
Diffstat (limited to 'firmware/target/coldfire/iaudio/m3/lcd-as-m3.S')
-rw-r--r-- | firmware/target/coldfire/iaudio/m3/lcd-as-m3.S | 85 |
1 files changed, 59 insertions, 26 deletions
diff --git a/firmware/target/coldfire/iaudio/m3/lcd-as-m3.S b/firmware/target/coldfire/iaudio/m3/lcd-as-m3.S index a135ce5eb6..74fcd692b7 100644 --- a/firmware/target/coldfire/iaudio/m3/lcd-as-m3.S +++ b/firmware/target/coldfire/iaudio/m3/lcd-as-m3.S | |||
@@ -58,15 +58,15 @@ | |||
58 | swap %d3 /* Shift data to upper byte */ | 58 | swap %d3 /* Shift data to upper byte */ |
59 | lsl.l #8, %d3 | 59 | lsl.l #8, %d3 |
60 | 60 | ||
61 | eor.l %d7, %d0 /* precalculate opposite state of clock line */ | 61 | move.l %d0, %d1 /* precalculate opposite state of clock line */ |
62 | eor.l %d7, %d1 | ||
62 | 63 | ||
63 | lsl.l #1,%d3 /* Shift out MSB */ | 64 | lsl.l #1, %d3 /* Shift out MSB */ |
64 | bcc.s 1f | 65 | bcc.s 1f |
65 | eor.l %d6, %d0 /* 1: Flip data bit */ | 66 | eor.l %d6, %d0 /* 1: Flip data bit */ |
67 | eor.l %d6, %d1 | ||
66 | 1: | 68 | 1: |
67 | move.l %d0, (%a0) /* Output new state and set CLK = 0*/ | 69 | move.l %d1, (%a0) /* Output new state and set CLK = 0*/ |
68 | move.l %d0, %d1 | ||
69 | eor.l %d7, %d1 | ||
70 | bra.w .wr_bit7 | 70 | bra.w .wr_bit7 |
71 | 71 | ||
72 | 72 | ||
@@ -98,62 +98,77 @@ | |||
98 | eor.l %d1, %d3 /* previous state, and 0's where it doesn't */ | 98 | eor.l %d1, %d3 /* previous state, and 0's where it doesn't */ |
99 | swap %d3 /* Shift data to upper word */ | 99 | swap %d3 /* Shift data to upper word */ |
100 | 100 | ||
101 | eor.l %d7, %d0 /* precalculate opposite state of clock line */ | 101 | move.l %d0, %d1 /* precalculate opposite state of clock line */ |
102 | eor.l %d7, %d1 | ||
102 | 103 | ||
103 | lsl.l #1,%d3 /* Shift out MSB */ | 104 | lsl.l #1, %d3 /* Shift out MSB */ |
104 | bcc.s 1f | 105 | bcc.s 1f |
105 | eor.l %d6, %d0 /* 1: Flip data bit */ | 106 | eor.l %d6, %d0 /* 1: Flip data bit */ |
107 | eor.l %d6, %d1 | ||
106 | 1: | 108 | 1: |
107 | move.l %d0, (%a0) /* Output new state and set CLK = 0*/ | 109 | move.l %d1, (%a0) /* Output new state and set CLK = 0*/ |
108 | move.l %d0, %d1 | ||
109 | eor.l %d7, %d1 | ||
110 | nop | ||
111 | 110 | ||
112 | .macro bit_out | 111 | .macro bit_out |
113 | lsl.l #1,%d3 | 112 | move.l %d0, (%a0) /* Set CLK = 1 */ |
113 | lsl.l #1, %d3 | ||
114 | bcc.s 1f | 114 | bcc.s 1f |
115 | eor.l %d6, %d0 | 115 | eor.l %d6, %d0 |
116 | eor.l %d6, %d1 | ||
116 | 1: | 117 | 1: |
117 | move.l %d1, (%a0) /* Set CLK = 1 (delayed) */ | 118 | move.l %d1, (%a0) |
118 | move.l %d0, (%a0) | ||
119 | move.l %d0, %d1 | ||
120 | eor.l %d7, %d1 | ||
121 | .endm | 119 | .endm |
122 | bit_out | 120 | |
121 | nop | ||
123 | nop | 122 | nop |
124 | bit_out | 123 | bit_out |
125 | nop | 124 | nop |
125 | nop | ||
126 | bit_out | 126 | bit_out |
127 | nop | 127 | nop |
128 | nop | ||
128 | bit_out | 129 | bit_out |
129 | nop | 130 | nop |
131 | nop | ||
130 | bit_out | 132 | bit_out |
131 | nop | 133 | nop |
134 | nop | ||
132 | bit_out | 135 | bit_out |
133 | nop | 136 | nop |
137 | nop | ||
134 | bit_out | 138 | bit_out |
135 | nop | 139 | nop |
140 | nop | ||
136 | bit_out | 141 | bit_out |
137 | nop | 142 | nop |
143 | nop | ||
144 | bit_out | ||
138 | 145 | ||
146 | nop | ||
139 | .wr_bit7: | 147 | .wr_bit7: |
148 | nop | ||
140 | bit_out | 149 | bit_out |
141 | nop | 150 | nop |
151 | nop | ||
142 | bit_out | 152 | bit_out |
143 | nop | 153 | nop |
154 | nop | ||
144 | bit_out | 155 | bit_out |
145 | nop | 156 | nop |
157 | nop | ||
146 | bit_out | 158 | bit_out |
147 | nop | 159 | nop |
160 | nop | ||
148 | bit_out | 161 | bit_out |
149 | nop | 162 | nop |
163 | nop | ||
150 | bit_out | 164 | bit_out |
151 | nop | 165 | nop |
166 | nop | ||
152 | bit_out | 167 | bit_out |
153 | nop | 168 | nop |
154 | |||
155 | nop | 169 | nop |
156 | move.l %d1, (%a0) /* Set CLK = 1 (delayed) */ | 170 | |
171 | move.l %d0, (%a0) /* Set CLK = 1 */ | ||
157 | move.w %d2, %sr | 172 | move.w %d2, %sr |
158 | rts | 173 | rts |
159 | 174 | ||
@@ -195,6 +210,7 @@ | |||
195 | move.l %d1, (%a0) /* Output new state and set CLK = 0*/ | 210 | move.l %d1, (%a0) /* Output new state and set CLK = 0*/ |
196 | move.l %d0, (%a0) /* set CLK = 1 */ | 211 | move.l %d0, (%a0) /* set CLK = 1 */ |
197 | .endm | 212 | .endm |
213 | |||
198 | bit_out_fast | 214 | bit_out_fast |
199 | bit_out_fast | 215 | bit_out_fast |
200 | bit_out_fast | 216 | bit_out_fast |
@@ -438,33 +454,41 @@ lcd_grey_data: | |||
438 | eor.l %d1, %d3 /* previous state, and 0's where it doesn't */ | 454 | eor.l %d1, %d3 /* previous state, and 0's where it doesn't */ |
439 | swap %d3 /* Shift data to upper word */ | 455 | swap %d3 /* Shift data to upper word */ |
440 | 456 | ||
441 | eor.l %d7, %d0 /* precalculate opposite state of clock line */ | 457 | move.l %d0, %d1 /* precalculate opposite state of clock line */ |
458 | eor.l %d7, %d1 | ||
442 | 459 | ||
443 | lsl.l #1,%d3 /* Shift out MSB */ | 460 | lsl.l #1, %d3 /* Shift out MSB */ |
444 | bcc.s 1f | 461 | bcc.s 1f |
445 | eor.l %d6, %d0 /* 1: Flip data bit */ | 462 | eor.l %d6, %d0 /* 1: Flip data bit */ |
463 | eor.l %d6, %d1 | ||
446 | 1: | 464 | 1: |
447 | move.l %d0, %d1 | 465 | move.l %d1, (%a0) /* Output new state and set CLK = 0*/ |
448 | move.l %d0, (%a0) /* Output new state and set CLK = 0*/ | ||
449 | eor.l %d7, %d1 | ||
450 | 466 | ||
451 | move.l (%a3), %d4 /* fetch 4 pixel phases */ | 467 | move.l (%a3), %d4 /* fetch 4 pixel phases */ |
452 | bit_out | 468 | bit_out |
453 | bclr.l #31, %d4 /* Z = !(p0 & 0x80); p0 &= ~0x80; */ | 469 | bclr.l #31, %d4 /* Z = !(p0 & 0x80); p0 &= ~0x80; */ |
454 | seq.b %d5 /* %d5 = ........................00000000 */ | 470 | seq.b %d5 /* %d5 = ........................00000000 */ |
455 | lsl.l #1, %d5 /* %d5 = .......................00000000. */ | 471 | lsl.l #1, %d5 /* %d5 = .......................00000000. */ |
472 | trapf | ||
473 | trapf | ||
456 | bit_out | 474 | bit_out |
457 | bclr.l #23, %d4 /* Z = !(p1 & 0x80); p1 &= ~0x80; */ | 475 | bclr.l #23, %d4 /* Z = !(p1 & 0x80); p1 &= ~0x80; */ |
458 | seq.b %d5 /* %d5 = .......................011111111 */ | 476 | seq.b %d5 /* %d5 = .......................011111111 */ |
459 | lsl.l #1, %d5 /* %d5 = ......................011111111. */ | 477 | lsl.l #1, %d5 /* %d5 = ......................011111111. */ |
478 | trapf | ||
479 | trapf | ||
460 | bit_out | 480 | bit_out |
461 | bclr.l #15, %d4 /* Z = !(p2 & 0x80); p2 &= ~0x80; */ | 481 | bclr.l #15, %d4 /* Z = !(p2 & 0x80); p2 &= ~0x80; */ |
462 | seq.b %d5 /* %d5 = ......................0122222222 */ | 482 | seq.b %d5 /* %d5 = ......................0122222222 */ |
463 | lsl.l #1, %d5 /* %d5 = .....................0122222222. */ | 483 | lsl.l #1, %d5 /* %d5 = .....................0122222222. */ |
484 | trapf | ||
485 | trapf | ||
464 | bit_out | 486 | bit_out |
465 | bclr.l #7, %d4 /* Z = !(p3 & 0x80); p3 &= ~0x80; */ | 487 | bclr.l #7, %d4 /* Z = !(p3 & 0x80); p3 &= ~0x80; */ |
466 | seq.b %d5 /* %d5 = .....................01233333333 */ | 488 | seq.b %d5 /* %d5 = .....................01233333333 */ |
467 | lsl.l #1, %d5 /* %d5 = ....................01233333333. */ | 489 | lsl.l #1, %d5 /* %d5 = ....................01233333333. */ |
490 | trapf | ||
491 | trapf | ||
468 | bit_out | 492 | bit_out |
469 | add.l (%a2)+, %d4 /* add 4 pixel values to the phases */ | 493 | add.l (%a2)+, %d4 /* add 4 pixel values to the phases */ |
470 | bit_out | 494 | bit_out |
@@ -476,18 +500,26 @@ lcd_grey_data: | |||
476 | bclr.l #31, %d4 /* Z = !(p0 & 0x80); p0 &= ~0x80; */ | 500 | bclr.l #31, %d4 /* Z = !(p0 & 0x80); p0 &= ~0x80; */ |
477 | seq.b %d5 /* %d5 = ....................012344444444 */ | 501 | seq.b %d5 /* %d5 = ....................012344444444 */ |
478 | lsl.l #1, %d5 /* %d5 = ...................012344444444. */ | 502 | lsl.l #1, %d5 /* %d5 = ...................012344444444. */ |
503 | trapf | ||
504 | trapf | ||
479 | bit_out | 505 | bit_out |
480 | bclr.l #23, %d4 /* Z = !(p1 & 0x80); p1 &= ~0x80; */ | 506 | bclr.l #23, %d4 /* Z = !(p1 & 0x80); p1 &= ~0x80; */ |
481 | seq.b %d5 /* %d5 = ...................0123455555555 */ | 507 | seq.b %d5 /* %d5 = ...................0123455555555 */ |
482 | lsl.l #1, %d5 /* %d5 = ..................0123455555555. */ | 508 | lsl.l #1, %d5 /* %d5 = ..................0123455555555. */ |
509 | trapf | ||
510 | trapf | ||
483 | bit_out | 511 | bit_out |
484 | bclr.l #15, %d4 /* Z = !(p2 & 0x80); p2 &= ~0x80; */ | 512 | bclr.l #15, %d4 /* Z = !(p2 & 0x80); p2 &= ~0x80; */ |
485 | seq.b %d5 /* %d5 = ..................01234566666666 */ | 513 | seq.b %d5 /* %d5 = ..................01234566666666 */ |
486 | lsl.l #1, %d5 /* %d5 = .................01234566666666. */ | 514 | lsl.l #1, %d5 /* %d5 = .................01234566666666. */ |
515 | trapf | ||
516 | trapf | ||
487 | bit_out | 517 | bit_out |
488 | bclr.l #7, %d4 /* Z = !(p3 & 0x80); p3 &= ~0x80; */ | 518 | bclr.l #7, %d4 /* Z = !(p3 & 0x80); p3 &= ~0x80; */ |
489 | seq.b %d5 /* %d5 = .................012345677777777 */ | 519 | seq.b %d5 /* %d5 = .................012345677777777 */ |
490 | lsr.l #7, %d5 /* %d5 = ........................01234567 */ | 520 | lsr.l #7, %d5 /* %d5 = ........................01234567 */ |
521 | trapf | ||
522 | trapf | ||
491 | bit_out | 523 | bit_out |
492 | add.l (%a2)+, %d4 /* add 4 pixel values to the phases */ | 524 | add.l (%a2)+, %d4 /* add 4 pixel values to the phases */ |
493 | bit_out | 525 | bit_out |
@@ -495,13 +527,14 @@ lcd_grey_data: | |||
495 | 527 | ||
496 | bit_out | 528 | bit_out |
497 | nop | 529 | nop |
530 | nop | ||
498 | bit_out | 531 | bit_out |
499 | move.l %d5, %d3 | 532 | move.l %d5, %d3 |
500 | lsl.l #8, %d3 | 533 | lsl.l #8, %d3 |
501 | or.l %d5, %d3 | 534 | or.l %d5, %d3 |
502 | |||
503 | nop | 535 | nop |
504 | move.l %d1, (%a0) /* Set CLK = 1 (delayed) */ | 536 | |
537 | move.l %d0, (%a0) /* Set CLK = 1 */ | ||
505 | move.w %d2, %sr | 538 | move.w %d2, %sr |
506 | 539 | ||
507 | cmp.l %a3, %a4 | 540 | cmp.l %a3, %a4 |