diff options
Diffstat (limited to 'firmware/target/coldfire/iaudio/m3/adc-m3.c')
-rw-r--r-- | firmware/target/coldfire/iaudio/m3/adc-m3.c | 91 |
1 files changed, 83 insertions, 8 deletions
diff --git a/firmware/target/coldfire/iaudio/m3/adc-m3.c b/firmware/target/coldfire/iaudio/m3/adc-m3.c index c4f8d92ae1..b0d7f7430b 100644 --- a/firmware/target/coldfire/iaudio/m3/adc-m3.c +++ b/firmware/target/coldfire/iaudio/m3/adc-m3.c | |||
@@ -18,15 +18,90 @@ | |||
18 | ****************************************************************************/ | 18 | ****************************************************************************/ |
19 | 19 | ||
20 | #include "config.h" | 20 | #include "config.h" |
21 | #include "cpu.h" | 21 | |
22 | #include "system.h" | ||
23 | #include "kernel.h" | ||
24 | #include "thread.h" | ||
25 | #include "adc.h" | 22 | #include "adc.h" |
23 | #include "i2c-coldfire.h" | ||
24 | #include "system.h" | ||
25 | |||
26 | #define ADC_I2C_ADDR 0xa0 | ||
27 | |||
28 | /* The M3 ADC is hooked exclusively to the secondary I²C bus, and requires | ||
29 | * very slow transfers (I²C clock <= 16kHz). So we start one 4-byte read | ||
30 | * transfer each tick, and handle it via an ISR. At 11MHz, one transfer | ||
31 | * takes too long to be started every tick, but it seems we have to live | ||
32 | * with that. */ | ||
33 | |||
34 | static unsigned char adc_data[NUM_ADC_CHANNELS] IBSS_ATTR; | ||
35 | static volatile bool data_ready = false; | ||
36 | |||
37 | |||
38 | static void adc_tick(void) | ||
39 | { | ||
40 | if ((MBSR2 & IBB) == 0) /* Bus is free */ | ||
41 | { | ||
42 | MBCR2 |= (MSTA|TXAK|MTX); /* Generate START and prepare for write */ | ||
43 | MBDR2 = ADC_I2C_ADDR|1; /* Send address */ | ||
44 | } | ||
45 | } | ||
26 | 46 | ||
27 | unsigned short adc_scan(int channel) | 47 | void IIC2(void) __attribute__((interrupt_handler)); |
48 | void IIC2(void) | ||
28 | { | 49 | { |
29 | /* TODO */ | 50 | static int bytenum = 0; |
30 | (void)channel; | 51 | |
31 | return 0xff; | 52 | MBSR2 &= ~IFF; /* Clear interrupt flag */ |
53 | |||
54 | if (MBSR2 & IAL) /* Arbitration lost - shouldn't happen */ | ||
55 | { /* normally, but CPU freq change might induce it */ | ||
56 | MBSR2 &= ~IAL; /* Clear flag */ | ||
57 | MBCR2 &= ~MSTA; /* STOP */ | ||
58 | } | ||
59 | else if (MBCR2 & MTX) /* Address phase */ | ||
60 | { | ||
61 | if (MBSR2 & RXAK) /* No ACK received */ | ||
62 | { | ||
63 | MBCR2 &= ~MSTA; /* STOP */ | ||
64 | return; | ||
65 | } | ||
66 | MBCR2 &= ~(MTX|TXAK); /* Switch to RX mode, enable TX ack generation */ | ||
67 | MBDR2; /* Dummy read */ | ||
68 | bytenum = 0; | ||
69 | } | ||
70 | else | ||
71 | { | ||
72 | switch (bytenum) | ||
73 | { | ||
74 | case 2: | ||
75 | MBCR2 |= TXAK; /* Don't ACK the last byte */ | ||
76 | break; | ||
77 | |||
78 | case 3: | ||
79 | MBCR2 &= ~MSTA; /* STOP before reading the last value */ | ||
80 | data_ready = true; /* Simplification - the last byte is a dummy. */ | ||
81 | break; | ||
82 | } | ||
83 | adc_data[bytenum++] = MBDR2; | ||
84 | } | ||
85 | |||
86 | } | ||
87 | |||
88 | unsigned short adc_read(int channel) | ||
89 | { | ||
90 | return adc_data[channel]; | ||
91 | } | ||
92 | |||
93 | void adc_init(void) | ||
94 | { | ||
95 | MFDR2 = 0x1f; /* I²C clock = SYSCLK / 3840 */ | ||
96 | MBCR2 = IEN; /* Enable interface */ | ||
97 | MBSR2 = 0; /* Clear flags */ | ||
98 | MBCR2 = (IEN|IIEN); /* Enable interrupts */ | ||
99 | |||
100 | and_l(~0x0f000000, &INTPRI8); | ||
101 | or_l( 0x04000000, &INTPRI8); /* INT62 - Priority 4 */ | ||
102 | |||
103 | tick_add_task(adc_tick); | ||
104 | |||
105 | while (!data_ready) | ||
106 | sleep(1); /* Ensure valid readings when adc_init returns */ | ||
32 | } | 107 | } |