10 files changed, 481 insertions, 69 deletions

diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c b/firmware/target/arm/s3c2440/adc-s3c2440.c
index fd5151a3bf..fd5151a3bf 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c
+++ b/firmware/target/arm/s3c2440/adc-s3c2440.c
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/wmcodec-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/wmcodec-meg-fx.c
index 52c26b898d..01b177da6c 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/wmcodec-meg-fx.c
+++ b/firmware/target/arm/s3c2440/gigabeat-fx/wmcodec-meg-fx.c
@@ -28,7 +28,7 @@
 #include "cpu.h"
 #include "kernel.h"
 #include "sound.h"
-#include "i2c-meg-fx.h"
+#include "i2c-s3c2440.h"
 #include "system-target.h"
 #include "timer.h"
 #include "wmcodec.h"
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c b/firmware/target/arm/s3c2440/i2c-s3c2440.c
index 836dedd462..4669186a4c 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c
+++ b/firmware/target/arm/s3c2440/i2c-s3c2440.c
@@ -19,7 +19,7 @@
  *
  ****************************************************************************/
 #include "system.h"
-#include "i2c-meg-fx.h"
+#include "i2c-s3c2440.h"
 
 static struct wakeup i2c_wake; /* Transfer completion signal */
 static struct mutex i2c_mtx;   /* Mutual exclusion */
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.h b/firmware/target/arm/s3c2440/i2c-s3c2440.h
index 793ee213fd..793ee213fd 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.h
+++ b/firmware/target/arm/s3c2440/i2c-s3c2440.h
diff --git a/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c b/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c
new file mode 100644
index 0000000000..237bf264f5
--- /dev/null
+++ b/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c
@@ -0,0 +1,292 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006 by Michael Sevakis
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include <stdlib.h>
+#include "system.h"
+#include "kernel.h"
+#include "logf.h"
+#include "audio.h"
+#include "sound.h"
+#include "file.h"
+
+/* PCM interrupt routine lockout */
+static struct
+{
+    int locked;
+    unsigned long state;
+} dma_play_lock =
+{
+    .locked = 0,
+    .state  = 0,
+};
+
+#define FIFO_COUNT ((IISFCON >> 6) & 0x3F)
+
+/* Setup for the DMA controller */
+#define DMA_CONTROL_SETUP  ((1<<31) | (1<<29) | (1<<23) | (1<<22) | (1<<20))
+
+#ifdef HAVE_UDA1341
+/* for PCLK = 50 MHz, frame size = 32 */
+/* [prescaler, master clock rate] */
+static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
+{
+    [HW_FREQ_64] = { 2, IISMOD_MASTER_CLOCK_256FS },
+    [HW_FREQ_44] = { 3, IISMOD_MASTER_CLOCK_384FS },
+    [HW_FREQ_22] = { 8, IISMOD_MASTER_CLOCK_256FS },
+    [HW_FREQ_11] = { 17, IISMOD_MASTER_CLOCK_256FS },
+};
+#endif
+
+/* DMA count has hit zero - no more data */
+/* Get more data from the callback and top off the FIFO */
+void fiq_handler(void) __attribute__((interrupt ("FIQ")));
+
+/* Mask the DMA interrupt */
+void pcm_play_lock(void)
+{
+    if (++dma_play_lock.locked == 1)
+        s3c_regset32(&INTMSK, DMA2_MASK);
+}
+
+/* Unmask the DMA interrupt if enabled */
+void pcm_play_unlock(void)
+{
+    if (--dma_play_lock.locked == 0)
+        s3c_regclr32(&INTMSK, dma_play_lock.state);
+}
+
+void pcm_play_dma_init(void)
+{
+    /* There seem to be problems when changing the IIS interface configuration
+     * when a clock is not present.
+     */
+    s3c_regset32(&CLKCON, 1<<17);
+    
+#ifdef HAVE_UDA1341
+    /* master, transmit mode, 16 bit samples, BCLK 32fs, PCLK */
+    IISMOD = IISMOD_MASTER_CLOCK_PCLK | IISMOD_MASTER_MODE | IISMOD_TRANSMIT_MODE
+             | IISMOD_16_BIT | IISMOD_MASTER_CLOCK_256FS | IISMOD_BIT_CLOCK_32FS;
+             
+    /* TX idle, enable prescaler */
+    IISCON |= IISCON_TX_IDLE | IISCON_IIS_PRESCALER_ENABLE;
+#else 
+    /* slave, transmit mode, 16 bit samples - MCLK 384fs - use 16.9344Mhz -
+       BCLK 32fs */
+    IISMOD = (1<<9) | (1<<8) | (2<<6) | (1<<3) | (1<<2) | (1<<0);
+
+    /* RX,TX off,on */
+    IISCON |= (1<<3) | (1<<2);
+#endif
+
+    s3c_regclr32(&CLKCON, 1<<17);
+
+    audiohw_init();
+
+    /* init GPIO */
+#ifdef GIGABEAT_F    
+/*    GPCCON = (GPCCON & ~(3<<14)) | (1<<14); */
+    S3C244_GPIO_CONFIG (GPCCON, 7, GPIO_OUTPUT);
+    GPCDAT |= (1<<7);
+#endif
+    
+    /* GPE4=I2SDO, GPE3=I2SDI, GPE2=CDCLK, GPE1=I2SSCLK, GPE0=I2SLRCK */
+    GPECON = (GPECON & ~0x3ff) | 0x2aa;
+
+    /* Do not service DMA requests, yet */
+
+    /* clear any pending int and mask it */
+    s3c_regset32(&INTMSK, DMA2_MASK);
+    SRCPND = DMA2_MASK;
+
+    /* connect to FIQ */
+    s3c_regset32(&INTMOD, DMA2_MASK);
+}
+
+void pcm_postinit(void)
+{
+    audiohw_postinit();
+}
+
+void pcm_dma_apply_settings(void)
+{
+#ifdef HAVE_UDA1341
+    /* set prescaler and master clock rate according to freq */
+    IISPSR = (pcm_freq_parms [pcm_fsel][0] * IISPSR_PRESCALER_A) | pcm_freq_parms [pcm_fsel][0];
+    IISMOD |= ~IISMOD_MASTER_CLOCK_384FS | pcm_freq_parms [pcm_fsel][1] ;
+#endif
+
+    audiohw_set_frequency(pcm_fsel);
+}
+
+/* Connect the DMA and start filling the FIFO */
+static void play_start_pcm(void)
+{
+    /* clear pending DMA interrupt */
+    SRCPND = DMA2_MASK;
+
+    /* Flush any pending writes */
+    clean_dcache_range((char*)DISRC2-0x30000000, (DCON2 & 0xFFFFF) * 2);
+
+    /* unmask DMA interrupt when unlocking */
+    dma_play_lock.state = DMA2_MASK;
+
+    /* turn on the request */
+    IISCON |= (1<<5);
+
+    /* Activate the channel */
+    DMASKTRIG2 = 0x2;
+
+    /* turn off the idle */
+    IISCON &= ~(1<<3);
+
+    /* start the IIS */
+    IISCON |= (1<<0);
+}
+
+/* Disconnect the DMA and wait for the FIFO to clear */
+static void play_stop_pcm(void)
+{
+    /* Mask DMA interrupt */
+    s3c_regset32(&INTMSK, DMA2_MASK);
+
+    /* De-Activate the DMA channel */
+    DMASKTRIG2 = 0x4;
+
+    /* are we playing? wait for the chunk to finish */
+    if (dma_play_lock.state != 0)
+    {
+        /* wait for the FIFO to empty and DMA to stop */
+        while ((IISCON & (1<<7)) || (DMASKTRIG2 & 0x2));
+    }
+
+    /* Keep interrupt masked when unlocking */
+    dma_play_lock.state = 0;
+
+    /* turn off the request */
+    IISCON &= ~(1<<5);
+
+    /* turn on the idle */
+    IISCON |= (1<<3);
+
+    /* stop the IIS */
+    IISCON &= ~(1<<0);
+}
+
+void pcm_play_dma_start(const void *addr, size_t size)
+{
+    /* Enable the IIS clock */
+    s3c_regset32(&CLKCON, 1<<17);
+
+    /* stop any DMA in progress - idle IIS */
+    play_stop_pcm();
+
+    /* connect DMA to the FIFO and enable the FIFO */
+    IISFCON = (1<<15) | (1<<13);
+
+    /* set DMA dest */
+    DIDST2 = (unsigned int)&IISFIFO;
+
+    /* IIS is on the APB bus, INT when TC reaches 0, fixed dest addr */
+    DIDSTC2 = 0x03;
+
+    /* set DMA source and options */
+    DISRC2 = (unsigned int)addr + 0x30000000;
+    /* How many transfers to make - we transfer half-word at a time = 2 bytes */
+    /* DMA control: CURR_TC int, single service mode, I2SSDO int, HW trig */
+    /*     no auto-reload, half-word (16bit) */
+    DCON2 = DMA_CONTROL_SETUP | (size / 2);
+    DISRCC2 = 0x00;  /* memory is on AHB bus, increment addresses */
+
+    play_start_pcm();
+}
+
+/* Promptly stop DMA transfers and stop IIS */
+void pcm_play_dma_stop(void)
+{
+    play_stop_pcm();
+
+    /* Disconnect the IIS clock */
+    s3c_regclr32(&CLKCON, 1<<17);
+}
+
+void pcm_play_dma_pause(bool pause)
+{
+    if (pause)
+    {
+        /* pause playback on current buffer */
+        play_stop_pcm();
+    }
+    else
+    {
+        /* restart playback on current buffer */
+        /* make sure we're aligned on left channel - skip any right
+           channel sample left waiting */
+        DISRC2 = (DCSRC2 + 2) & ~0x3;
+        DCON2  = DMA_CONTROL_SETUP | (DSTAT2 & 0xFFFFE);
+        play_start_pcm();
+    }
+}
+
+void fiq_handler(void)
+{
+    static unsigned char *start;
+    static size_t         size;
+    register pcm_more_callback_type get_more;   /* No stack for this */
+
+    /* clear any pending interrupt */
+    SRCPND = DMA2_MASK;
+
+    /* Buffer empty.  Try to get more. */
+    get_more = pcm_callback_for_more;
+    size = 0;
+
+    if (get_more == NULL || (get_more(&start, &size), size == 0))
+    {
+        /* Callback missing or no more DMA to do */
+        pcm_play_dma_stop();
+        pcm_play_dma_stopped_callback();
+    }
+    else
+    {
+        /* Flush any pending cache writes */
+        clean_dcache_range(start, size);
+
+        /* set the new DMA values */
+        DCON2 = DMA_CONTROL_SETUP | (size >> 1);
+        DISRC2 = (unsigned int)start + 0x30000000;
+
+        /* Re-Activate the channel */
+        DMASKTRIG2 = 0x2;
+    }
+}
+
+size_t pcm_get_bytes_waiting(void)
+{
+    /* lie a little and only return full pairs */
+    return (DSTAT2 & 0xFFFFE) * 2;
+}
+
+const void * pcm_play_dma_get_peak_buffer(int *count)
+{
+    unsigned long addr = DCSRC2;
+    int cnt = DSTAT2;
+    *count = (cnt & 0xFFFFF) >> 1;
+    return (void *)((addr + 2) & ~3);
+}
diff --git a/firmware/target/arm/s3c2440/mini2440/powermgmt-mini2440.c b/firmware/target/arm/s3c2440/mini2440/powermgmt-mini2440.c
new file mode 100644
index 0000000000..5584993040
--- /dev/null
+++ b/firmware/target/arm/s3c2440/mini2440/powermgmt-mini2440.c
@@ -0,0 +1,69 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2009 by Bob Cousins
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "config.h"
+#include "system.h"
+#include "adc.h"
+#include "power.h"
+#include "powermgmt.h"
+
+/* The following constants are dummy values since there is no battery */
+const unsigned short battery_level_dangerous[BATTERY_TYPES_COUNT] =
+{
+    3450
+};
+
+const unsigned short battery_level_shutoff[BATTERY_TYPES_COUNT] =
+{
+    3400
+};
+
+/* voltages (millivolt) of 0%, 10%, ... 100% when charging disabled */
+const unsigned short percent_to_volt_discharge[BATTERY_TYPES_COUNT][11] =
+{
+    /* Typical Li Ion 830mAH  */
+    { 3480, 3550, 3590, 3610, 3630, 3650, 3700, 3760, 3800, 3910, 3990 },
+};
+
+/* voltages (millivolt) of 0%, 10%, ... 100% when charging enabled */
+const unsigned short percent_to_volt_charge[11] =
+{
+    /* Typical Li Ion 830mAH */
+    3480, 3550, 3590, 3610, 3630, 3650, 3700, 3760, 3800, 3910, 3990
+};
+
+
+/* Returns battery voltage from ADC [millivolts] */
+/* full-scale (2^10) in millivolt */
+unsigned int battery_adc_voltage(void)
+{
+    /* Since we have no battery, return a fully charged value */
+    return 4000 * 1024 / 1000;
+}
+
+unsigned int input_millivolts(void)
+{
+    unsigned int batt_millivolts = battery_voltage();
+
+   /* No battery, return nominal value */
+    return batt_millivolts;
+}
+
+
diff --git a/firmware/target/arm/s3c2440/sd-s3c2440.c b/firmware/target/arm/s3c2440/sd-s3c2440.c
index 78c9e9bf23..9cb9bdfc58 100644
--- a/firmware/target/arm/s3c2440/sd-s3c2440.c
+++ b/firmware/target/arm/s3c2440/sd-s3c2440.c
@@ -126,9 +126,6 @@ static unsigned char *  uncached_buffer;
 /*****************************************************************************
     Definitions specific to Mini2440
  *****************************************************************************/
-#define FCLK 405000000
-#define HCLK (FCLK/4)   /* = 101,250,000 */
-#define PCLK (HCLK/2)   /* =  50,625,000 */
 
 #define SD_CD (1<<8)    /* Port G */
 #define SD_WP (1<<8)    /* Port H */
@@ -206,8 +203,11 @@ static void debug_r1(int cmd)
 void SDI (void)
 {
     int status = SDIDSTA;
+#ifndef HAVE_MULTIDRIVE
+    const int curr_card = 0;
+#endif     
     
-    transfer_error[curr_card] = status 
+    transfer_error[curr_card] = status
 #if 0
         & ( S3C2410_SDIDSTA_CRCFAIL | S3C2410_SDIDSTA_RXCRCFAIL |
             S3C2410_SDIDSTA_DATATIMEOUT )
@@ -619,7 +619,9 @@ static int sd_transfer_sectors(IF_MD2(int card_no,) unsigned long start,
     sd_enable(true);
     set_leds(SD_ACTIVE_LED);
 
+#ifdef HAVE_MULTIDRIVE
     curr_card = card_no;
+#endif
     if (card_info[card_no].initialized <= 0)
     {
         ret = sd_init_card(card_no);
@@ -814,6 +816,9 @@ int sd_read_sectors(IF_MD2(int card_no,) unsigned long start, int incount,
 int sd_write_sectors(IF_MD2(int card_no,) unsigned long start, int count,
                       const void* outbuf)
 {
+#ifndef HAVE_MULTIDRIVE
+    const int card_no = 0;
+#endif
     dbgprintf ("sd_write %d %x %d\n", card_no, start, count);
     
     return sd_transfer_sectors(IF_MD2(card_no,) start, count, outbuf, true);
diff --git a/firmware/target/arm/s3c2440/system-target.h b/firmware/target/arm/s3c2440/system-target.h
index 9808d31255..cf3db301eb 100644
--- a/firmware/target/arm/s3c2440/system-target.h
+++ b/firmware/target/arm/s3c2440/system-target.h
@@ -27,30 +27,34 @@
 /* TODO: Needs checking/porting */

 

 #ifdef GIGABEAT_F

-#define CPUFREQ_DEFAULT 98784000

-#define CPUFREQ_NORMAL  98784000

-#define CPUFREQ_MAX    296352000

+    #define CPUFREQ_DEFAULT 98784000

+    #define CPUFREQ_NORMAL  98784000

+    #define CPUFREQ_MAX    296352000

 

-#ifdef BOOTLOADER

-/* All addresses within rockbox are in IRAM in the bootloader so

-   are therefore uncached */

-#define UNCACHED_ADDR(a) (a)

-#else /* !BOOTLOADER */

-#define UNCACHED_BASE_ADDR 0x30000000

-#define UNCACHED_ADDR(a)  ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR ))

-#endif /* BOOTLOADER */

+    #ifdef BOOTLOADER

+        /* All addresses within rockbox are in IRAM in the bootloader so

+           are therefore uncached */

+        #define UNCACHED_ADDR(a) (a)

+    #else /* !BOOTLOADER */

+        #define UNCACHED_BASE_ADDR 0x30000000

+        #define UNCACHED_ADDR(a)  ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR ))

+    #endif /* BOOTLOADER */

 

 #elif defined(MINI2440)

 

-#define CPUFREQ_DEFAULT 101250000

-#define CPUFREQ_NORMAL  101250000

-#define CPUFREQ_MAX     405000000

-

-#define UNCACHED_BASE_ADDR 0x30000000

-#define UNCACHED_ADDR(a)  ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR ))

+    #define CPUFREQ_DEFAULT 101250000

+    #define CPUFREQ_NORMAL  101250000

+    #define CPUFREQ_MAX     405000000

+    

+    #define UNCACHED_BASE_ADDR 0x30000000

+    #define UNCACHED_ADDR(a)  ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR ))

 

+    #define FCLK 405000000

+    #define HCLK (FCLK/4)   /* = 101,250,000 */

+    #define PCLK (HCLK/2)   /* =  50,625,000 */

+    

 #else

-#error Unknown target

+    #error Unknown target

 #endif

 

 

diff --git a/firmware/target/arm/s3c2440/uart-s3c2440.c b/firmware/target/arm/s3c2440/uart-s3c2440.c
index 2a61b61a39..84282f731a 100644
--- a/firmware/target/arm/s3c2440/uart-s3c2440.c
+++ b/firmware/target/arm/s3c2440/uart-s3c2440.c
@@ -30,13 +30,32 @@
 #include "kernel.h"
 #include "thread.h"
 
+#include "system-target.h"
 #include "uart-s3c2440.h"
 
-#define FCLK 405000000
-#define HCLK (FCLK/4)   /* = 101,250,000 */
-#define PCLK (HCLK/2)   /* =  50,625,000 */
+#define MAX_PRINTF_BUF        1024
 
-#define MAX_TX_BUF        1024
+/****************************************************************************
+ * serial driver API 
+ ****************************************************************************/
+void serial_setup (void)
+{
+    uart_init();
+    uart_init_device(DEBUG_UART_PORT);
+}
+
+int tx_rdy(void)
+{
+    if (uart_tx_ready (DEBUG_UART_PORT))
+        return 1;
+    else
+        return 0;
+}
+
+void tx_writec(unsigned char c)
+{
+    uart_send_byte (DEBUG_UART_PORT, c);
+}
 
 
 /****************************************************************************
@@ -46,10 +65,12 @@
 void uart_printf (const char *format, ...)
 {
     static bool debug_uart_init = false;
-    static char tx_buf [MAX_TX_BUF];
+    static char tx_buf [MAX_PRINTF_BUF];
 
     int len;
     unsigned char *ptr;
+    int j;
+    
     va_list ap;
     va_start(ap, format);
 
@@ -59,11 +80,16 @@ void uart_printf (const char *format, ...)
 
     if (!debug_uart_init)
     {
-      uart_init_device(UART_DEBUG);
+      uart_init_device(DEBUG_UART_PORT);
       debug_uart_init = true;
     }
     
-    uart_send (UART_DEBUG, tx_buf, len);
+    for (j=0; j<len; j++)
+    {
+        uart_send_byte (DEBUG_UART_PORT, tx_buf[j]);
+        if ( tx_buf[j] == '\n')
+            uart_send_byte (DEBUG_UART_PORT, '\r');
+    }
 }
 
 /****************************************************************************
@@ -142,28 +168,49 @@ bool uart_config (unsigned dev, unsigned speed, unsigned num_bits,
     return true;
 }
 
+/* transmit */
+bool uart_tx_ready (unsigned dev)
+{
+    /* test if transmit buffer empty */
+    switch (dev)
+    {
+    case 0:
+        if (UTRSTAT0 & 0x02)
+            return true;
+        else
+            return false;
+        break;
+    case 1:
+        if (UTRSTAT1 & 0x02)
+            return true;
+        else
+            return false;
+        break;
+    case 2:
+        if (UTRSTAT2 & 0x02)
+            return true;
+        else
+            return false;
+        break;
+    }
+    return false;
+}
+
 bool uart_send_byte (unsigned dev, char ch)
 {
+    /* wait for transmit buffer empty */
+    while (!uart_tx_ready(dev))
+        ;
+        
     switch (dev)
     {
     case 0:
-        /* wait for transmit buffer empty */
-        while ((UTRSTAT0 & 0x02) == 0)
-          ;
         UTXH0 = ch;
         break;
-
     case 1:
-        /* wait for transmit buffer empty */
-        while ((UTRSTAT1 & 0x02) == 0)
-          ;
         UTXH1 = ch;
         break;
-
     case 2:
-        /* wait for transmit buffer empty */
-        while ((UTRSTAT2 & 0x02) == 0)
-          ;
         UTXH2 = ch;
         break;
     }
@@ -171,26 +218,26 @@ bool uart_send_byte (unsigned dev, char ch)
     return true;
 }
 
-char uart_rx_ready (unsigned dev)
+/* Receive */
+
+bool uart_rx_ready (unsigned dev)
 {
+    /* test receive buffer data ready */
     switch (dev)
     {
     case 0:
-        /* wait for receive buffer data ready */
         if (UTRSTAT0 & 0x01)
             return true;
         else
             return false;
         break;
     case 1:
-        /* wait for receive buffer data ready */
         if (UTRSTAT1 & 0x01)
             return true;
         else
             return false;
         break;
     case 2:
-        /* wait for receive buffer data ready */
         if (UTRSTAT2 & 0x01)
             return true;
         else
@@ -202,43 +249,34 @@ char uart_rx_ready (unsigned dev)
 
 char uart_read_byte (unsigned dev)
 {
+    while (!uart_rx_ready(dev))
+        ;
     switch (dev)
     {
     case 0:
-        while (!uart_rx_ready(dev))
-            ;
         return URXH0;
         break;
     case 1:
-        while (!uart_rx_ready(dev))
-            ;
         return URXH1;
         break;
     case 2:
-        while (!uart_rx_ready(dev))
-            ;
         return URXH2;
         break;
     }
     
-    return true;
+    return '\0';
 }
 
 /****************************************************************************
  * General
  *****************************************************************************/
 
-bool uart_send (unsigned dev, char *buf, unsigned len)
+bool uart_send_buf (unsigned dev, char *buf, unsigned len)
 {
     unsigned index=0;
     while (index<len)
     {
         uart_send_byte (dev, buf[index]);
-        
-        /* hack for ASCII terminals */
-        if (buf[index] == '\n')
-          uart_send_byte (dev, '\r');
-          
         index++;
     }
     return true;
diff --git a/firmware/target/arm/s3c2440/uart-s3c2440.h b/firmware/target/arm/s3c2440/uart-s3c2440.h
index 01a8f67ea1..38790af8e8 100644
--- a/firmware/target/arm/s3c2440/uart-s3c2440.h
+++ b/firmware/target/arm/s3c2440/uart-s3c2440.h
@@ -22,16 +22,17 @@
 #ifndef __UART_S3C2440_H__
 #define __UART_S3C2440_H__
 
-#define UART_DEBUG        0
+/* target specific */
+#define DEBUG_UART_PORT     0
 
-#define UART_NO_PARITY    0
-#define UART_ODD_PARITY   4
-#define UART_EVEN_PARITY  5
-#define UART_MARK_PARITY  6
-#define UART_SPACE_PARITY 7
+#define UART_NO_PARITY      0
+#define UART_ODD_PARITY     4
+#define UART_EVEN_PARITY    5
+#define UART_MARK_PARITY    6
+#define UART_SPACE_PARITY   7
 
-#define UART_1_STOP_BIT   0
-#define UART_2_STOP_BIT   1
+#define UART_1_STOP_BIT     0
+#define UART_2_STOP_BIT     1
 
 bool uart_init (void);
 void uart_printf (const char *format, ...);
@@ -39,10 +40,13 @@ void uart_printf (const char *format, ...);
 /* low level routines */
 bool uart_init_device (unsigned dev);
 bool uart_config (unsigned dev, unsigned speed, unsigned num_bits, unsigned parity, unsigned stop_bits);
-bool uart_send (unsigned dev, char *buf, unsigned len);
 
+bool uart_tx_ready  (unsigned dev);
+bool uart_send_byte (unsigned dev, char ch);
+bool uart_send_buf  (unsigned dev, char *buf, unsigned len);
+
+bool uart_rx_ready  (unsigned dev);
 char uart_read_byte (unsigned dev);
-char uart_rx_ready (unsigned dev);
 
 
 #endif