diff options
Diffstat (limited to 'firmware/target/arm')
-rw-r--r-- | firmware/target/arm/mmu-arm.c (renamed from firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.c) | 89 | ||||
-rw-r--r-- | firmware/target/arm/mmu-arm.h (renamed from firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.h) | 8 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/ata-meg-fx.c | 1 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c | 1 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c | 16 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/system-target.h | 2 | ||||
-rwxr-xr-x | firmware/target/arm/tms320dm320/crt0.S | 18 | ||||
-rw-r--r-- | firmware/target/arm/tms320dm320/mrobe-500/lcd-mr500.c | 1 | ||||
-rw-r--r-- | firmware/target/arm/tms320dm320/system-dm320.c | 15 | ||||
-rw-r--r-- | firmware/target/arm/tms320dm320/uart-dm320.c | 3 |
10 files changed, 89 insertions, 65 deletions
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.c b/firmware/target/arm/mmu-arm.c index c47c1330bc..db7f5e59cd 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.c +++ b/firmware/target/arm/mmu-arm.c | |||
@@ -1,51 +1,42 @@ | |||
1 | #include <string.h> | 1 | /*************************************************************************** |
2 | #include "s3c2440.h" | 2 | * __________ __ ___. |
3 | #include "mmu-meg-fx.h" | 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ |
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2006,2007 by Greg White | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | #include "cpu.h" | ||
20 | #include "mmu-arm.h" | ||
4 | #include "panic.h" | 21 | #include "panic.h" |
5 | 22 | ||
6 | static void enable_mmu(void); | ||
7 | static void set_ttb(void); | ||
8 | static void set_page_tables(void); | ||
9 | static void map_section(unsigned int pa, unsigned int va, int mb, int cache_flags); | ||
10 | |||
11 | #define SECTION_ADDRESS_MASK (-1 << 20) | 23 | #define SECTION_ADDRESS_MASK (-1 << 20) |
12 | #define CACHE_ALL (1 << 3 | 1 << 2 ) | ||
13 | #define CACHE_NONE 0 | ||
14 | #define BUFFERED (1 << 2) | ||
15 | #define MB (1 << 20) | 24 | #define MB (1 << 20) |
16 | 25 | ||
17 | void memory_init(void) { | 26 | void ttb_init(void) { |
18 | set_ttb(); | 27 | unsigned int* ttbPtr; |
19 | set_page_tables(); | ||
20 | enable_mmu(); | ||
21 | } | ||
22 | |||
23 | unsigned int* ttb_base = (unsigned int *) TTB_BASE; | ||
24 | const int ttb_size = 4096; | ||
25 | |||
26 | void set_ttb() { | ||
27 | int i; | ||
28 | int* ttbPtr; | ||
29 | int domain_access; | ||
30 | |||
31 | /* must be 16Kb (0x4000) aligned */ | ||
32 | ttb_base = (int*) TTB_BASE; | ||
33 | for (i=0; i<ttb_size; i++,ttbPtr++) | ||
34 | ttbPtr = 0; | ||
35 | asm volatile("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttb_base)); | ||
36 | |||
37 | /* set domain D0 to "client" permission access */ | ||
38 | |||
39 | domain_access = 3; | ||
40 | asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (domain_access)); | ||
41 | 28 | ||
42 | } | 29 | /* must be 16Kb (0x4000) aligned - clear out the TTB */ |
30 | for (ttbPtr=TTB_BASE; ttbPtr<(TTB_SIZE+TTB_BASE); ttbPtr++) | ||
31 | { | ||
32 | *ttbPtr = 0; | ||
33 | } | ||
43 | 34 | ||
44 | void set_page_tables() { | 35 | /* Set the TTB base address */ |
36 | asm volatile("mcr p15, 0, %0, c2, c0, 0" : : "r" (TTB_BASE)); | ||
45 | 37 | ||
46 | map_section(0, 0, 0x1000, CACHE_NONE); /* map every memory region to itself */ | 38 | /* Set all domains to manager status */ |
47 | map_section(0x30000000, 0, 32, CACHE_ALL); /* map RAM to 0 and enable caching for it */ | 39 | asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (0xFFFFFFFF)); |
48 | map_section((int)FRAME, (int)FRAME, 1, BUFFERED); /* enable buffered writing for the framebuffer */ | ||
49 | } | 40 | } |
50 | 41 | ||
51 | void map_section(unsigned int pa, unsigned int va, int mb, int cache_flags) { | 42 | void map_section(unsigned int pa, unsigned int va, int mb, int cache_flags) { |
@@ -54,20 +45,20 @@ void map_section(unsigned int pa, unsigned int va, int mb, int cache_flags) { | |||
54 | int section_no; | 45 | int section_no; |
55 | 46 | ||
56 | section_no = va >> 20; /* sections are 1Mb size */ | 47 | section_no = va >> 20; /* sections are 1Mb size */ |
57 | ttbPtr = ttb_base + section_no; | 48 | ttbPtr = TTB_BASE + section_no; |
58 | pa &= SECTION_ADDRESS_MASK; /* align to 1Mb */ | 49 | pa &= SECTION_ADDRESS_MASK; /* align to 1Mb */ |
59 | for(i=0; i<mb; i++, pa += MB) { | 50 | for(i=0; i<mb; i++, pa += MB) { |
60 | *(ttbPtr + i) = | 51 | *(ttbPtr + i) = |
61 | pa | | 52 | pa | |
62 | 1 << 10 | /* superuser - r/w, user - no access */ | 53 | 1 << 10 | /* superuser - r/w, user - no access */ |
63 | 0 << 5 | /* domain 0th */ | 54 | 0 << 5 | /* domain 0th */ |
64 | 1 << 4 | /* should be "1" */ | 55 | 1 << 4 | /* should be "1" */ |
65 | cache_flags | | 56 | cache_flags | |
66 | 1 << 1; /* Section signature */ | 57 | 1 << 1; /* Section signature */ |
67 | } | 58 | } |
68 | } | 59 | } |
69 | 60 | ||
70 | static void enable_mmu(void) { | 61 | void enable_mmu(void) { |
71 | int regread; | 62 | int regread; |
72 | 63 | ||
73 | asm volatile( | 64 | asm volatile( |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.h b/firmware/target/arm/mmu-arm.h index 524978852d..b744305dbd 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.h +++ b/firmware/target/arm/mmu-arm.h | |||
@@ -17,6 +17,14 @@ | |||
17 | * | 17 | * |
18 | ****************************************************************************/ | 18 | ****************************************************************************/ |
19 | 19 | ||
20 | #define CACHE_ALL (1 << 3 | 1 << 2 ) | ||
21 | #define CACHE_NONE 0 | ||
22 | #define BUFFERED (1 << 2) | ||
23 | |||
24 | void ttb_init(void); | ||
25 | void enable_mmu(void); | ||
26 | void map_section(unsigned int pa, unsigned int va, int mb, int cache_flags); | ||
27 | |||
20 | /* Invalidate DCache for this range */ | 28 | /* Invalidate DCache for this range */ |
21 | /* Will do write back */ | 29 | /* Will do write back */ |
22 | void invalidate_dcache_range(const void *base, unsigned int size); | 30 | void invalidate_dcache_range(const void *base, unsigned int size); |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/ata-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/ata-meg-fx.c index d33bcaaf6e..1f5c5c8fbe 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/ata-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/ata-meg-fx.c | |||
@@ -25,7 +25,6 @@ | |||
25 | #include "panic.h" | 25 | #include "panic.h" |
26 | #include "pcf50606.h" | 26 | #include "pcf50606.h" |
27 | #include "ata-target.h" | 27 | #include "ata-target.h" |
28 | #include "mmu-meg-fx.h" | ||
29 | #include "backlight-target.h" | 28 | #include "backlight-target.h" |
30 | 29 | ||
31 | /* ARESET on C7C68300 and RESET on ATA interface (Active Low) */ | 30 | /* ARESET on C7C68300 and RESET on ATA interface (Active Low) */ |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c index a38b4e424e..7f25cb6a15 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c | |||
@@ -23,7 +23,6 @@ | |||
23 | #include "audio.h" | 23 | #include "audio.h" |
24 | #include "sound.h" | 24 | #include "sound.h" |
25 | #include "file.h" | 25 | #include "file.h" |
26 | #include "mmu-meg-fx.h" | ||
27 | 26 | ||
28 | /* All exact rates for 16.9344MHz clock */ | 27 | /* All exact rates for 16.9344MHz clock */ |
29 | #define GIGABEAT_11025HZ (0x19 << 1) | 28 | #define GIGABEAT_11025HZ (0x19 << 1) |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c index 00cf626ab3..c7b1b77c9f 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c | |||
@@ -1,7 +1,8 @@ | |||
1 | #include "kernel.h" | 1 | #include "kernel.h" |
2 | #include "system.h" | 2 | #include "system.h" |
3 | #include "panic.h" | 3 | #include "panic.h" |
4 | #include "mmu-meg-fx.h" | 4 | #include "mmu-arm.h" |
5 | #include "cpu.h" | ||
5 | 6 | ||
6 | #define default_interrupt(name) \ | 7 | #define default_interrupt(name) \ |
7 | extern __attribute__((weak,alias("UIRQ"))) void name (void) | 8 | extern __attribute__((weak,alias("UIRQ"))) void name (void) |
@@ -90,6 +91,19 @@ void system_reboot(void) | |||
90 | ; | 91 | ; |
91 | } | 92 | } |
92 | 93 | ||
94 | static void set_page_tables(void) | ||
95 | { | ||
96 | map_section(0, 0, 0x1000, CACHE_NONE); /* map every memory region to itself */ | ||
97 | map_section(0x30000000, 0, 32, CACHE_ALL); /* map RAM to 0 and enable caching for it */ | ||
98 | map_section((int)FRAME, (int)FRAME, 1, BUFFERED); /* enable buffered writing for the framebuffer */ | ||
99 | } | ||
100 | |||
101 | void memory_init(void) { | ||
102 | ttb_init(); | ||
103 | set_page_tables(); | ||
104 | enable_mmu(); | ||
105 | } | ||
106 | |||
93 | void system_init(void) | 107 | void system_init(void) |
94 | { | 108 | { |
95 | /* Disable interrupts and set all to IRQ mode */ | 109 | /* Disable interrupts and set all to IRQ mode */ |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h b/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h index 215b5a4daa..2fab652596 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h +++ b/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h | |||
@@ -19,8 +19,8 @@ | |||
19 | #ifndef SYSTEM_TARGET_H | 19 | #ifndef SYSTEM_TARGET_H |
20 | #define SYSTEM_TARGET_H | 20 | #define SYSTEM_TARGET_H |
21 | 21 | ||
22 | #include "mmu-meg-fx.h" | ||
23 | #include "system-arm.h" | 22 | #include "system-arm.h" |
23 | #include "mmu-arm.h" | ||
24 | 24 | ||
25 | #define CPUFREQ_DEFAULT 98784000 | 25 | #define CPUFREQ_DEFAULT 98784000 |
26 | #define CPUFREQ_NORMAL 98784000 | 26 | #define CPUFREQ_NORMAL 98784000 |
diff --git a/firmware/target/arm/tms320dm320/crt0.S b/firmware/target/arm/tms320dm320/crt0.S index 68c0d9e1c5..8c747f7a51 100755 --- a/firmware/target/arm/tms320dm320/crt0.S +++ b/firmware/target/arm/tms320dm320/crt0.S | |||
@@ -48,14 +48,19 @@ start: | |||
48 | str r0, [r1, #28] | 48 | str r0, [r1, #28] |
49 | #endif | 49 | #endif |
50 | 50 | ||
51 | /* Disable high vectors (at 0xffff0000 instead of 0x00000000) */ | 51 | /* Disable data and instruction cache, high vectors (at 0xffff0000 instead of 0x00000000) */ |
52 | mrc p15, 0, r0, c1, c0 | 52 | mrc p15, 0, r0, c1, c0, 0 |
53 | and r0, r0, #~(1<<13) | 53 | /* clear bits 13, 9:8 (--VI --RS) */ |
54 | mcr p15, 0, r0, c1, c0 | 54 | bic r0, r0, #0x00003300 |
55 | /* clear bits 7, 2:0 (B--- -C-M) */ | ||
56 | bic r0, r0, #0x00000085 | ||
57 | /* make sure bit 2 (A) Align is set */ | ||
58 | orr r0, r0, #0x00000002 | ||
59 | mcr p15, 0, r0, c1, c0, 0 | ||
55 | 60 | ||
56 | #if !defined(BOOTLOADER) | 61 | #if !defined(BOOTLOADER) |
57 | 62 | ||
58 | #if 0//!defined(STUB) | 63 | #if !defined(STUB) |
59 | /* Zero out IBSS */ | 64 | /* Zero out IBSS */ |
60 | ldr r2, =_iedata | 65 | ldr r2, =_iedata |
61 | ldr r3, =_iend | 66 | ldr r3, =_iend |
@@ -64,8 +69,7 @@ start: | |||
64 | cmp r3, r2 | 69 | cmp r3, r2 |
65 | strhi r4, [r2], #4 | 70 | strhi r4, [r2], #4 |
66 | bhi 1b | 71 | bhi 1b |
67 | #endif | 72 | |
68 | #if 1 | ||
69 | /* Copy the IRAM */ | 73 | /* Copy the IRAM */ |
70 | ldr r2, =_iramcopy | 74 | ldr r2, =_iramcopy |
71 | ldr r3, =_iramstart | 75 | ldr r3, =_iramstart |
diff --git a/firmware/target/arm/tms320dm320/mrobe-500/lcd-mr500.c b/firmware/target/arm/tms320dm320/mrobe-500/lcd-mr500.c index 37286bffc4..bc1439762d 100644 --- a/firmware/target/arm/tms320dm320/mrobe-500/lcd-mr500.c +++ b/firmware/target/arm/tms320dm320/mrobe-500/lcd-mr500.c | |||
@@ -82,7 +82,6 @@ void lcd_init_device(void) | |||
82 | void lcd_update_rect(int x, int y, int width, int height) | 82 | void lcd_update_rect(int x, int y, int width, int height) |
83 | { | 83 | { |
84 | fb_data *dst, *src; | 84 | fb_data *dst, *src; |
85 | int yc; | ||
86 | 85 | ||
87 | if (!lcd_on) | 86 | if (!lcd_on) |
88 | return; | 87 | return; |
diff --git a/firmware/target/arm/tms320dm320/system-dm320.c b/firmware/target/arm/tms320dm320/system-dm320.c index 8a50ba7f08..f3f8dcea26 100644 --- a/firmware/target/arm/tms320dm320/system-dm320.c +++ b/firmware/target/arm/tms320dm320/system-dm320.c | |||
@@ -16,7 +16,8 @@ | |||
16 | * KIND, either express or implied. | 16 | * KIND, either express or implied. |
17 | * | 17 | * |
18 | ****************************************************************************/ | 18 | ****************************************************************************/ |
19 | 19 | #include "cpu.h" | |
20 | #include "mmu-arm.h" | ||
20 | #include "kernel.h" | 21 | #include "kernel.h" |
21 | #include "system.h" | 22 | #include "system.h" |
22 | #include "panic.h" | 23 | #include "panic.h" |
@@ -26,6 +27,9 @@ | |||
26 | #define default_interrupt(name) \ | 27 | #define default_interrupt(name) \ |
27 | extern __attribute__((weak,alias("UIRQ"))) void name (void) | 28 | extern __attribute__((weak,alias("UIRQ"))) void name (void) |
28 | 29 | ||
30 | void irq_handler(void) __attribute__((interrupt ("IRQ"), naked)); | ||
31 | void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked)); | ||
32 | |||
29 | default_interrupt(TIMER0); | 33 | default_interrupt(TIMER0); |
30 | default_interrupt(TIMER1); | 34 | default_interrupt(TIMER1); |
31 | default_interrupt(TIMER2); | 35 | default_interrupt(TIMER2); |
@@ -101,7 +105,6 @@ static void UIRQ(void) | |||
101 | panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]); | 105 | panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]); |
102 | } | 106 | } |
103 | 107 | ||
104 | void irq_handler(void) __attribute__((interrupt ("IRQ"), naked)); | ||
105 | void irq_handler(void) | 108 | void irq_handler(void) |
106 | { | 109 | { |
107 | /* | 110 | /* |
@@ -116,7 +119,6 @@ void irq_handler(void) | |||
116 | "subs pc, lr, #4 \n"); /* Return from FIQ */ | 119 | "subs pc, lr, #4 \n"); /* Return from FIQ */ |
117 | } | 120 | } |
118 | 121 | ||
119 | void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked)); | ||
120 | void fiq_handler(void) | 122 | void fiq_handler(void) |
121 | { | 123 | { |
122 | /* | 124 | /* |
@@ -179,6 +181,13 @@ void system_init(void) | |||
179 | enable_interrupts(); | 181 | enable_interrupts(); |
180 | uart_init(); | 182 | uart_init(); |
181 | spi_init(); | 183 | spi_init(); |
184 | |||
185 | /* MMU initialization (Starts data and instruction cache) */ | ||
186 | ttb_init(); | ||
187 | map_section(0, 0, 0x1000, CACHE_NONE); /* Make sure everything is mapped on itself */ | ||
188 | map_section(0x00900000, 0x00900000, 64, CACHE_ALL); /* Enable caching for RAM */ | ||
189 | map_section((int)FRAME, (int)FRAME, 2, BUFFERED); /* enable buffered writing for the framebuffer */ | ||
190 | enable_mmu(); | ||
182 | } | 191 | } |
183 | 192 | ||
184 | int system_memory_guard(int newmode) | 193 | int system_memory_guard(int newmode) |
diff --git a/firmware/target/arm/tms320dm320/uart-dm320.c b/firmware/target/arm/tms320dm320/uart-dm320.c index 6425b75960..5168cb11c6 100644 --- a/firmware/target/arm/tms320dm320/uart-dm320.c +++ b/firmware/target/arm/tms320dm320/uart-dm320.c | |||
@@ -24,7 +24,8 @@ | |||
24 | 24 | ||
25 | #define CONFIG_UART_BRSR 87 | 25 | #define CONFIG_UART_BRSR 87 |
26 | #define MAX_UART_BUFFER 31 | 26 | #define MAX_UART_BUFFER 31 |
27 | unsigned char uart1buffer[MAX_UART_BUFFER]; | 27 | unsigned char uart1buffer[MAX_UART_BUFFER], uart1_send_buffer_ring[512]; |
28 | int uart1_send_count=0,uart1_send_point=0; | ||
28 | int uart1read = 0, uart1write = 0, uart1count = 0; | 29 | int uart1read = 0, uart1write = 0, uart1count = 0; |
29 | 30 | ||
30 | /* | 31 | /* |