diff options
Diffstat (limited to 'firmware/target/arm/tms320dm320')
-rw-r--r-- | firmware/target/arm/tms320dm320/spi-dm320.c | 89 |
1 files changed, 49 insertions, 40 deletions
diff --git a/firmware/target/arm/tms320dm320/spi-dm320.c b/firmware/target/arm/tms320dm320/spi-dm320.c index 12ce0e0d5e..c2e774462a 100644 --- a/firmware/target/arm/tms320dm320/spi-dm320.c +++ b/firmware/target/arm/tms320dm320/spi-dm320.c | |||
@@ -39,21 +39,21 @@ struct SPI_info { | |||
39 | volatile unsigned short *setreg; | 39 | volatile unsigned short *setreg; |
40 | volatile unsigned short *clrreg; | 40 | volatile unsigned short *clrreg; |
41 | int bit; | 41 | int bit; |
42 | bool idle_low; | 42 | unsigned short spi_mode; |
43 | char divider; | 43 | bool clk_invert; |
44 | }; | 44 | }; |
45 | 45 | ||
46 | static struct SPI_info spi_targets[] = | 46 | static const struct SPI_info spi_targets[] = |
47 | { | 47 | { |
48 | #ifndef CREATIVE_ZVx | 48 | #ifndef CREATIVE_ZVx |
49 | [SPI_target_TSC2100] = { &IO_GIO_BITCLR1, &IO_GIO_BITSET1, | 49 | [SPI_target_TSC2100] = { &IO_GIO_BITCLR1, &IO_GIO_BITSET1, |
50 | GIO_TS_ENABLE, true, 0x07}, | 50 | GIO_TS_ENABLE, 0x260D, true}, |
51 | /* RTC seems to have timing problems if the CLK idles low */ | 51 | /* RTC seems to have timing problems if the CLK idles low */ |
52 | [SPI_target_RX5X348AB] = { &IO_GIO_BITSET0, &IO_GIO_BITCLR0, | 52 | [SPI_target_RX5X348AB] = { &IO_GIO_BITSET0, &IO_GIO_BITCLR0, |
53 | GIO_RTC_ENABLE, false, 0x3F}, | 53 | GIO_RTC_ENABLE, 0x263F, true}, |
54 | /* This appears to work properly idleing low, idling high is very glitchy */ | 54 | /* This appears to work properly idling low, idling high is very glitchy */ |
55 | [SPI_target_BACKLIGHT] = { &IO_GIO_BITCLR1, &IO_GIO_BITSET1, | 55 | [SPI_target_BACKLIGHT] = { &IO_GIO_BITCLR1, &IO_GIO_BITSET1, |
56 | GIO_BL_ENABLE, true, 0x07}, | 56 | GIO_BL_ENABLE, 0x2656, false}, |
57 | #else | 57 | #else |
58 | [SPI_target_LTV250QV] = { &IO_GIO_BITCLR2, &IO_GIO_BITSET2, | 58 | [SPI_target_LTV250QV] = { &IO_GIO_BITCLR2, &IO_GIO_BITSET2, |
59 | GIO_LCD_ENABLE, true, 0x07}, | 59 | GIO_LCD_ENABLE, true, 0x07}, |
@@ -61,7 +61,6 @@ static struct SPI_info spi_targets[] = | |||
61 | }; | 61 | }; |
62 | 62 | ||
63 | #define IO_SERIAL0_XMIT (0x100) | 63 | #define IO_SERIAL0_XMIT (0x100) |
64 | #define IO_SERIAL0_MODE_SCLK (1 << 10) | ||
65 | 64 | ||
66 | static void spi_disable_all_targets(void) | 65 | static void spi_disable_all_targets(void) |
67 | { | 66 | { |
@@ -77,41 +76,55 @@ int spi_block_transfer(enum SPI_target target, | |||
77 | uint8_t *rx_bytes, unsigned int rx_size) | 76 | uint8_t *rx_bytes, unsigned int rx_size) |
78 | { | 77 | { |
79 | mutex_lock(&spi_mtx); | 78 | mutex_lock(&spi_mtx); |
79 | |||
80 | /* Enable the clock */ | ||
81 | bitset16(&IO_CLK_MOD2, CLK_MOD2_SIF0); | ||
80 | 82 | ||
81 | IO_SERIAL0_MODE &= ~(1<<10); | 83 | if(spi_targets[target].clk_invert) |
82 | IO_SERIAL0_MODE |= (spi_targets[target].idle_low << 10); | 84 | { |
83 | 85 | bitset16(&IO_CLK_INV, (1 << 12)); | |
84 | IO_SERIAL0_MODE &= ~(0xFF); | 86 | } |
85 | IO_SERIAL0_MODE |= spi_targets[target].divider; | 87 | else |
86 | 88 | { | |
87 | /* Activate the slave select pin */ | 89 | bitclr16(&IO_CLK_INV, (1 << 12)); |
88 | if(tx_size) { | ||
89 | IO_SERIAL0_TX_ENABLE = 0x0001; | ||
90 | *spi_targets[target].setreg = spi_targets[target].bit; | ||
91 | } | 90 | } |
92 | 91 | ||
92 | IO_SERIAL0_MODE = spi_targets[target].spi_mode; | ||
93 | |||
94 | /* Activate the slave select pin */ | ||
95 | IO_SERIAL0_TX_ENABLE = 0x0001; | ||
96 | *spi_targets[target].setreg = spi_targets[target].bit; | ||
97 | |||
98 | while (IO_SERIAL0_RX_DATA & IO_SERIAL0_XMIT) {}; | ||
99 | |||
93 | while (tx_size--) | 100 | while (tx_size--) |
94 | { | 101 | { |
95 | /* Send one byte */ | 102 | /* Send one byte */ |
96 | IO_SERIAL0_TX_DATA = *tx_bytes++; | 103 | IO_SERIAL0_TX_DATA = (short)*tx_bytes++; |
97 | /* Wait until transfer finished */ | 104 | /* Wait until transfer finished */ |
98 | while (IO_SERIAL0_RX_DATA & IO_SERIAL0_XMIT); | 105 | while (IO_SERIAL0_RX_DATA & IO_SERIAL0_XMIT) {}; |
99 | } | 106 | } |
100 | 107 | ||
101 | while (rx_size--) | 108 | while (rx_size--) |
102 | { | 109 | { |
110 | unsigned short data; | ||
111 | |||
103 | /* Make the clock tick */ | 112 | /* Make the clock tick */ |
104 | IO_SERIAL0_TX_DATA = 0; | 113 | IO_SERIAL0_TX_DATA = 0; |
105 | 114 | ||
106 | /* Wait until transfer finished */ | 115 | /* Wait until transfer finished */ |
107 | unsigned short data; | 116 | while ((data = IO_SERIAL0_RX_DATA) & IO_SERIAL0_XMIT) {}; |
108 | while ((data = IO_SERIAL0_RX_DATA) & IO_SERIAL0_XMIT); | ||
109 | 117 | ||
110 | *rx_bytes++ = data & 0xff; | 118 | *rx_bytes++ = (unsigned char) data; |
111 | } | 119 | } |
112 | 120 | ||
113 | *spi_targets[target].clrreg = spi_targets[target].bit; | 121 | *spi_targets[target].clrreg = spi_targets[target].bit; |
114 | 122 | ||
123 | IO_SERIAL0_TX_ENABLE = 0x0000; | ||
124 | |||
125 | /* Disable the clock */ | ||
126 | bitclr16(&IO_CLK_MOD2, CLK_MOD2_SIF0); | ||
127 | |||
115 | mutex_unlock(&spi_mtx); | 128 | mutex_unlock(&spi_mtx); |
116 | return 0; | 129 | return 0; |
117 | } | 130 | } |
@@ -120,25 +133,21 @@ void spi_init(void) | |||
120 | { | 133 | { |
121 | mutex_init(&spi_mtx); | 134 | mutex_init(&spi_mtx); |
122 | 135 | ||
123 | IO_SERIAL0_MODE = 0x2200 | 0x3F; | 136 | /* Enable the clock */ |
124 | /* Enable TX */ | 137 | bitset16(&IO_CLK_MOD2, CLK_MOD2_SIF0); |
125 | IO_SERIAL0_TX_ENABLE = 0x0001; | ||
126 | #ifndef CREATIVE_ZVx | ||
127 | /* Setup SPI Chip Select Pins: | ||
128 | * 12 - RTC | ||
129 | * 18 - Touchscreen | ||
130 | * 29 - Backlight | ||
131 | */ | ||
132 | /* 12: output, non-inverted, no-irq, falling edge, no-chat, normal */ | ||
133 | dm320_set_io(12, false, false, false, false, false, 0x00); | ||
134 | 138 | ||
135 | /* 18: output, non-inverted, no-irq, falling edge, no-chat, normal */ | 139 | /* Disable transmitter */ |
136 | dm320_set_io(18, false, false, false, false, false, 0x00); | 140 | IO_SERIAL0_TX_ENABLE = 0x0000; |
137 | 141 | ||
138 | /* 29: output, non-inverted, no-irq, falling edge, no-chat, normal */ | 142 | IO_SERIAL0_MODE = 0x0230; |
139 | dm320_set_io(29, false, false, false, false, false, 0x00); | 143 | |
140 | #endif | 144 | /* Make sure the SPI clock is inverted */ |
145 | bitclr16(&IO_CLK_INV, ( 1 << 12 )); | ||
146 | |||
141 | /* make sure only one is ever enabled at a time */ | 147 | /* make sure only one is ever enabled at a time */ |
142 | spi_disable_all_targets(); | 148 | spi_disable_all_targets(); |
143 | 149 | ||
150 | /* Disable the clock */ | ||
151 | bitclr16(&IO_CLK_MOD2, CLK_MOD2_SIF0); | ||
144 | } | 152 | } |
153 | |||