summaryrefslogtreecommitdiff
path: root/firmware/target/arm/tms320dm320/system-dm320.c
diff options
context:
space:
mode:
Diffstat (limited to 'firmware/target/arm/tms320dm320/system-dm320.c')
-rw-r--r--firmware/target/arm/tms320dm320/system-dm320.c49
1 files changed, 24 insertions, 25 deletions
diff --git a/firmware/target/arm/tms320dm320/system-dm320.c b/firmware/target/arm/tms320dm320/system-dm320.c
index a918d99064..93cf3c51c4 100644
--- a/firmware/target/arm/tms320dm320/system-dm320.c
+++ b/firmware/target/arm/tms320dm320/system-dm320.c
@@ -100,7 +100,7 @@ default_interrupt(RESERVED);
100 * change the offset for the interrupt in the entry table. 100 * change the offset for the interrupt in the entry table.
101 */ 101 */
102 102
103static const unsigned short const irqpriority[] = 103static const unsigned short const irqpriority[] =
104{ 104{
105 IRQ_TIMER0,IRQ_TIMER1,IRQ_TIMER2,IRQ_TIMER3,IRQ_CCD_VD0,IRQ_CCD_VD1, 105 IRQ_TIMER0,IRQ_TIMER1,IRQ_TIMER2,IRQ_TIMER3,IRQ_CCD_VD0,IRQ_CCD_VD1,
106 IRQ_CCD_WEN,IRQ_VENC,IRQ_SERIAL0,IRQ_SERIAL1,IRQ_EXT_HOST,IRQ_DSPHINT, 106 IRQ_CCD_WEN,IRQ_VENC,IRQ_SERIAL0,IRQ_SERIAL1,IRQ_EXT_HOST,IRQ_DSPHINT,
@@ -165,7 +165,7 @@ void fiq_handler(void)
165void system_reboot(void) 165void system_reboot(void)
166{ 166{
167 /* Code taken from linux/include/asm-arm/arch-itdm320-20/system.h at NeuroSVN */ 167 /* Code taken from linux/include/asm-arm/arch-itdm320-20/system.h at NeuroSVN */
168 __asm__ __volatile__( 168 __asm__ __volatile__(
169 "mov ip, #0 \n" 169 "mov ip, #0 \n"
170 "mcr p15, 0, ip, c7, c7, 0 @ invalidate cache \n" 170 "mcr p15, 0, ip, c7, c7, 0 @ invalidate cache \n"
171 "mcr p15, 0, ip, c7, c10,4 @ drain WB \n" 171 "mcr p15, 0, ip, c7, c10,4 @ drain WB \n"
@@ -175,7 +175,7 @@ void system_reboot(void)
175 "bic ip, ip, #0x2100 @ ..v....s........ \n" 175 "bic ip, ip, #0x2100 @ ..v....s........ \n"
176 "mcr p15, 0, ip, c1, c0, 0 @ ctrl register \n" 176 "mcr p15, 0, ip, c1, c0, 0 @ ctrl register \n"
177 "mov ip, #0xFF000000 \n" 177 "mov ip, #0xFF000000 \n"
178 "orr pc, ip, #0xFF0000 @ ip = 0xFFFF0000 \n" 178 "orr pc, ip, #0xFF0000 @ ip = 0xFFFF0000 \n"
179 : 179 :
180 : 180 :
181 : "cc" 181 : "cc"
@@ -198,8 +198,8 @@ void system_exception_wait(void)
198 198
199void system_init(void) 199void system_init(void)
200{ 200{
201 unsigned int vector_addr; 201// unsigned int vector_addr;
202 /* Pin 33 is connected to a buzzer, for an annoying sound set 202 /* Pin 33 is connected to a buzzer, for an annoying sound set
203 * PWM0C == 0x3264 203 * PWM0C == 0x3264
204 * PWM0H == 0x1932 204 * PWM0H == 0x1932
205 * Function to 1 205 * Function to 1
@@ -228,8 +228,8 @@ void system_init(void)
228 IO_INTC_FISEL2 = 0; 228 IO_INTC_FISEL2 = 0;
229 229
230 /* Only initially needed clocks should be turned on */ 230 /* Only initially needed clocks should be turned on */
231 IO_CLK_MOD0 = CLK_MOD0_HPIB | CLK_MOD0_DSP | CLK_MOD0_SDRAMC | 231 IO_CLK_MOD0 = CLK_MOD0_HPIB | CLK_MOD0_DSP | CLK_MOD0_SDRAMC |
232 CLK_MOD0_EMIF | CLK_MOD0_INTC | CLK_MOD0_AIM | 232 CLK_MOD0_EMIF | CLK_MOD0_INTC | CLK_MOD0_AIM |
233 CLK_MOD0_AHB | CLK_MOD0_BUSC | CLK_MOD0_ARM; 233 CLK_MOD0_AHB | CLK_MOD0_BUSC | CLK_MOD0_ARM;
234 IO_CLK_MOD1 = CLK_MOD1_CPBUS; 234 IO_CLK_MOD1 = CLK_MOD1_CPBUS;
235 IO_CLK_MOD2 = CLK_MOD2_GIO; 235 IO_CLK_MOD2 = CLK_MOD2_GIO;
@@ -258,17 +258,17 @@ void system_init(void)
258 * IO_EMIF_CS4CTRL2 = 0x4220; 258 * IO_EMIF_CS4CTRL2 = 0x4220;
259 * 259 *
260 * More agressive numbers may be possible, but it depends on the clocking 260 * More agressive numbers may be possible, but it depends on the clocking
261 * setup. 261 * setup.
262 */ 262 */
263 IO_EMIF_CS4CTRL1 = 0x66AB; 263 IO_EMIF_CS4CTRL1 = 0x66AB;
264 IO_EMIF_CS4CTRL2 = 0x4220; 264 IO_EMIF_CS4CTRL2 = 0x4220;
265 265
266 /* 27 MHz input clock: 266 /* 27 MHz input clock:
267 * PLLA: 27 * 15 / 2 = 202.5 MHz 267 * PLLA: 27 * 15 / 2 = 202.5 MHz
268 * PLLB: 27 * 9 / 2 = 121.5 MHz (off: bit 12) 268 * PLLB: 27 * 9 / 2 = 121.5 MHz (off: bit 12)
269 */ 269 */
270 IO_CLK_PLLA = (14 << 4) | 1; 270 IO_CLK_PLLA = (14 << 4) | 1;
271 IO_CLK_PLLB = ( 1 << 12) | ( 8 << 4) | 1; 271 IO_CLK_PLLB = ( 1 << 12) | ( 8 << 4) | 1;
272 272
273 /* Set the slow and fast clock speeds used for boosting 273 /* Set the slow and fast clock speeds used for boosting
274 * Slow Setup: 274 * Slow Setup:
@@ -282,31 +282,31 @@ void system_init(void)
282 clock_arm_fast = (1 << 8) | 0; 282 clock_arm_fast = (1 << 8) | 0;
283 283
284 IO_CLK_DIV0 = clock_arm_slow; 284 IO_CLK_DIV0 = clock_arm_slow;
285 285
286 /* SDRAM div= 2 ( 101.25 MHz ) 286 /* SDRAM div= 2 ( 101.25 MHz )
287 * AXL div = 1 ( 202.5 MHz ) 287 * AXL div = 1 ( 202.5 MHz )
288 */ 288 */
289 IO_CLK_DIV1 = (0 << 8) | 1; 289 IO_CLK_DIV1 = (0 << 8) | 1;
290 290
291 /* MS div = 15 ( 13.5 MHz ) 291 /* MS div = 15 ( 13.5 MHz )
292 * DSP div = 4 ( 50.625 MHz - could be double, but this saves power) 292 * DSP div = 4 ( 50.625 MHz - could be double, but this saves power)
293 */ 293 */
294 IO_CLK_DIV2 = (3 << 8) | 14; 294 IO_CLK_DIV2 = (3 << 8) | 14;
295 295
296 /* MMC div = 256 ( slow ) 296 /* MMC div = 256 ( slow )
297 * VENC div = 32 ( 843.75 KHz ) 297 * VENC div = 32 ( 843.75 KHz )
298 */ 298 */
299 IO_CLK_DIV3 = (31 << 8) | 255; 299 IO_CLK_DIV3 = (31 << 8) | 255;
300 300
301 /* I2C div = 1 ( 48 MHz if M48XI is running ) 301 /* I2C div = 1 ( 48 MHz if M48XI is running )
302 * VLNQ div = 32 302 * VLNQ div = 32
303 */ 303 */
304 IO_CLK_DIV4 = (31 << 8) | 0; 304 IO_CLK_DIV4 = (31 << 8) | 0;
305 305
306 /* Feed everything from PLLA */ 306 /* Feed everything from PLLA */
307 IO_CLK_SEL0=0x007E; 307 IO_CLK_SEL0=0x007E;
308 IO_CLK_SEL1=0x1000; 308 IO_CLK_SEL1=0x1000;
309 IO_CLK_SEL2=0x0000; 309 IO_CLK_SEL2=0x0000;
310 } 310 }
311 else 311 else
312#endif 312#endif
@@ -335,16 +335,16 @@ void system_init(void)
335 /* IRQENTRY only reflects enabled interrupts */ 335 /* IRQENTRY only reflects enabled interrupts */
336 IO_INTC_RAW = 0; 336 IO_INTC_RAW = 0;
337 337
338 vector_addr = (unsigned int) irqvector; 338 // vector_addr = (unsigned int) irqvector;
339 IO_INTC_ENTRY_TBA0 = 0;//(short) vector_addr & ~0x000F; 339 IO_INTC_ENTRY_TBA0 = 0;//(short) vector_addr & ~0x000F;
340 IO_INTC_ENTRY_TBA1 = 0;//(short) (vector_addr >> 16); 340 IO_INTC_ENTRY_TBA1 = 0;//(short) (vector_addr >> 16);
341 341
342 int i; 342 int i;
343 /* Set interrupt priorities to predefined values */ 343 /* Set interrupt priorities to predefined values */
344 for(i = 0; i < 23; i++) 344 for(i = 0; i < 23; i++)
345 DM320_REG(0x0540+i*2) = ((irqpriority[i*2+1] & 0x3F) << 8) | 345 DM320_REG(0x0540+i*2) = ((irqpriority[i*2+1] & 0x3F) << 8) |
346 (irqpriority[i*2] & 0x3F); /* IO_INTC_PRIORITYx */ 346 (irqpriority[i*2] & 0x3F); /* IO_INTC_PRIORITYx */
347 347
348 /* Turn off all timers */ 348 /* Turn off all timers */
349 IO_TIMER0_TMMD = CONFIG_TIMER0_TMMD_STOP; 349 IO_TIMER0_TMMD = CONFIG_TIMER0_TMMD_STOP;
350 IO_TIMER1_TMMD = CONFIG_TIMER1_TMMD_STOP; 350 IO_TIMER1_TMMD = CONFIG_TIMER1_TMMD_STOP;
@@ -410,12 +410,12 @@ void set_cpu_frequency(long frequency)
410 return; 410 return;
411 } 411 }
412 412
413 if (frequency == CPUFREQ_MAX) 413 if (frequency == CPUFREQ_MAX)
414 { 414 {
415 IO_CLK_DIV0 = clock_arm_fast; 415 IO_CLK_DIV0 = clock_arm_fast;
416 FREQ = CPUFREQ_MAX; 416 FREQ = CPUFREQ_MAX;
417 } 417 }
418 else 418 else
419 { 419 {
420 IO_CLK_DIV0 = clock_arm_slow; 420 IO_CLK_DIV0 = clock_arm_slow;
421 FREQ = CPUFREQ_NORMAL; 421 FREQ = CPUFREQ_NORMAL;
@@ -477,7 +477,7 @@ void udelay(int usec) {
477 * can lead to lockup. 477 * can lead to lockup.
478 * Interrupt status bit check below is used to prevent this lockup. 478 * Interrupt status bit check below is used to prevent this lockup.
479 */ 479 */
480 480
481 if (stop < count) 481 if (stop < count)
482 { 482 {
483 /* udelay will end after counter reset (tick) */ 483 /* udelay will end after counter reset (tick) */
@@ -503,4 +503,3 @@ void system_prepare_fw_start(void)
503 IO_INTC_EINT2 = 0; 503 IO_INTC_EINT2 = 0;
504} 504}
505#endif 505#endif
506