diff options
Diffstat (limited to 'firmware/target/arm/tms320dm320/dsp/vectors.asm')
-rw-r--r-- | firmware/target/arm/tms320dm320/dsp/vectors.asm | 143 |
1 files changed, 143 insertions, 0 deletions
diff --git a/firmware/target/arm/tms320dm320/dsp/vectors.asm b/firmware/target/arm/tms320dm320/dsp/vectors.asm new file mode 100644 index 0000000000..1551d996fc --- /dev/null +++ b/firmware/target/arm/tms320dm320/dsp/vectors.asm | |||
@@ -0,0 +1,143 @@ | |||
1 | ;* Copyright (c) 2007, C.P.R. Baaij | ||
2 | ;* All rights reserved. | ||
3 | ;* | ||
4 | ;* Redistribution and use in source and binary forms, with or without | ||
5 | ;* modification, are permitted provided that the following conditions are met: | ||
6 | ;* * Redistributions of source code must retain the above copyright | ||
7 | ;* notice, this list of conditions and the following disclaimer. | ||
8 | ;* * Redistributions in binary form must reproduce the above copyright | ||
9 | ;* notice, this list of conditions and the following disclaimer in the | ||
10 | ;* documentation and/or other materials provided with the distribution. | ||
11 | ;* | ||
12 | ;* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR | ||
13 | ;* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | ||
14 | ;* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. | ||
15 | ;* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
16 | ;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
17 | ;* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | ||
18 | ;* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | ||
19 | ;* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
20 | ;* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
21 | ;* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
22 | |||
23 | ;*-----------------------------------------------------------------------------* | ||
24 | ;* Interrupt Vectors * | ||
25 | ;*-----------------------------------------------------------------------------* | ||
26 | .mmregs | ||
27 | |||
28 | ; External Functions | ||
29 | .global _handle_int0 | ||
30 | .global _c_int00 | ||
31 | .global _handle_dma0 | ||
32 | .global _handle_dmac | ||
33 | |||
34 | .sect ".vectors" | ||
35 | ; Reset Interrupt | ||
36 | RS_V: BD _c_int00 | ||
37 | NOP | ||
38 | NOP | ||
39 | |||
40 | ; Non-Maskable Interrupt | ||
41 | NMI_V: RETE | ||
42 | NOP | ||
43 | NOP | ||
44 | NOP | ||
45 | |||
46 | ; Software Interrupts | ||
47 | SINt17_V: .space 4*16 | ||
48 | SINt18_V: .space 4*16 | ||
49 | SINt19_V: .space 4*16 | ||
50 | SINt20_V: .space 4*16 | ||
51 | SINt21_V: .space 4*16 | ||
52 | SINt22_V: .space 4*16 | ||
53 | SINt23_V: .space 4*16 | ||
54 | SINt24_V: .space 4*16 | ||
55 | SINt25_V: .space 4*16 | ||
56 | SINt26_V: .space 4*16 | ||
57 | SINt27_V: .space 4*16 | ||
58 | SINt28_V: .space 4*16 | ||
59 | SINt29_V: .space 4*16 | ||
60 | SINt30_V: .space 4*16 | ||
61 | ; INT0 - ARM Interrupting DSP via HPIB | ||
62 | INT0_V: BD _handle_int0 | ||
63 | NOP | ||
64 | NOP | ||
65 | ; INT1 - Interrupt is generated based on the settings of DSP_SYNC_STATE and | ||
66 | ; DSP_SYNC_MASK register of the coprocessor subsystem or when DSPINT1 bit in | ||
67 | ; CP_INTC is set. | ||
68 | INT1_V: RETE | ||
69 | NOP | ||
70 | NOP | ||
71 | NOP | ||
72 | ; INT2 - Interrupt is generated when DSPINT2 bit in CP_INTC register of the | ||
73 | ; coprocessor subsystem is set. | ||
74 | INT2_V: RETE | ||
75 | NOP | ||
76 | NOP | ||
77 | NOP | ||
78 | ; Timer Interrupt | ||
79 | TINT_V: RETE | ||
80 | NOP | ||
81 | NOP | ||
82 | NOP | ||
83 | ; McBSP0 receive interrupt | ||
84 | BRINT0_V: RETE | ||
85 | NOP | ||
86 | NOP | ||
87 | NOP | ||
88 | ; McBSP0 transmit interrupt | ||
89 | BXINT0_V: RETE | ||
90 | NOP | ||
91 | NOP | ||
92 | NOP | ||
93 | ; DMA Channel-0 interrupt | ||
94 | DMAC0_V: BD _handle_dma0 | ||
95 | NOP | ||
96 | NOP | ||
97 | ; DMA Channel-1 interrupt | ||
98 | DMAC1_V: RETE | ||
99 | NOP | ||
100 | NOP | ||
101 | NOP | ||
102 | ; INT3 - Interrupt is generated when DSPINT3 bit in CP_INTC register of the | ||
103 | ; coprocessor subsystem is set or on write of any value to BRKPT_TRG | ||
104 | INT3_V: RETE | ||
105 | NOP | ||
106 | NOP | ||
107 | NOP | ||
108 | ; HPIB HINT to DSP | ||
109 | HINT_V: RETE | ||
110 | NOP | ||
111 | NOP | ||
112 | NOP | ||
113 | ; BRINT1/DMAC2 McBSP1 receive interrupt | ||
114 | BRINT1_V: RETE | ||
115 | NOP | ||
116 | NOP | ||
117 | NOP | ||
118 | ; BXINT1/DMAC3 McBSP1 transmit interrupt | ||
119 | BXINT1_V: RETE | ||
120 | NOP | ||
121 | NOP | ||
122 | NOP | ||
123 | ; DMA Channel-4 interrupt | ||
124 | DMAC4_V: RETE | ||
125 | NOP | ||
126 | NOP | ||
127 | NOP | ||
128 | ; DMA Channel-5 interrupt | ||
129 | DMAC5_V: RETE | ||
130 | NOP | ||
131 | NOP | ||
132 | NOP | ||
133 | ; HPIB DMAC interrupt | ||
134 | HPIB_DMA_V: BD _handle_dmac | ||
135 | NOP | ||
136 | NOP | ||
137 | |||
138 | ; EHIF interrupt to DSP | ||
139 | EHIV_V: RETE | ||
140 | NOP | ||
141 | NOP | ||
142 | NOP | ||
143 | .end | ||