diff options
Diffstat (limited to 'firmware/target/arm/tms320dm320/dsp/aic23.c')
-rw-r--r-- | firmware/target/arm/tms320dm320/dsp/aic23.c | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/firmware/target/arm/tms320dm320/dsp/aic23.c b/firmware/target/arm/tms320dm320/dsp/aic23.c new file mode 100644 index 0000000000..e6eb8b4c29 --- /dev/null +++ b/firmware/target/arm/tms320dm320/dsp/aic23.c | |||
@@ -0,0 +1,58 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Maurus Cuelenaere | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | |||
20 | #include "audio.h" | ||
21 | #include "registers.h" | ||
22 | |||
23 | /* based on http://archopen.svn.sourceforge.net/viewvc/archopen/ArchOpen/trunk/libdsp/aic23.c?revision=213&view=markup */ | ||
24 | void audiohw_init(void) | ||
25 | { | ||
26 | /* port config */ | ||
27 | #if 0 | ||
28 | SPCR10 = 0; /* DLB = 0 ** RJUST = 0 ** CLKSTP = 0 ** DXENA = 0 ** ABIS = 0 ** RINTM = 0 ** RSYNCER = 0 ** RFULL = 0 ** RRDY = 0 ** RRST = 0 */ | ||
29 | SPCR20 = (1 << 9); /* FREE = 1 ** SOFT = 0 ** FRST = 0 ** GRST = 0 ** XINTM = 0 ** XSYNCER = 0 ** XEMPTY = 0 ** XRDY = 0 ** XRST = 0 */ | ||
30 | RCR10 = (1 << 8) | (2 << 5); /* RFRLEN1 = 1 ** RWDLEN1 = 2 */ | ||
31 | RCR20 = 0; /* RPHASE = 0 ** RFRLEN2 = 0 ** RWDLEN2 = 0 ** RCOMPAND = 0 ** RFIG = 0 ** RDATDLY = 0 */ | ||
32 | XCR10 = (1 << 8) | (2 << 5); /* XFRLEN1 = 1 ** XWDLEN1 = 2 */ | ||
33 | XCR20 = 0; /* XPHASE = 0 ** XFRLEN2 = 0 ** XWDLEN2 = 0 ** XCOMPAND = 0 ** XFIG = 0 ** XDATDLY = 0 */ | ||
34 | SRGR10 = 0; /* FWID = 0 ** CLKGDV = 0 */ | ||
35 | SRGR20 = 0; /* FREE = 0 ** CLKSP = 0 ** CLKSM = 0 ** FSGM = 0 ** FPER = 0 */ | ||
36 | PCR0 = (1 << 1) | 1; /* IDLEEN = 0 ** XIOEN = 0 ** RIOEN = 0 ** FSXM = 0 ** FSRM = 0 ** SCLKME = 0 ** CLKSSTAT = 0 ** DXSTAT = 0 ** DRSTAT = 0 ** CLKXM = 0 ** CLKRM = 0 ** FSXP = 0 ** FSRP = 0 ** CLKXP = 1 ** CLKRP = 1 */ | ||
37 | #else | ||
38 | SPCR10 = 0; | ||
39 | SPCR20 = 0x0200; /* SPCR : free running mode */ | ||
40 | |||
41 | RCR10 = 0x00A0; | ||
42 | RCR20 = 0x00A1; /* RCR : 32 bit receive data length */ | ||
43 | |||
44 | XCR10 = 0x00A0; | ||
45 | XCR20 = 0x00A0; /* XCR : 32 bit transmit data length */ | ||
46 | |||
47 | SRGR10 = 0; | ||
48 | SRGR20 = 0x3000; /* SRGR 1 & 2 */ | ||
49 | |||
50 | PCR0 = 0x000E - 8; /* PCR : FSX, FSR active low, external FS/CLK source */ | ||
51 | #endif | ||
52 | } | ||
53 | |||
54 | void audiohw_postinit(void) | ||
55 | { | ||
56 | /* Trigger first XEVT0 */ | ||
57 | SPCR20 |= 1; | ||
58 | } | ||