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Diffstat (limited to 'firmware/target/arm/s5l8702/uc8702.h')
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diff --git a/firmware/target/arm/s5l8702/uc8702.h b/firmware/target/arm/s5l8702/uc8702.h deleted file mode 100644 index 36e4f8faa4..0000000000 --- a/firmware/target/arm/s5l8702/uc8702.h +++ /dev/null | |||
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1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2014 by Cástor Muñoz | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #ifndef __UC8702_H__ | ||
22 | #define __UC8702_H__ | ||
23 | |||
24 | #include <stdint.h> | ||
25 | #include <stdbool.h> | ||
26 | |||
27 | |||
28 | /* s5l8702 UART controller (UC8702): | ||
29 | * | ||
30 | * This UART is similar to the UART included in s5l8700 (see also | ||
31 | * s3c2416 and s3c6400 datasheets), UC8702 adds fine tunning for | ||
32 | * Tx/Rx bitrate and autobauding. | ||
33 | */ | ||
34 | |||
35 | /*#define UC8702_DEBUG*/ | ||
36 | |||
37 | /* | ||
38 | * uc8702 HW definitions | ||
39 | */ | ||
40 | #define UART_PORT_MAX 4 | ||
41 | #define UART_FIFO_SIZE 16 | ||
42 | |||
43 | #define UART_PORT_BASE(b,i) ((b) + 0x4000 * (i)) | ||
44 | |||
45 | /* | ||
46 | * controller registers | ||
47 | */ | ||
48 | #define REG32_PTR_T volatile uint32_t * | ||
49 | |||
50 | #define ULCON(ba) (*((REG32_PTR_T)((ba) + 0x00))) /* line control */ | ||
51 | #define UCON(ba) (*((REG32_PTR_T)((ba) + 0x04))) /* control */ | ||
52 | #define UFCON(ba) (*((REG32_PTR_T)((ba) + 0x08))) /* FIFO control */ | ||
53 | #define UMCON(ba) (*((REG32_PTR_T)((ba) + 0x0C))) /* modem control */ | ||
54 | #define UTRSTAT(ba) (*((REG32_PTR_T)((ba) + 0x10))) /* Tx/Rx status */ | ||
55 | #define UERSTAT(ba) (*((REG32_PTR_T)((ba) + 0x14))) /* Rx error status */ | ||
56 | #define UFSTAT(ba) (*((REG32_PTR_T)((ba) + 0x18))) /* FIFO status */ | ||
57 | #define UMSTAT(ba) (*((REG32_PTR_T)((ba) + 0x1C))) /* modem status */ | ||
58 | #define UTXH(ba) (*((REG32_PTR_T)((ba) + 0x20))) /* transmission hold */ | ||
59 | #define URXH(ba) (*((REG32_PTR_T)((ba) + 0x24))) /* receive buffer */ | ||
60 | #define UBRDIV(ba) (*((REG32_PTR_T)((ba) + 0x28))) /* baud rate divisor */ | ||
61 | #define UABRCNT(ba) (*((REG32_PTR_T)((ba) + 0x2c))) /* autobaud counter */ | ||
62 | #define UABRSTAT(ba) (*((REG32_PTR_T)((ba) + 0x30))) /* autobaud status */ | ||
63 | #define UBRCONTX(ba) (*((REG32_PTR_T)((ba) + 0x34))) /* Tx frame config */ | ||
64 | #define UBRCONRX(ba) (*((REG32_PTR_T)((ba) + 0x38))) /* Rx frame config */ | ||
65 | |||
66 | /* ULCON register */ | ||
67 | #define ULCON_DATA_BITS_MASK 0x3 | ||
68 | #define ULCON_DATA_BITS_POS 0 | ||
69 | #define ULCON_DATA_BITS_5 0 | ||
70 | #define ULCON_DATA_BITS_6 1 | ||
71 | #define ULCON_DATA_BITS_7 2 | ||
72 | #define ULCON_DATA_BITS_8 3 | ||
73 | |||
74 | #define ULCON_STOP_BITS_MASK 0x1 | ||
75 | #define ULCON_STOP_BITS_POS 2 | ||
76 | #define ULCON_STOP_BITS_1 0 | ||
77 | #define ULCON_STOP_BITS_2 1 | ||
78 | |||
79 | #define ULCON_PARITY_MASK 0x7 | ||
80 | #define ULCON_PARITY_POS 3 | ||
81 | #define ULCON_PARITY_NONE 0 | ||
82 | #define ULCON_PARITY_ODD 4 | ||
83 | #define ULCON_PARITY_EVEN 5 | ||
84 | #define ULCON_PARITY_FORCE_1 6 | ||
85 | #define ULCON_PARITY_FORCE_0 7 | ||
86 | |||
87 | #define ULCON_INFRARED_EN_BIT (1 << 6) | ||
88 | |||
89 | /* UCON register */ | ||
90 | #define UCON_RX_MODE_MASK 0x3 | ||
91 | #define UCON_RX_MODE_POS 0 | ||
92 | |||
93 | #define UCON_TX_MODE_MASK 0x3 | ||
94 | #define UCON_TX_MODE_POS 2 | ||
95 | |||
96 | #define UCON_MODE_DISABLED 0 | ||
97 | #define UCON_MODE_INTREQ 1 /* INT request or polling mode */ | ||
98 | #define UCON_MODE_UNDEFINED 2 /* Not defined, DMAREQ signal 1 ??? */ | ||
99 | #define UCON_MODE_DMAREQ 3 /* DMA request (signal 0) */ | ||
100 | |||
101 | #define UCON_SEND_BREAK_BIT (1 << 4) | ||
102 | #define UCON_LOOPBACK_BIT (1 << 5) | ||
103 | #define UCON_RX_TOUT_EN_BIT (1 << 7) /* Rx timeout enable */ | ||
104 | |||
105 | #define UCON_CLKSEL_MASK 0x1 | ||
106 | #define UCON_CLKSEL_POS 10 | ||
107 | #define UCON_CLKSEL_PCLK 0 /* internal */ | ||
108 | #define UCON_CLKSEL_ECLK 1 /* external */ | ||
109 | |||
110 | #define UCON_RX_TOUT_INT_BIT (1 << 11) /* Rx timeout INT enable */ | ||
111 | #define UCON_RX_INT_BIT (1 << 12) /* Rx INT enable */ | ||
112 | #define UCON_TX_INT_BIT (1 << 13) /* Tx INT enable */ | ||
113 | #define UCON_ERR_INT_BIT (1 << 14) /* Rx error INT enable */ | ||
114 | #define UCON_MODEM_INT_BIT (1 << 15) /* modem INT enable (TBC) */ | ||
115 | #define UCON_AUTOBR_INT_BIT (1 << 16) /* autobauding INT enable */ | ||
116 | #define UCON_AUTOBR_START_BIT (1 << 17) /* autobauding start/stop */ | ||
117 | |||
118 | /* UFCON register */ | ||
119 | #define UFCON_FIFO_ENABLE_BIT (1 << 0) | ||
120 | #define UFCON_RX_FIFO_RST_BIT (1 << 1) | ||
121 | #define UFCON_TX_FIFO_RST_BIT (1 << 2) | ||
122 | |||
123 | #define UFCON_RX_FIFO_TRG_MASK 0x3 | ||
124 | #define UFCON_RX_FIFO_TRG_POS 4 | ||
125 | #define UFCON_RX_FIFO_TRG_4 0 | ||
126 | #define UFCON_RX_FIFO_TRG_8 1 | ||
127 | #define UFCON_RX_FIFO_TRG_12 2 | ||
128 | #define UFCON_RX_FIFO_TRG_16 3 | ||
129 | |||
130 | #define UFCON_TX_FIFO_TRG_MASK 0x3 | ||
131 | #define UFCON_TX_FIFO_TRG_POS 6 | ||
132 | #define UFCON_TX_FIFO_TRG_EMPTY 0 | ||
133 | #define UFCON_TX_FIFO_TRG_4 1 | ||
134 | #define UFCON_TX_FIFO_TRG_8 2 | ||
135 | #define UFCON_TX_FIFO_TRG_12 3 | ||
136 | |||
137 | /* UMCON register */ | ||
138 | #define UMCON_RTS_BIT (1 << 0) | ||
139 | #define UMCON_AUTO_FLOW_CTRL_BIT (1 << 4) | ||
140 | |||
141 | /* UTRSTAT register */ | ||
142 | #define UTRSTAT_RXBUF_RDY_BIT (1 << 0) | ||
143 | #define UTRSTAT_TXBUF_EMPTY_BIT (1 << 1) | ||
144 | #define UTRSTAT_TX_EMPTY_BIT (1 << 2) | ||
145 | #define UTRSTAT_RX_TOUT_INT_BIT (1 << 3) /* Rx timeout INT status */ | ||
146 | #define UTRSTAT_RX_INT_BIT (1 << 4) | ||
147 | #define UTRSTAT_TX_INT_BIT (1 << 5) | ||
148 | #define UTRSTAT_ERR_INT_BIT (1 << 6) | ||
149 | #define UTRSTAT_MODEM_INT_BIT (1 << 7) /* modem INT status (TBC) */ | ||
150 | #define UTRSTAT_AUTOBR_INT_BIT (1 << 8) /* autobauding INT status */ | ||
151 | |||
152 | /* UERSTAT register */ | ||
153 | #define UERSTAT_OVERRUN_BIT (1 << 0) | ||
154 | #define UERSTAT_PARITY_ERR_BIT (1 << 1) | ||
155 | #define UERSTAT_FRAME_ERR_BIT (1 << 2) | ||
156 | #define UERSTAT_BREAK_DETECT_BIT (1 << 3) | ||
157 | |||
158 | /* UFSTAT register */ | ||
159 | #define UFSTAT_RX_FIFO_CNT_MASK 0xf | ||
160 | #define UFSTAT_RX_FIFO_CNT_POS 0 | ||
161 | |||
162 | #define UFSTAT_TX_FIFO_CNT_MASK 0xf | ||
163 | #define UFSTAT_TX_FIFO_CNT_POS 4 | ||
164 | |||
165 | #define UFSTAT_RX_FIFO_FULL_BIT (1 << 8) | ||
166 | #define UFSTAT_TX_FIFO_FULL_BIT (1 << 9) | ||
167 | #define UFSTAT_RX_FIFO_ERR_BIT (1 << 10) /* clears when reading UERSTAT | ||
168 | for the last pending error */ | ||
169 | /* UMSTAT register */ | ||
170 | #define UMSTAT_CTS_ACTIVE_BIT (1 << 0) | ||
171 | #define UMSTAT_CTS_DELTA_BIT (1 << 4) | ||
172 | |||
173 | /* Bitrate: | ||
174 | * | ||
175 | * Master UCLK clock is divided by 16 to serialize data, UBRDIV is | ||
176 | * used to configure nominal bit width, NBW = (UBRDIV+1)*16 in UCLK | ||
177 | * clock ticks. | ||
178 | * | ||
179 | * Fine tuning works shrining/expanding each individual bit of each | ||
180 | * frame. Each bit width can be incremented/decremented by 1/16 of | ||
181 | * nominal bit width, it seems UCLK is divided by 17 for expanded | ||
182 | * bits and divided by 15 for compressed bits. A whole frame of N | ||
183 | * bits can be shrined or expanded up to (NBW * N / 16) UCLK clock | ||
184 | * ticks (in 1/16 steps). | ||
185 | */ | ||
186 | /* UBRCONx register */ | ||
187 | #define UC_FRAME_MAX_LEN 12 /* 1 start + 8 data + 1 par + 2 stop */ | ||
188 | #define UBRCON_JITTER_MASK 0x3 | ||
189 | #define UBRCON_JITTER_POS(bit) ((bit) << 1) /* 0..UC_FRAME_MAX_LEN-1 */ | ||
190 | |||
191 | #define UBRCON_JITTER_NONE 0 /* no jitter for this bit */ | ||
192 | #define UBRCON_JITTER_INC 1 /* increment 1/16 bit width */ | ||
193 | #define UBRCON_JITTER_UNUSED 2 /* does nothing */ | ||
194 | #define UBRCON_JITTER_DEC 3 /* decremet 1/16 bit width */ | ||
195 | |||
196 | /* Autobauding: | ||
197 | * | ||
198 | * Initial UABRSTAT is NOT_INIT, it goes to READY when either of | ||
199 | * UCON_AUTOBR bits are enabled for the first time. | ||
200 | * | ||
201 | * Interrupts are enabled/disabled using UCON_AUTOBR_INT_BIT and | ||
202 | * checked using UTRSTAT_AUTOBR_INT_BIT, writing this bit cleans the | ||
203 | * interrupt. | ||
204 | * | ||
205 | * When UCON_AUTOBR_START_BIT is enabled, autobauding starts and the | ||
206 | * hardware waits for a low pulse on RX line. | ||
207 | * | ||
208 | * Once autobauding is started, when a falling edge is detected on | ||
209 | * the RX line, UABRSTAT changes to COUNTING status, an internal | ||
210 | * counter starts incrementing at UCLK clock frequency. During | ||
211 | * COUNTING state, UABRCNT reads as the value of the previous ABR | ||
212 | * count, not the value of the current internal count. | ||
213 | * | ||
214 | * Count finish when a rising edge is detected on the line, at this | ||
215 | * moment internal counter stops and it can be read using UABRCNT | ||
216 | * register, UABRSTAT goes to READY, AUTOBR_START_BIT is disabled, | ||
217 | * and an interrupt is raised if UCON_AUTOBR_INT_BIT is enabled. | ||
218 | */ | ||
219 | /* UABRSTAT register */ | ||
220 | #define UABRSTAT_STATUS_MASK 0x3 | ||
221 | #define UABRSTAT_STATUS_POS 0 | ||
222 | |||
223 | #define UABRSTAT_STATUS_NOT_INIT 0 /* initial status */ | ||
224 | #define UABRSTAT_STATUS_READY 1 /* machine is ready */ | ||
225 | #define UABRSTAT_STATUS_COUNTING 2 /* count in progress */ | ||
226 | |||
227 | |||
228 | /* | ||
229 | * structs | ||
230 | */ | ||
231 | struct uartc | ||
232 | { | ||
233 | /* static configuration */ | ||
234 | const uint32_t baddr; | ||
235 | /* private */ | ||
236 | struct uartc_port *port_l[UART_PORT_MAX]; | ||
237 | }; | ||
238 | |||
239 | struct uartc_port | ||
240 | { | ||
241 | /* static configuration */ | ||
242 | struct uartc * const uartc; | ||
243 | const uint8_t id; /* port number */ | ||
244 | const uint8_t rx_trg; /* UFCON_RX_FIFO_TRG_xxx */ | ||
245 | const uint8_t tx_trg; /* UFCON_TX_FIFO_TRG_xxx */ | ||
246 | const uint8_t clksel; /* UFCON_CLKSEL_xxx */ | ||
247 | const uint32_t clkhz; /* UCLK (PCLK or ECLK) frequency */ | ||
248 | void (* const tx_cb) (int len); /* ISRs */ | ||
249 | void (* const rx_cb) (int len, char *data, char *err, uint32_t abr_cnt); | ||
250 | |||
251 | /* private */ | ||
252 | uint32_t baddr; | ||
253 | uint32_t utrstat_int_mask; | ||
254 | bool abr_aborted; | ||
255 | uint8_t rx_data[UART_FIFO_SIZE]; /* data buffer for rx_cb */ | ||
256 | uint8_t rx_err[UART_FIFO_SIZE]; /* error buffer for rx_cb */ | ||
257 | |||
258 | #ifdef UC8702_DEBUG | ||
259 | uint32_t n_tx_bytes; | ||
260 | uint32_t n_rx_bytes; | ||
261 | uint32_t n_ovr_err; | ||
262 | uint32_t n_parity_err; | ||
263 | uint32_t n_frame_err; | ||
264 | uint32_t n_break_detect; | ||
265 | uint32_t n_abnormal0; | ||
266 | uint32_t n_abnormal1; | ||
267 | #endif | ||
268 | }; | ||
269 | |||
270 | |||
271 | /* | ||
272 | * uc8702 low level API | ||
273 | */ | ||
274 | |||
275 | /* Initialization */ | ||
276 | void uartc_open(struct uartc* uartc); | ||
277 | void uartc_close(struct uartc* uartc); | ||
278 | void uartc_port_open(struct uartc_port *port); | ||
279 | void uartc_port_close(struct uartc_port *port); | ||
280 | void uartc_port_rx_onoff(struct uartc_port *port, bool onoff); | ||
281 | void uartc_port_tx_onoff(struct uartc_port *port, bool onoff); | ||
282 | |||
283 | /* Configuration */ | ||
284 | void uartc_port_config(struct uartc_port *port, unsigned int speed, | ||
285 | uint8_t data_bits, uint8_t parity, uint8_t stop_bits); | ||
286 | void uartc_port_set_bitrate(struct uartc_port *port, unsigned int speed); | ||
287 | void uartc_port_set_rx_mode(struct uartc_port *port, uint32_t mode); | ||
288 | void uartc_port_set_tx_mode(struct uartc_port *port, uint32_t mode); | ||
289 | |||
290 | /* Transmit */ | ||
291 | bool uartc_port_tx_ready(struct uartc_port *port); | ||
292 | void uartc_port_tx_byte(struct uartc_port *port, uint8_t ch); | ||
293 | void uartc_port_send_byte(struct uartc_port *port, uint8_t ch); | ||
294 | |||
295 | /* Receive */ | ||
296 | bool uartc_port_rx_ready(struct uartc_port *port); | ||
297 | uint8_t uartc_port_rx_byte(struct uartc_port *port); | ||
298 | uint8_t uartc_port_read_byte(struct uartc_port *port); | ||
299 | |||
300 | /* Autobauding */ | ||
301 | void uartc_port_abr_start(struct uartc_port *port); | ||
302 | void uartc_port_abr_stop(struct uartc_port *port); | ||
303 | |||
304 | /* ISR */ | ||
305 | void uartc_callback(struct uartc *uartc, int dev); | ||
306 | |||
307 | #ifdef UC8702_DEBUG | ||
308 | enum { | ||
309 | ABR_INFO_ST_IDLE, | ||
310 | ABR_INFO_ST_LAUNCHED, | ||
311 | ABR_INFO_ST_COUNTING, | ||
312 | ABR_INFO_ST_ABNORMAL | ||
313 | }; | ||
314 | |||
315 | void uartc_port_get_line_info(struct uartc_port *port, | ||
316 | int *tx_status, int *rx_status, | ||
317 | int *tx_speed, int *rx_speed, char *line_cfg); | ||
318 | |||
319 | int uartc_port_get_abr_info(struct uartc_port *port, unsigned int *abr_cnt); | ||
320 | #endif | ||
321 | #endif /* __UC8702_H__ */ | ||