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-rw-r--r--firmware/target/arm/s5l8702/uc8702.c446
1 files changed, 0 insertions, 446 deletions
diff --git a/firmware/target/arm/s5l8702/uc8702.c b/firmware/target/arm/s5l8702/uc8702.c
deleted file mode 100644
index 91c4a3c9e6..0000000000
--- a/firmware/target/arm/s5l8702/uc8702.c
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@@ -1,446 +0,0 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2014 by Cástor Muñoz
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21#include <stdint.h>
22#include "kernel.h"
23#include "uc8702.h"
24
25
26/*
27 * s5l8702 UART controller (UC8702)
28 */
29
30/* Rx related masks */
31#define UTRSTAT_RX_RELATED_INTS \
32 (UTRSTAT_RX_INT_BIT | UTRSTAT_RX_TOUT_INT_BIT | \
33 UTRSTAT_ERR_INT_BIT | UTRSTAT_AUTOBR_INT_BIT)
34#define UCON_RX_RELATED_INTS \
35 (UCON_RX_INT_BIT | UCON_RX_TOUT_INT_BIT | \
36 UCON_ERR_INT_BIT | UCON_AUTOBR_INT_BIT)
37
38/* Initialization */
39static void uartc_port_id_reset(struct uartc* uartc, int id)
40{
41 uint32_t baddr = UART_PORT_BASE(uartc->baddr, id);
42
43 /* set port registers to default reset values */
44 UCON(baddr) = 0;
45 ULCON(baddr) = 0;
46 UMCON(baddr) = 0;
47 UFCON(baddr) = UFCON_RX_FIFO_RST_BIT | UFCON_TX_FIFO_RST_BIT;
48 /* clear all interrupts */
49 UTRSTAT(baddr) = UTRSTAT_RX_RELATED_INTS
50 | UTRSTAT_TX_INT_BIT
51 | UTRSTAT_MODEM_INT_BIT;
52 UBRDIV(baddr) = 0;
53 UBRCONTX(baddr) = 0;
54 UBRCONRX(baddr) = 0;
55
56 uartc->port_l[id] = (void*)0;
57}
58
59static void uartc_reset(struct uartc* uartc)
60{
61 for (int id = 0; id < UART_PORT_MAX; id++)
62 uartc_port_id_reset(uartc, id);
63}
64
65void uartc_open(struct uartc* uartc)
66 __attribute__((alias("uartc_reset")));
67
68void uartc_close(struct uartc* uartc)
69 __attribute__((alias("uartc_reset")));
70
71void uartc_port_open(struct uartc_port *port)
72{
73 struct uartc *uartc = port->uartc;
74 uint32_t baddr = UART_PORT_BASE(uartc->baddr, port->id);
75
76 port->baddr = baddr;
77 port->utrstat_int_mask = (port->rx_cb ? UTRSTAT_RX_RELATED_INTS : 0)
78 | (port->tx_cb ? UTRSTAT_TX_INT_BIT : 0);
79 port->abr_aborted = 0;
80
81 /* disable Tx/Rx and mask all interrupts */
82 UCON(baddr) = 0;
83
84 /* clear all interrupts */
85 UTRSTAT(baddr) = UTRSTAT_RX_RELATED_INTS
86 | UTRSTAT_TX_INT_BIT
87 | UTRSTAT_MODEM_INT_BIT;
88
89 /* configure registers */
90 UFCON(baddr) = UFCON_FIFO_ENABLE_BIT
91 | UFCON_RX_FIFO_RST_BIT
92 | UFCON_TX_FIFO_RST_BIT
93 | ((port->rx_trg & UFCON_RX_FIFO_TRG_MASK) << UFCON_RX_FIFO_TRG_POS)
94 | ((port->tx_trg & UFCON_TX_FIFO_TRG_MASK) << UFCON_TX_FIFO_TRG_POS);
95
96 UMCON(baddr) = UMCON_RTS_BIT; /* activate nRTS (low level) */
97
98 UCON(baddr) = (UCON_MODE_DISABLED << UCON_RX_MODE_POS)
99 | (UCON_MODE_DISABLED << UCON_TX_MODE_POS)
100 | ((port->clksel & UCON_CLKSEL_MASK) << UCON_CLKSEL_POS)
101 | (port->rx_cb ? UCON_RX_RELATED_INTS|UCON_RX_TOUT_EN_BIT : 0)
102 | (port->tx_cb ? UCON_TX_INT_BIT : 0);
103
104 /* register port on parent controller */
105 uartc->port_l[port->id] = port;
106}
107
108void uartc_port_close(struct uartc_port *port)
109{
110 uartc_port_id_reset(port->uartc, port->id);
111}
112
113/* Configuration */
114void uartc_port_config(struct uartc_port *port, unsigned int speed,
115 uint8_t data_bits, uint8_t parity, uint8_t stop_bits)
116{
117 uint32_t baddr = port->baddr;
118
119 ULCON(baddr) = ((parity & ULCON_PARITY_MASK) << ULCON_PARITY_POS)
120 | ((stop_bits & ULCON_STOP_BITS_MASK) << ULCON_STOP_BITS_POS)
121 | ((data_bits & ULCON_DATA_BITS_MASK) << ULCON_DATA_BITS_POS);
122
123 uartc_port_set_bitrate(port, speed);
124}
125
126void uartc_port_set_bitrate(struct uartc_port *port, unsigned int speed)
127{
128 uint32_t baddr = port->baddr;
129 int uclk = port->clkhz;
130
131 /* Real baud width in UCLK/16 ticks: trunc(UCLK/(16*speed) + 0.5) */
132 int brdiv = (uclk + (speed << 3)) / (speed << 4);
133
134 UBRDIV(baddr) = brdiv - 1;
135
136 /* Fine adjust:
137 *
138 * Along the whole frame, insert/remove "jittered" bauds when needed
139 * to minimize frame lenght accumulated error.
140 *
141 * jitter_width: "jittered" bauds are 1/16 wider/narrower than normal
142 * bauds, so step is 1/16 of real baud width = brdiv (in UCLK ticks)
143 *
144 * baud_err_width: it is the difference between theoric width and real
145 * width = CLK/speed - brdiv*16 (in UCLK ticks)
146 *
147 * Previous widths are scaled by 'speed' factor to simplify operations
148 * and preserve precision using integer operations.
149 */
150 int jitter_width = brdiv * speed;
151 int baud_err_width = uclk - (jitter_width << 4);
152
153 int jitter_incdec = UBRCON_JITTER_INC;
154 if (baud_err_width < 0) {
155 baud_err_width = -baud_err_width;
156 jitter_incdec = UBRCON_JITTER_DEC;
157 }
158
159 int err_width = 0;
160 uint32_t brcon = 0;
161 /* TODO: for (bit < configured frame length) */
162 for (int bit = 0; bit < UC_FRAME_MAX_LEN; bit++) {
163 err_width += baud_err_width;
164 /* adjust to the nearest width */
165 if (jitter_width < (err_width << 1)) {
166 brcon |= jitter_incdec << UBRCON_JITTER_POS(bit);
167 err_width -= jitter_width;
168 }
169 }
170
171 UBRCONRX(baddr) = brcon;
172 UBRCONTX(baddr) = brcon;
173}
174
175/* TODO: uarc_port_set_bitrate_raw() using precalculated values */
176
177/* Select Tx/Rx modes: disabling Tx/Rx resets HW, including
178 FIFOs and shift registers */
179void uartc_port_set_rx_mode(struct uartc_port *port, uint32_t mode)
180{
181 UCON(port->baddr) = (mode << UCON_RX_MODE_POS) |
182 (UCON(port->baddr) & ~(UCON_RX_MODE_MASK << UCON_RX_MODE_POS));
183}
184
185void uartc_port_set_tx_mode(struct uartc_port *port, uint32_t mode)
186{
187 UCON(port->baddr) = (mode << UCON_TX_MODE_POS) |
188 (UCON(port->baddr) & ~(UCON_TX_MODE_MASK << UCON_TX_MODE_POS));
189}
190
191/* Transmit */
192bool uartc_port_tx_ready(struct uartc_port *port)
193{
194 return (UTRSTAT(port->baddr) & UTRSTAT_TXBUF_EMPTY_BIT);
195}
196
197void uartc_port_tx_byte(struct uartc_port *port, uint8_t ch)
198{
199 UTXH(port->baddr) = ch;
200#ifdef UC8702_DEBUG
201 port->n_tx_bytes++;
202#endif
203}
204
205void uartc_port_send_byte(struct uartc_port *port, uint8_t ch)
206{
207 /* wait for transmit buffer empty */
208 while (!uartc_port_tx_ready(port));
209 uartc_port_tx_byte(port, ch);
210}
211
212/* Receive */
213bool uartc_port_rx_ready(struct uartc_port *port)
214{
215 /* test receive buffer data ready */
216 return (UTRSTAT(port->baddr) & UTRSTAT_RXBUF_RDY_BIT);
217}
218
219uint8_t uartc_port_rx_byte(struct uartc_port *port)
220{
221 return URXH(port->baddr) & 0xff;
222}
223
224uint8_t uartc_port_read_byte(struct uartc_port *port)
225{
226 while (!uartc_port_rx_ready(port));
227 return uartc_port_rx_byte(port);
228}
229
230/* Autobauding */
231static inline int uartc_port_abr_status(struct uartc_port *port)
232{
233 return UABRSTAT(port->baddr) & UABRSTAT_STATUS_MASK;
234}
235
236void uartc_port_abr_start(struct uartc_port *port)
237{
238 port->abr_aborted = 0;
239 UCON(port->baddr) |= UCON_AUTOBR_START_BIT;
240}
241
242void uartc_port_abr_stop(struct uartc_port *port)
243{
244 if (uartc_port_abr_status(port) == UABRSTAT_STATUS_COUNTING)
245 /* There is no known way to stop the HW once COUNTING is
246 * in progress.
247 * If we disable AUTOBR_START_BIT now, COUNTING is not
248 * aborted, instead the HW will launch interrupts for
249 * every new rising edge detected while AUTOBR_START_BIT
250 * remains disabled.
251 * If AUTOBR_START_BIT is enabled, the HW will stop by
252 * itself when a rising edge is detected.
253 * So, do not disable AUTOBR_START_BIT and wait for the
254 * next rising edge.
255 */
256 port->abr_aborted = 1;
257 else
258 UCON(port->baddr) &= ~UCON_AUTOBR_START_BIT;
259}
260
261/* ISR */
262void ICODE_ATTR uartc_callback(struct uartc *uartc, int id)
263{
264 struct uartc_port *port = uartc->port_l[id];
265 uint32_t baddr = port->baddr;
266
267 /* filter registered interrupts */
268 uint32_t ints = UTRSTAT(baddr) & port->utrstat_int_mask;
269
270 /* clear interrupts, events ocurring while processing
271 this ISR will be processed in the next call */
272 UTRSTAT(baddr) = ints;
273
274 if (ints & UTRSTAT_RX_RELATED_INTS)
275 {
276 int len = 0;
277 uint32_t abr_cnt = 0;
278
279 if (ints & UTRSTAT_AUTOBR_INT_BIT)
280 {
281 if (uartc_port_abr_status(port) == UABRSTAT_STATUS_COUNTING) {
282 #ifdef UC8702_DEBUG
283 if (UCON(baddr) & UCON_AUTOBR_START_BIT) port->n_abnormal0++;
284 else port->n_abnormal1++;
285 #endif
286 /* try to fix abnormal situations */
287 UCON(baddr) |= UCON_AUTOBR_START_BIT;
288 }
289 else if (!port->abr_aborted)
290 abr_cnt = UABRCNT(baddr);
291 }
292
293 if (ints & (UTRSTAT_RX_RELATED_INTS ^ UTRSTAT_AUTOBR_INT_BIT))
294 {
295 /* get FIFO count */
296 uint32_t ufstat = UFSTAT(baddr);
297 len = (ufstat & UFSTAT_RX_FIFO_CNT_MASK) |
298 ((ufstat & UFSTAT_RX_FIFO_FULL_BIT) >> (8 - 4));
299
300 for (int i = 0; i < len; i++) {
301 /* must read error status first, then data */
302 port->rx_err[i] = UERSTAT(baddr);
303 port->rx_data[i] = URXH(baddr);
304 }
305 }
306
307 /* 'abr_cnt' is zero when no ABR interrupt exists, 'len'
308 * might be zero due to RX_TOUT interrupts are raised by
309 * the hardware even when RX FIFO is empty.
310 * When overrun, it is marked on the first readed error:
311 * overrun = len ? (rx_err[0] & UERSTAT_OVERRUN_BIT) : 0
312 */
313 port->rx_cb(len, port->rx_data, port->rx_err, abr_cnt);
314
315 #ifdef UC8702_DEBUG
316 if (len) {
317 port->n_rx_bytes += len;
318 if (port->rx_err[0] & UERSTAT_OVERRUN_BIT)
319 port->n_ovr_err++;
320 for (int i = 0; i < len; i++) {
321 if (port->rx_err[i] & UERSTAT_PARITY_ERR_BIT)
322 port->n_parity_err++;
323 if (port->rx_err[i] & UERSTAT_FRAME_ERR_BIT)
324 port->n_frame_err++;
325 if (port->rx_err[i] & UERSTAT_BREAK_DETECT_BIT)
326 port->n_break_detect++;
327 }
328 }
329 #endif
330 }
331
332 #if 0
333 /* not used and not tested */
334 if (ints & UTRSTAT_TX_INT_BIT)
335 {
336 port->tx_cb(UART_FIFO_SIZE - ((UFSTAT(baddr) & \
337 UFSTAT_TX_FIFO_CNT_MASK) >> UFSTAT_TX_FIFO_CNT_POS));
338 }
339 #endif
340}
341
342
343#ifdef UC8702_DEBUG
344/*#define LOGF_ENABLE*/
345#include "logf.h"
346
347static int get_bitrate(int uclk, int brdiv, int brcon, int frame_len)
348{
349 logf("get_bitrate(%d, %d, 0x%08x, %d)", uclk, brdiv, brcon, frame_len);
350
351 int avg_speed;
352 int speed_sum = 0;
353 unsigned int frame_width = 0; /* in UCLK clock ticks */
354
355 /* calculate resulting speed for every frame len */
356 for (int bit = 0; bit < frame_len; bit++)
357 {
358 frame_width += brdiv * 16;
359
360 int incdec = ((brcon >> UBRCON_JITTER_POS(bit)) & UBRCON_JITTER_MASK);
361 if (incdec == UBRCON_JITTER_INC) frame_width += brdiv;
362 else if (incdec == UBRCON_JITTER_DEC) frame_width -= brdiv;
363
364 /* speed = truncate((UCLK / (real_frame_width / NBITS)) + 0.5)
365 XXX: overflows for big UCLK */
366 int speed = (((uclk*(bit+1))<<1) + frame_width) / (frame_width<<1);
367 speed_sum += speed;
368 logf(" %d: %c %d", bit, ((incdec == UBRCON_JITTER_INC) ? 'i' :
369 ((incdec == UBRCON_JITTER_DEC) ? 'd' : '.')), speed);
370 }
371
372 /* average of the speed for all frame lengths */
373 avg_speed = speed_sum / frame_len;
374 logf(" avg speed = %d", avg_speed);
375
376 return avg_speed;
377}
378
379void uartc_port_get_line_info(struct uartc_port *port,
380 int *tx_status, int *rx_status,
381 int *tx_speed, int *rx_speed, char *line_cfg)
382{
383 uint32_t baddr = port->baddr;
384
385 uint32_t ucon = UCON(baddr);
386 if (*tx_status)
387 *tx_status = ((ucon >> UCON_TX_MODE_POS) & UCON_TX_MODE_MASK) ? 1 : 0;
388 if (*rx_status)
389 *rx_status = ((ucon >> UCON_RX_MODE_POS) & UCON_RX_MODE_MASK) ? 1 : 0;
390
391 uint32_t ulcon = ULCON(baddr);
392 int n_data = ((ulcon >> ULCON_DATA_BITS_POS) & ULCON_DATA_BITS_MASK) + 5;
393 int n_stop = ((ulcon >> ULCON_STOP_BITS_POS) & ULCON_STOP_BITS_MASK) + 1;
394 int parity = (ulcon >> ULCON_PARITY_POS) & ULCON_PARITY_MASK;
395 int frame_len = 1 + n_data + (parity ? 1 : 0) + n_stop;
396
397 uint32_t brdiv = UBRDIV(baddr) + 1;
398 if (*tx_speed)
399 *tx_speed = get_bitrate(port->clkhz, brdiv, UBRCONTX(baddr), frame_len);
400 if (*rx_speed)
401 *rx_speed = get_bitrate(port->clkhz, brdiv, UBRCONRX(baddr), frame_len);
402
403 if (*line_cfg) {
404 line_cfg[0] = '0' + n_data;
405 line_cfg[1] = ((parity == ULCON_PARITY_NONE) ? 'N' :
406 ((parity == ULCON_PARITY_EVEN) ? 'E' :
407 ((parity == ULCON_PARITY_ODD) ? 'O' :
408 ((parity == ULCON_PARITY_FORCE_1) ? 'M' :
409 ((parity == ULCON_PARITY_FORCE_0) ? 'S' : '?')))));
410 line_cfg[2] = '0' + n_stop;
411 line_cfg[3] = '\0';
412 }
413}
414
415/* Autobauding */
416int uartc_port_get_abr_info(struct uartc_port *port, unsigned int *abr_cnt)
417{
418 int status;
419 uint32_t abr_status;
420 uint32_t baddr = port->baddr;
421
422 int flags = disable_irq_save();
423
424 abr_status = uartc_port_abr_status(port);
425
426 if (UCON(port->baddr) & UCON_AUTOBR_START_BIT) {
427 if (abr_status == UABRSTAT_STATUS_COUNTING)
428 status = ABR_INFO_ST_COUNTING; /* waiting for rising edge */
429 else
430 status = ABR_INFO_ST_LAUNCHED; /* waiting for falling edge */
431 }
432 else {
433 if (abr_status == UABRSTAT_STATUS_COUNTING)
434 status = ABR_INFO_ST_ABNORMAL;
435 else
436 status = ABR_INFO_ST_IDLE;
437 }
438
439 if (*abr_cnt)
440 *abr_cnt = UABRCNT(baddr);
441
442 restore_irq(flags);
443
444 return status;
445}
446#endif /* UC8702_DEBUG */
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