diff options
Diffstat (limited to 'firmware/target/arm/s3c2440')
-rw-r--r-- | firmware/target/arm/s3c2440/system-target.h | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/firmware/target/arm/s3c2440/system-target.h b/firmware/target/arm/s3c2440/system-target.h index 0721feeee4..ad32f89552 100644 --- a/firmware/target/arm/s3c2440/system-target.h +++ b/firmware/target/arm/s3c2440/system-target.h | |||
@@ -27,14 +27,16 @@ | |||
27 | /* NB: These values must match the register settings in s3c2440/crt0.S */ | 27 | /* NB: These values must match the register settings in s3c2440/crt0.S */ |
28 | 28 | ||
29 | #ifdef GIGABEAT_F | 29 | #ifdef GIGABEAT_F |
30 | #define CPUFREQ_DEFAULT 98784000 | 30 | /* MPLLCON = 0x000C9042, 16.9344 MHz refclk, therefore: |
31 | #define CPUFREQ_NORMAL 98784000 | 31 | * MPLL = 294940800 = 2*(201 + 8)*16934400 / ((4 + 2) * 2^2) */ |
32 | #define CPUFREQ_MAX 296352000 | 32 | #define CPUFREQ_DEFAULT 98313600 |
33 | #define CPUFREQ_NORMAL 98313600 | ||
34 | #define CPUFREQ_MAX 294940800 | ||
33 | 35 | ||
34 | /* Uses 1:3:6 */ | 36 | /* Uses 1:3:6 */ |
35 | #define FCLK CPUFREQ_MAX | 37 | #define FCLK CPUFREQ_MAX |
36 | #define HCLK (FCLK/3) /* = 98,784,000 */ | 38 | #define HCLK (FCLK/3) /* = 98,313,600 */ |
37 | #define PCLK (HCLK/2) /* = 49,392,000 */ | 39 | #define PCLK (HCLK/2) /* = 49,156,800 */ |
38 | 40 | ||
39 | #ifdef BOOTLOADER | 41 | #ifdef BOOTLOADER |
40 | /* All addresses within rockbox are in IRAM in the bootloader so | 42 | /* All addresses within rockbox are in IRAM in the bootloader so |