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-rw-r--r--firmware/target/arm/s3c2440/gigabeat-fx/ata-meg-fx.c1
-rw-r--r--firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.c235
-rw-r--r--firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.h35
-rw-r--r--firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c1
-rw-r--r--firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c16
-rw-r--r--firmware/target/arm/s3c2440/gigabeat-fx/system-target.h2
6 files changed, 16 insertions, 274 deletions
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/ata-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/ata-meg-fx.c
index d33bcaaf6e..1f5c5c8fbe 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/ata-meg-fx.c
+++ b/firmware/target/arm/s3c2440/gigabeat-fx/ata-meg-fx.c
@@ -25,7 +25,6 @@
25#include "panic.h" 25#include "panic.h"
26#include "pcf50606.h" 26#include "pcf50606.h"
27#include "ata-target.h" 27#include "ata-target.h"
28#include "mmu-meg-fx.h"
29#include "backlight-target.h" 28#include "backlight-target.h"
30 29
31/* ARESET on C7C68300 and RESET on ATA interface (Active Low) */ 30/* ARESET on C7C68300 and RESET on ATA interface (Active Low) */
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.c
deleted file mode 100644
index c47c1330bc..0000000000
--- a/firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.c
+++ /dev/null
@@ -1,235 +0,0 @@
1#include <string.h>
2#include "s3c2440.h"
3#include "mmu-meg-fx.h"
4#include "panic.h"
5
6static void enable_mmu(void);
7static void set_ttb(void);
8static void set_page_tables(void);
9static void map_section(unsigned int pa, unsigned int va, int mb, int cache_flags);
10
11#define SECTION_ADDRESS_MASK (-1 << 20)
12#define CACHE_ALL (1 << 3 | 1 << 2 )
13#define CACHE_NONE 0
14#define BUFFERED (1 << 2)
15#define MB (1 << 20)
16
17void memory_init(void) {
18 set_ttb();
19 set_page_tables();
20 enable_mmu();
21}
22
23unsigned int* ttb_base = (unsigned int *) TTB_BASE;
24const int ttb_size = 4096;
25
26void set_ttb() {
27 int i;
28 int* ttbPtr;
29 int domain_access;
30
31 /* must be 16Kb (0x4000) aligned */
32 ttb_base = (int*) TTB_BASE;
33 for (i=0; i<ttb_size; i++,ttbPtr++)
34 ttbPtr = 0;
35 asm volatile("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttb_base));
36
37 /* set domain D0 to "client" permission access */
38
39 domain_access = 3;
40 asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (domain_access));
41
42}
43
44void set_page_tables() {
45
46 map_section(0, 0, 0x1000, CACHE_NONE); /* map every memory region to itself */
47 map_section(0x30000000, 0, 32, CACHE_ALL); /* map RAM to 0 and enable caching for it */
48 map_section((int)FRAME, (int)FRAME, 1, BUFFERED); /* enable buffered writing for the framebuffer */
49}
50
51void map_section(unsigned int pa, unsigned int va, int mb, int cache_flags) {
52 unsigned int* ttbPtr;
53 int i;
54 int section_no;
55
56 section_no = va >> 20; /* sections are 1Mb size */
57 ttbPtr = ttb_base + section_no;
58 pa &= SECTION_ADDRESS_MASK; /* align to 1Mb */
59 for(i=0; i<mb; i++, pa += MB) {
60 *(ttbPtr + i) =
61 pa |
62 1 << 10 | /* superuser - r/w, user - no access */
63 0 << 5 | /* domain 0th */
64 1 << 4 | /* should be "1" */
65 cache_flags |
66 1 << 1; /* Section signature */
67 }
68}
69
70static void enable_mmu(void) {
71 int regread;
72
73 asm volatile(
74 "MRC p15, 0, %r0, c1, c0, 0\n" /* Read reg1, control register */
75 : /* outputs */
76 "=r"(regread)
77 : /* inputs */
78 : /* clobbers */
79 "r0"
80 );
81
82 if ( !(regread & 0x04) || !(regread & 0x00001000) ) /* Was the ICache or DCache Enabled? */
83 clean_dcache(); /* If so we need to clean the DCache before invalidating below */
84
85 asm volatile("mov r0, #0\n"
86 "mcr p15, 0, r0, c8, c7, 0\n" /* invalidate TLB */
87
88 "mcr p15, 0, r0, c7, c7,0\n" /* invalidate both icache and dcache */
89
90 "mrc p15, 0, r0, c1, c0, 0\n"
91 "orr r0, r0, #1<<0\n" /* enable mmu bit, icache and dcache */
92 "orr r0, r0, #1<<2\n" /* enable dcache */
93 "orr r0, r0, #1<<12\n" /* enable icache */
94 "mcr p15, 0, r0, c1, c0, 0" : : : "r0");
95 asm volatile("nop \n nop \n nop \n nop");
96}
97
98/* Invalidate DCache for this range */
99/* Will do write back */
100void invalidate_dcache_range(const void *base, unsigned int size) {
101 unsigned int addr = (((int) base) & ~31); /* Align start to cache line*/
102 unsigned int end = ((addr+size) & ~31)+64; /* Align end to cache line, pad */
103 asm volatile(
104"inv_start: \n"
105 "mcr p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
106 "add %0, %0, #32 \n"
107 "cmp %0, %1 \n"
108 "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
109 "addne %0, %0, #32 \n"
110 "cmpne %0, %1 \n"
111 "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
112 "addne %0, %0, #32 \n"
113 "cmpne %0, %1 \n"
114 "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
115 "addne %0, %0, #32 \n"
116 "cmpne %0, %1 \n"
117 "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
118 "addne %0, %0, #32 \n"
119 "cmpne %0, %1 \n"
120 "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
121 "addne %0, %0, #32 \n"
122 "cmpne %0, %1 \n"
123 "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
124 "addne %0, %0, #32 \n"
125 "cmpne %0, %1 \n"
126 "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
127 "addne %0, %0, #32 \n"
128 "cmpne %0, %1 \n"
129 "bne inv_start \n"
130 "mov %0, #0\n"
131 "mcr p15,0,%0,c7,c10,4\n" /* Drain write buffer */
132 : : "r" (addr), "r" (end));
133}
134
135/* clean DCache for this range */
136/* forces DCache writeback for the specified range */
137void clean_dcache_range(const void *base, unsigned int size) {
138 unsigned int addr = (int) base;
139 unsigned int end = addr+size+32;
140 asm volatile(
141 "bic %0, %0, #31 \n"
142"clean_start: \n"
143 "mcr p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
144 "add %0, %0, #32 \n"
145 "cmp %0, %1 \n"
146 "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
147 "addlo %0, %0, #32 \n"
148 "cmplo %0, %1 \n"
149 "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
150 "addlo %0, %0, #32 \n"
151 "cmplo %0, %1 \n"
152 "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
153 "addlo %0, %0, #32 \n"
154 "cmplo %0, %1 \n"
155 "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
156 "addlo %0, %0, #32 \n"
157 "cmplo %0, %1 \n"
158 "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
159 "addlo %0, %0, #32 \n"
160 "cmplo %0, %1 \n"
161 "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
162 "addlo %0, %0, #32 \n"
163 "cmplo %0, %1 \n"
164 "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
165 "addlo %0, %0, #32 \n"
166 "cmplo %0, %1 \n"
167 "blo clean_start \n"
168 "mov %0, #0\n"
169 "mcr p15,0,%0,c7,c10,4 \n" /* Drain write buffer */
170 : : "r" (addr), "r" (end));
171}
172
173/* Dump DCache for this range */
174/* Will *NOT* do write back */
175void dump_dcache_range(const void *base, unsigned int size) {
176 unsigned int addr = (int) base;
177 unsigned int end = addr+size;
178 asm volatile(
179 "tst %0, #31 \n" /* Check to see if low five bits are set */
180 "bic %0, %0, #31 \n" /* Clear them */
181 "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line, if those bits were set */
182 "add %0, %0, #32 \n" /* Move to the next cache line */
183 "tst %1, #31 \n" /* Check last line for bits set */
184 "bic %1, %1, #31 \n" /* Clear those bits */
185 "mcrne p15, 0, %1, c7, c14, 1 \n" /* Clean and invalidate this line, if not cache aligned */
186"dump_start: \n"
187 "mcr p15, 0, %0, c7, c6, 1 \n" /* Invalidate this line */
188 "add %0, %0, #32 \n" /* Next cache line */
189 "cmp %0, %1 \n"
190 "bne dump_start \n"
191"dump_end: \n"
192 "mcr p15,0,%0,c7,c10,4 \n" /* Drain write buffer */
193 : : "r" (addr), "r" (end));
194}
195/* Cleans entire DCache */
196void clean_dcache(void)
197{
198 unsigned int index, addr;
199
200 for(index = 0; index <= 63; index++) {
201 addr = (0 << 5) | (index << 26);
202 asm volatile(
203 "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
204 : : "r" (addr));
205 addr = (1 << 5) | (index << 26);
206 asm volatile(
207 "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
208 : : "r" (addr));
209 addr = (2 << 5) | (index << 26);
210 asm volatile(
211 "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
212 : : "r" (addr));
213 addr = (3 << 5) | (index << 26);
214 asm volatile(
215 "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
216 : : "r" (addr));
217 addr = (4 << 5) | (index << 26);
218 asm volatile(
219 "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
220 : : "r" (addr));
221 addr = (5 << 5) | (index << 26);
222 asm volatile(
223 "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
224 : : "r" (addr));
225 addr = (6 << 5) | (index << 26);
226 asm volatile(
227 "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
228 : : "r" (addr));
229 addr = (7 << 5) | (index << 26);
230 asm volatile(
231 "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
232 : : "r" (addr));
233 }
234}
235
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.h b/firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.h
deleted file mode 100644
index 524978852d..0000000000
--- a/firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2006,2007 by Greg White
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20/* Invalidate DCache for this range */
21/* Will do write back */
22void invalidate_dcache_range(const void *base, unsigned int size);
23
24/* clean DCache for this range */
25/* forces DCache writeback for the specified range */
26void clean_dcache_range(const void *base, unsigned int size);
27
28/* Dump DCache for this range */
29/* Will *NOT* do write back */
30void dump_dcache_range(const void *base, unsigned int size);
31
32/* Cleans entire DCache */
33void clean_dcache(void);
34
35void memory_init(void);
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c
index a38b4e424e..7f25cb6a15 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c
+++ b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c
@@ -23,7 +23,6 @@
23#include "audio.h" 23#include "audio.h"
24#include "sound.h" 24#include "sound.h"
25#include "file.h" 25#include "file.h"
26#include "mmu-meg-fx.h"
27 26
28/* All exact rates for 16.9344MHz clock */ 27/* All exact rates for 16.9344MHz clock */
29#define GIGABEAT_11025HZ (0x19 << 1) 28#define GIGABEAT_11025HZ (0x19 << 1)
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c
index 00cf626ab3..c7b1b77c9f 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c
+++ b/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c
@@ -1,7 +1,8 @@
1#include "kernel.h" 1#include "kernel.h"
2#include "system.h" 2#include "system.h"
3#include "panic.h" 3#include "panic.h"
4#include "mmu-meg-fx.h" 4#include "mmu-arm.h"
5#include "cpu.h"
5 6
6#define default_interrupt(name) \ 7#define default_interrupt(name) \
7 extern __attribute__((weak,alias("UIRQ"))) void name (void) 8 extern __attribute__((weak,alias("UIRQ"))) void name (void)
@@ -90,6 +91,19 @@ void system_reboot(void)
90 ; 91 ;
91} 92}
92 93
94static void set_page_tables(void)
95{
96 map_section(0, 0, 0x1000, CACHE_NONE); /* map every memory region to itself */
97 map_section(0x30000000, 0, 32, CACHE_ALL); /* map RAM to 0 and enable caching for it */
98 map_section((int)FRAME, (int)FRAME, 1, BUFFERED); /* enable buffered writing for the framebuffer */
99}
100
101void memory_init(void) {
102 ttb_init();
103 set_page_tables();
104 enable_mmu();
105}
106
93void system_init(void) 107void system_init(void)
94{ 108{
95 /* Disable interrupts and set all to IRQ mode */ 109 /* Disable interrupts and set all to IRQ mode */
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h b/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h
index 215b5a4daa..2fab652596 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h
+++ b/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h
@@ -19,8 +19,8 @@
19#ifndef SYSTEM_TARGET_H 19#ifndef SYSTEM_TARGET_H
20#define SYSTEM_TARGET_H 20#define SYSTEM_TARGET_H
21 21
22#include "mmu-meg-fx.h"
23#include "system-arm.h" 22#include "system-arm.h"
23#include "mmu-arm.h"
24 24
25#define CPUFREQ_DEFAULT 98784000 25#define CPUFREQ_DEFAULT 98784000
26#define CPUFREQ_NORMAL 98784000 26#define CPUFREQ_NORMAL 98784000
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-19 22:54:19 +0000