diff options
Diffstat (limited to 'firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.c')
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.c | 222 |
1 files changed, 222 insertions, 0 deletions
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.c new file mode 100644 index 0000000000..6142213f0c --- /dev/null +++ b/firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.c | |||
@@ -0,0 +1,222 @@ | |||
1 | #include <string.h> | ||
2 | #include "s3c2440.h" | ||
3 | #include "mmu-meg-fx.h" | ||
4 | #include "panic.h" | ||
5 | |||
6 | void map_memory(void); | ||
7 | static void enable_mmu(void); | ||
8 | static void set_ttb(void); | ||
9 | static void set_page_tables(void); | ||
10 | static void map_section(unsigned int pa, unsigned int va, int mb, int cache_flags); | ||
11 | |||
12 | #define SECTION_ADDRESS_MASK (-1 << 20) | ||
13 | #define CACHE_ALL (1 << 3 | 1 << 2 ) | ||
14 | #define CACHE_NONE 0 | ||
15 | #define BUFFERED (1 << 2) | ||
16 | #define MB (1 << 20) | ||
17 | |||
18 | void map_memory(void) { | ||
19 | set_ttb(); | ||
20 | set_page_tables(); | ||
21 | enable_mmu(); | ||
22 | } | ||
23 | |||
24 | unsigned int* ttb_base = (unsigned int *) TTB_BASE; | ||
25 | const int ttb_size = 4096; | ||
26 | |||
27 | void set_ttb() { | ||
28 | int i; | ||
29 | int* ttbPtr; | ||
30 | int domain_access; | ||
31 | |||
32 | /* must be 16Kb (0x4000) aligned */ | ||
33 | ttb_base = (int*) TTB_BASE; | ||
34 | for (i=0; i<ttb_size; i++,ttbPtr++) | ||
35 | ttbPtr = 0; | ||
36 | asm volatile("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttb_base)); | ||
37 | |||
38 | /* set domain D0 to "client" permission access */ | ||
39 | |||
40 | domain_access = 3; | ||
41 | asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (domain_access)); | ||
42 | |||
43 | } | ||
44 | |||
45 | void set_page_tables() { | ||
46 | |||
47 | map_section(0, 0, 0x1000, CACHE_NONE); /* map every memory region to itself */ | ||
48 | map_section(0x30000000, 0, 32, CACHE_ALL); /* map RAM to 0 and enable caching for it */ | ||
49 | map_section((int)FRAME, (int)FRAME, 1, BUFFERED); /* enable buffered writing for the framebuffer */ | ||
50 | } | ||
51 | |||
52 | void map_section(unsigned int pa, unsigned int va, int mb, int cache_flags) { | ||
53 | unsigned int* ttbPtr; | ||
54 | int i; | ||
55 | int section_no; | ||
56 | |||
57 | section_no = va >> 20; /* sections are 1Mb size */ | ||
58 | ttbPtr = ttb_base + section_no; | ||
59 | pa &= SECTION_ADDRESS_MASK; /* align to 1Mb */ | ||
60 | for(i=0; i<mb; i++, pa += MB) { | ||
61 | *(ttbPtr + i) = | ||
62 | pa | | ||
63 | 1 << 10 | /* superuser - r/w, user - no access */ | ||
64 | 0 << 5 | /* domain 0th */ | ||
65 | 1 << 4 | /* should be "1" */ | ||
66 | cache_flags | | ||
67 | 1 << 1; /* Section signature */ | ||
68 | } | ||
69 | } | ||
70 | |||
71 | static void enable_mmu(void) { | ||
72 | asm volatile("mov r0, #0\n" | ||
73 | "mcr p15, 0, r0, c8, c7, 0\n" /* invalidate TLB */ | ||
74 | |||
75 | "mcr p15, 0, r0, c7, c7,0\n" /* invalidate both icache and dcache */ | ||
76 | |||
77 | "mrc p15, 0, r0, c1, c0, 0\n" | ||
78 | "orr r0, r0, #1<<0\n" /* enable mmu bit, icache and dcache */ | ||
79 | "orr r0, r0, #1<<2\n" /* enable dcache */ | ||
80 | "orr r0, r0, #1<<12\n" /* enable icache */ | ||
81 | "mcr p15, 0, r0, c1, c0, 0" : : : "r0"); | ||
82 | asm volatile("nop \n nop \n nop \n nop"); | ||
83 | } | ||
84 | |||
85 | /* Invalidate DCache for this range */ | ||
86 | /* Will do write back */ | ||
87 | void invalidate_dcache_range(const void *base, unsigned int size) { | ||
88 | unsigned int addr = (((int) base) & ~31); /* Align start to cache line*/ | ||
89 | unsigned int end = ((addr+size) & ~31)+64; /* Align end to cache line, pad */ | ||
90 | asm volatile( | ||
91 | "inv_start: \n" | ||
92 | "mcr p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */ | ||
93 | "add %0, %0, #32 \n" | ||
94 | "cmp %0, %1 \n" | ||
95 | "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */ | ||
96 | "addne %0, %0, #32 \n" | ||
97 | "cmpne %0, %1 \n" | ||
98 | "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */ | ||
99 | "addne %0, %0, #32 \n" | ||
100 | "cmpne %0, %1 \n" | ||
101 | "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */ | ||
102 | "addne %0, %0, #32 \n" | ||
103 | "cmpne %0, %1 \n" | ||
104 | "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */ | ||
105 | "addne %0, %0, #32 \n" | ||
106 | "cmpne %0, %1 \n" | ||
107 | "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */ | ||
108 | "addne %0, %0, #32 \n" | ||
109 | "cmpne %0, %1 \n" | ||
110 | "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */ | ||
111 | "addne %0, %0, #32 \n" | ||
112 | "cmpne %0, %1 \n" | ||
113 | "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */ | ||
114 | "addne %0, %0, #32 \n" | ||
115 | "cmpne %0, %1 \n" | ||
116 | "bne inv_start \n" | ||
117 | "mov %0, #0\n" | ||
118 | "mcr p15,0,%0,c7,c10,4\n" /* Drain write buffer */ | ||
119 | : : "r" (addr), "r" (end)); | ||
120 | } | ||
121 | |||
122 | /* clean DCache for this range */ | ||
123 | /* forces DCache writeback for the specified range */ | ||
124 | void clean_dcache_range(const void *base, unsigned int size) { | ||
125 | unsigned int addr = (int) base; | ||
126 | unsigned int end = addr+size+32; | ||
127 | asm volatile( | ||
128 | "bic %0, %0, #31 \n" | ||
129 | "clean_start: \n" | ||
130 | "mcr p15, 0, %0, c7, c10, 1 \n" /* Clean this line */ | ||
131 | "add %0, %0, #32 \n" | ||
132 | "cmp %0, %1 \n" | ||
133 | "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */ | ||
134 | "addlo %0, %0, #32 \n" | ||
135 | "cmplo %0, %1 \n" | ||
136 | "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */ | ||
137 | "addlo %0, %0, #32 \n" | ||
138 | "cmplo %0, %1 \n" | ||
139 | "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */ | ||
140 | "addlo %0, %0, #32 \n" | ||
141 | "cmplo %0, %1 \n" | ||
142 | "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */ | ||
143 | "addlo %0, %0, #32 \n" | ||
144 | "cmplo %0, %1 \n" | ||
145 | "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */ | ||
146 | "addlo %0, %0, #32 \n" | ||
147 | "cmplo %0, %1 \n" | ||
148 | "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */ | ||
149 | "addlo %0, %0, #32 \n" | ||
150 | "cmplo %0, %1 \n" | ||
151 | "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */ | ||
152 | "addlo %0, %0, #32 \n" | ||
153 | "cmplo %0, %1 \n" | ||
154 | "blo clean_start \n" | ||
155 | "mov %0, #0\n" | ||
156 | "mcr p15,0,%0,c7,c10,4 \n" /* Drain write buffer */ | ||
157 | : : "r" (addr), "r" (end)); | ||
158 | } | ||
159 | |||
160 | /* Dump DCache for this range */ | ||
161 | /* Will *NOT* do write back */ | ||
162 | void dump_dcache_range(const void *base, unsigned int size) { | ||
163 | unsigned int addr = (int) base; | ||
164 | unsigned int end = addr+size; | ||
165 | asm volatile( | ||
166 | "tst %0, #31 \n" /* Check to see if low five bits are set */ | ||
167 | "bic %0, %0, #31 \n" /* Clear them */ | ||
168 | "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line, if those bits were set */ | ||
169 | "add %0, %0, #32 \n" /* Move to the next cache line */ | ||
170 | "tst %1, #31 \n" /* Check last line for bits set */ | ||
171 | "bic %1, %1, #31 \n" /* Clear those bits */ | ||
172 | "mcrne p15, 0, %1, c7, c14, 1 \n" /* Clean and invalidate this line, if not cache aligned */ | ||
173 | "dump_start: \n" | ||
174 | "mcr p15, 0, %0, c7, c6, 1 \n" /* Invalidate this line */ | ||
175 | "add %0, %0, #32 \n" /* Next cache line */ | ||
176 | "cmp %0, %1 \n" | ||
177 | "bne dump_start \n" | ||
178 | "dump_end: \n" | ||
179 | "mcr p15,0,%0,c7,c10,4 \n" /* Drain write buffer */ | ||
180 | : : "r" (addr), "r" (end)); | ||
181 | } | ||
182 | /* Cleans entire DCache */ | ||
183 | void clean_dcache(void) | ||
184 | { | ||
185 | unsigned int index, addr; | ||
186 | |||
187 | for(index = 0; index <= 63; index++) { | ||
188 | addr = (0 << 5) | (index << 26); | ||
189 | asm volatile( | ||
190 | "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */ | ||
191 | : : "r" (addr)); | ||
192 | addr = (1 << 5) | (index << 26); | ||
193 | asm volatile( | ||
194 | "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */ | ||
195 | : : "r" (addr)); | ||
196 | addr = (2 << 5) | (index << 26); | ||
197 | asm volatile( | ||
198 | "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */ | ||
199 | : : "r" (addr)); | ||
200 | addr = (3 << 5) | (index << 26); | ||
201 | asm volatile( | ||
202 | "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */ | ||
203 | : : "r" (addr)); | ||
204 | addr = (4 << 5) | (index << 26); | ||
205 | asm volatile( | ||
206 | "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */ | ||
207 | : : "r" (addr)); | ||
208 | addr = (5 << 5) | (index << 26); | ||
209 | asm volatile( | ||
210 | "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */ | ||
211 | : : "r" (addr)); | ||
212 | addr = (6 << 5) | (index << 26); | ||
213 | asm volatile( | ||
214 | "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */ | ||
215 | : : "r" (addr)); | ||
216 | addr = (7 << 5) | (index << 26); | ||
217 | asm volatile( | ||
218 | "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */ | ||
219 | : : "r" (addr)); | ||
220 | } | ||
221 | } | ||
222 | |||