diff options
Diffstat (limited to 'firmware/target/arm/rk27xx')
-rw-r--r-- | firmware/target/arm/rk27xx/system-rk27xx.c | 55 | ||||
-rw-r--r-- | firmware/target/arm/rk27xx/system-target.h | 5 |
2 files changed, 58 insertions, 2 deletions
diff --git a/firmware/target/arm/rk27xx/system-rk27xx.c b/firmware/target/arm/rk27xx/system-rk27xx.c index 1b4505541f..8c75deef07 100644 --- a/firmware/target/arm/rk27xx/system-rk27xx.c +++ b/firmware/target/arm/rk27xx/system-rk27xx.c | |||
@@ -231,3 +231,58 @@ void commit_discard_dcache_range (const void *base, unsigned int size) | |||
231 | opcode += 32; | 231 | opcode += 32; |
232 | } | 232 | } |
233 | } | 233 | } |
234 | |||
235 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ | ||
236 | static inline void set_sdram_timing(int ahb_freq) | ||
237 | { | ||
238 | MCSDR_T_REF = (125*ahb_freq/1000000) >> 3; | ||
239 | MCSDR_T_RFC = (64*ahb_freq/1000000)/1000; | ||
240 | } | ||
241 | |||
242 | void set_cpu_frequency(long frequency) | ||
243 | { | ||
244 | if (cpu_frequency == frequency) | ||
245 | return; | ||
246 | |||
247 | set_sdram_timing(12000000); | ||
248 | |||
249 | if (frequency == CPUFREQ_MAX) | ||
250 | { | ||
251 | /* PLL set to 200 Mhz | ||
252 | * PLL:ARM = 1:1 | ||
253 | * ARM:AHB = 2:1 | ||
254 | * AHB:APB = 2:1 | ||
255 | */ | ||
256 | SCU_DIVCON1 = (SCU_DIVCON1 &~ 0x1f) | (1<<3)|1; | ||
257 | SCU_PLLCON1 = ((1<<24)|(1<<23)|(5<<16)|(49<<4)); /*((24/6)*50)/1*/ | ||
258 | |||
259 | /* wait for PLL lock ~0.3 ms */ | ||
260 | while (!(SCU_STATUS & 1)); | ||
261 | |||
262 | /* leave SLOW mode */ | ||
263 | SCU_DIVCON1 &= ~1; | ||
264 | |||
265 | set_sdram_timing(CPUFREQ_MAX/2); | ||
266 | } | ||
267 | else | ||
268 | { | ||
269 | /* PLL set to 100 MHz | ||
270 | * PLL:ARM = 2:1 | ||
271 | * ARM:AHB = 1:1 | ||
272 | * AHB:APB = 1:1 | ||
273 | */ | ||
274 | SCU_DIVCON1 = (SCU_DIVCON1 & ~0x1f) | (1<<2)|1; | ||
275 | SCU_PLLCON1 = ((1<<24)|(1<<23)|(5<<16)|(49<<4)|(1<<1)); /*((24/6)*50)/2*/ | ||
276 | |||
277 | /* wait for PLL lock ~0.3 ms */ | ||
278 | while (!(SCU_STATUS & 1)); | ||
279 | |||
280 | /* leave SLOW mode */ | ||
281 | SCU_DIVCON1 &= ~1; | ||
282 | |||
283 | set_sdram_timing(CPUFREQ_NORMAL); | ||
284 | } | ||
285 | |||
286 | cpu_frequency = frequency; | ||
287 | } | ||
288 | #endif | ||
diff --git a/firmware/target/arm/rk27xx/system-target.h b/firmware/target/arm/rk27xx/system-target.h index 730686549d..8a705dd77a 100644 --- a/firmware/target/arm/rk27xx/system-target.h +++ b/firmware/target/arm/rk27xx/system-target.h | |||
@@ -48,7 +48,8 @@ static inline void commit_dcache(void) {} | |||
48 | void commit_discard_dcache(void); | 48 | void commit_discard_dcache(void); |
49 | void commit_discard_idcache(void); | 49 | void commit_discard_idcache(void); |
50 | 50 | ||
51 | #define CPUFREQ_NORMAL 200000000 | 51 | #define CPUFREQ_DEFAULT 50000000 |
52 | #define CPUFREQ_MAX 200000000 | 52 | #define CPUFREQ_NORMAL 50000000 |
53 | #define CPUFREQ_MAX 200000000 | ||
53 | 54 | ||
54 | #endif /* SYSTEM_TARGET_H */ | 55 | #endif /* SYSTEM_TARGET_H */ |