diff options
Diffstat (limited to 'firmware/target/arm/rk27xx/kernel-rk27xx.c')
-rw-r--r-- | firmware/target/arm/rk27xx/kernel-rk27xx.c | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/firmware/target/arm/rk27xx/kernel-rk27xx.c b/firmware/target/arm/rk27xx/kernel-rk27xx.c new file mode 100644 index 0000000000..d54a09dd1f --- /dev/null +++ b/firmware/target/arm/rk27xx/kernel-rk27xx.c | |||
@@ -0,0 +1,54 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2011 by Marcin Bukat | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #include "config.h" | ||
22 | #include "system.h" | ||
23 | #include "kernel.h" | ||
24 | |||
25 | /* rockchip rk27xx driver for the kernel timer */ | ||
26 | |||
27 | /* sys timer ISR */ | ||
28 | void INT_TIMER0(void) | ||
29 | { | ||
30 | /* clear interrupt */ | ||
31 | TMR0CON &= ~0x04; | ||
32 | |||
33 | call_tick_tasks(); /* Run through the list of tick tasks */ | ||
34 | } | ||
35 | |||
36 | /* this assumes 50MHz APB bus frequency */ | ||
37 | void tick_start(unsigned int interval_in_ms) | ||
38 | { | ||
39 | unsigned int cycles = 50000 * interval_in_ms; | ||
40 | |||
41 | /* enable timer clock */ | ||
42 | SCU_CLKCFG &= (1<<28); | ||
43 | |||
44 | /* configure timer0 */ | ||
45 | TMR0LR = cycles; | ||
46 | TMR0CON = (1<<8) | (1<<7) | (1<<1); /* periodic, 1/1, interrupt enable */ | ||
47 | |||
48 | /* unmask timer0 interrupt */ | ||
49 | INTC_IMR |= 0x04; | ||
50 | |||
51 | /* enable timer0 interrupt */ | ||
52 | INTC_IECR |= 0x04; | ||
53 | } | ||
54 | |||